1*51cb23d4SPatrice Chotard #ifndef _ST_PINCFG_H_ 2*51cb23d4SPatrice Chotard #define _ST_PINCFG_H_ 3*51cb23d4SPatrice Chotard 4*51cb23d4SPatrice Chotard /* Alternate functions */ 5*51cb23d4SPatrice Chotard #define ALT1 1 6*51cb23d4SPatrice Chotard #define ALT2 2 7*51cb23d4SPatrice Chotard #define ALT3 3 8*51cb23d4SPatrice Chotard #define ALT4 4 9*51cb23d4SPatrice Chotard #define ALT5 5 10*51cb23d4SPatrice Chotard #define ALT6 6 11*51cb23d4SPatrice Chotard #define ALT7 7 12*51cb23d4SPatrice Chotard 13*51cb23d4SPatrice Chotard /* Output enable */ 14*51cb23d4SPatrice Chotard #define OE (1 << 27) 15*51cb23d4SPatrice Chotard /* Pull Up */ 16*51cb23d4SPatrice Chotard #define PU (1 << 26) 17*51cb23d4SPatrice Chotard /* Open Drain */ 18*51cb23d4SPatrice Chotard #define OD (1 << 25) 19*51cb23d4SPatrice Chotard #define RT (1 << 23) 20*51cb23d4SPatrice Chotard #define INVERTCLK (1 << 22) 21*51cb23d4SPatrice Chotard #define CLKNOTDATA (1 << 21) 22*51cb23d4SPatrice Chotard #define DOUBLE_EDGE (1 << 20) 23*51cb23d4SPatrice Chotard #define CLK_A (0 << 18) 24*51cb23d4SPatrice Chotard #define CLK_B (1 << 18) 25*51cb23d4SPatrice Chotard #define CLK_C (2 << 18) 26*51cb23d4SPatrice Chotard #define CLK_D (3 << 18) 27*51cb23d4SPatrice Chotard 28*51cb23d4SPatrice Chotard /* User-frendly defines for Pin Direction */ 29*51cb23d4SPatrice Chotard /* oe = 0, pu = 0, od = 0 */ 30*51cb23d4SPatrice Chotard #define IN (0) 31*51cb23d4SPatrice Chotard /* oe = 0, pu = 1, od = 0 */ 32*51cb23d4SPatrice Chotard #define IN_PU (PU) 33*51cb23d4SPatrice Chotard /* oe = 1, pu = 0, od = 0 */ 34*51cb23d4SPatrice Chotard #define OUT (OE) 35*51cb23d4SPatrice Chotard /* oe = 1, pu = 0, od = 1 */ 36*51cb23d4SPatrice Chotard #define BIDIR (OE | OD) 37*51cb23d4SPatrice Chotard /* oe = 1, pu = 1, od = 1 */ 38*51cb23d4SPatrice Chotard #define BIDIR_PU (OE | PU | OD) 39*51cb23d4SPatrice Chotard 40*51cb23d4SPatrice Chotard /* RETIME_TYPE */ 41*51cb23d4SPatrice Chotard /* 42*51cb23d4SPatrice Chotard * B Mode 43*51cb23d4SPatrice Chotard * Bypass retime with optional delay parameter 44*51cb23d4SPatrice Chotard */ 45*51cb23d4SPatrice Chotard #define BYPASS (0) 46*51cb23d4SPatrice Chotard /* 47*51cb23d4SPatrice Chotard * R0, R1, R0D, R1D modes 48*51cb23d4SPatrice Chotard * single-edge data non inverted clock, retime data with clk 49*51cb23d4SPatrice Chotard */ 50*51cb23d4SPatrice Chotard #define SE_NICLK_IO (RT) 51*51cb23d4SPatrice Chotard /* 52*51cb23d4SPatrice Chotard * RIV0, RIV1, RIV0D, RIV1D modes 53*51cb23d4SPatrice Chotard * single-edge data inverted clock, retime data with clk 54*51cb23d4SPatrice Chotard */ 55*51cb23d4SPatrice Chotard #define SE_ICLK_IO (RT | INVERTCLK) 56*51cb23d4SPatrice Chotard /* 57*51cb23d4SPatrice Chotard * R0E, R1E, R0ED, R1ED modes 58*51cb23d4SPatrice Chotard * double-edge data, retime data with clk 59*51cb23d4SPatrice Chotard */ 60*51cb23d4SPatrice Chotard #define DE_IO (RT | DOUBLE_EDGE) 61*51cb23d4SPatrice Chotard /* 62*51cb23d4SPatrice Chotard * CIV0, CIV1 modes with inverted clock 63*51cb23d4SPatrice Chotard * Retiming the clk pins will park clock & reduce the noise within the core. 64*51cb23d4SPatrice Chotard */ 65*51cb23d4SPatrice Chotard #define ICLK (RT | CLKNOTDATA | INVERTCLK) 66*51cb23d4SPatrice Chotard /* 67*51cb23d4SPatrice Chotard * CLK0, CLK1 modes with non-inverted clock 68*51cb23d4SPatrice Chotard * Retiming the clk pins will park clock & reduce the noise within the core. 69*51cb23d4SPatrice Chotard */ 70*51cb23d4SPatrice Chotard #define NICLK (RT | CLKNOTDATA) 71*51cb23d4SPatrice Chotard #endif /* _ST_PINCFG_H_ */ 72