1*46787734SManivannan Sadhasivam// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*46787734SManivannan Sadhasivam/* 3*46787734SManivannan Sadhasivam * Copyright (c) 2018 Collabora Ltd. 4*46787734SManivannan Sadhasivam * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 5*46787734SManivannan Sadhasivam * 6*46787734SManivannan Sadhasivam * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw 7*46787734SManivannan Sadhasivam */ 8*46787734SManivannan Sadhasivam 9*46787734SManivannan Sadhasivam/dts-v1/; 10*46787734SManivannan Sadhasivam#include "rk3399-rock960.dtsi" 11*46787734SManivannan Sadhasivam#include "rk3399-sdram-ddr3-1600.dtsi" 12*46787734SManivannan Sadhasivam 13*46787734SManivannan Sadhasivam/ { 14*46787734SManivannan Sadhasivam model = "96boards RK3399 Ficus"; 15*46787734SManivannan Sadhasivam compatible = "vamrs,ficus", "rockchip,rk3399"; 16*46787734SManivannan Sadhasivam 17*46787734SManivannan Sadhasivam chosen { 18*46787734SManivannan Sadhasivam stdout-path = "serial2:1500000n8"; 19*46787734SManivannan Sadhasivam }; 20*46787734SManivannan Sadhasivam 21*46787734SManivannan Sadhasivam clkin_gmac: external-gmac-clock { 22*46787734SManivannan Sadhasivam compatible = "fixed-clock"; 23*46787734SManivannan Sadhasivam clock-frequency = <125000000>; 24*46787734SManivannan Sadhasivam clock-output-names = "clkin_gmac"; 25*46787734SManivannan Sadhasivam #clock-cells = <0>; 26*46787734SManivannan Sadhasivam }; 27*46787734SManivannan Sadhasivam}; 28*46787734SManivannan Sadhasivam 29*46787734SManivannan Sadhasivam&gmac { 30*46787734SManivannan Sadhasivam assigned-clocks = <&cru SCLK_RMII_SRC>; 31*46787734SManivannan Sadhasivam assigned-clock-parents = <&clkin_gmac>; 32*46787734SManivannan Sadhasivam clock_in_out = "input"; 33*46787734SManivannan Sadhasivam phy-supply = <&vcc3v3_sys>; 34*46787734SManivannan Sadhasivam phy-mode = "rgmii"; 35*46787734SManivannan Sadhasivam pinctrl-names = "default"; 36*46787734SManivannan Sadhasivam pinctrl-0 = <&rgmii_pins>; 37*46787734SManivannan Sadhasivam snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 38*46787734SManivannan Sadhasivam snps,reset-active-low; 39*46787734SManivannan Sadhasivam snps,reset-delays-us = <0 10000 50000>; 40*46787734SManivannan Sadhasivam tx_delay = <0x28>; 41*46787734SManivannan Sadhasivam rx_delay = <0x11>; 42*46787734SManivannan Sadhasivam status = "okay"; 43*46787734SManivannan Sadhasivam}; 44*46787734SManivannan Sadhasivam 45*46787734SManivannan Sadhasivam&pcie0 { 46*46787734SManivannan Sadhasivam ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; 47*46787734SManivannan Sadhasivam}; 48*46787734SManivannan Sadhasivam 49*46787734SManivannan Sadhasivam&pinctrl { 50*46787734SManivannan Sadhasivam gmac { 51*46787734SManivannan Sadhasivam rgmii_sleep_pins: rgmii-sleep-pins { 52*46787734SManivannan Sadhasivam rockchip,pins = 53*46787734SManivannan Sadhasivam <3 15 RK_FUNC_GPIO &pcfg_output_low>; 54*46787734SManivannan Sadhasivam }; 55*46787734SManivannan Sadhasivam }; 56*46787734SManivannan Sadhasivam 57*46787734SManivannan Sadhasivam pcie { 58*46787734SManivannan Sadhasivam pcie_drv: pcie-drv { 59*46787734SManivannan Sadhasivam rockchip,pins = 60*46787734SManivannan Sadhasivam <1 24 RK_FUNC_GPIO &pcfg_pull_none>; 61*46787734SManivannan Sadhasivam }; 62*46787734SManivannan Sadhasivam }; 63*46787734SManivannan Sadhasivam 64*46787734SManivannan Sadhasivam usb2 { 65*46787734SManivannan Sadhasivam host_vbus_drv: host-vbus-drv { 66*46787734SManivannan Sadhasivam rockchip,pins = 67*46787734SManivannan Sadhasivam <4 27 RK_FUNC_GPIO &pcfg_pull_none>; 68*46787734SManivannan Sadhasivam }; 69*46787734SManivannan Sadhasivam }; 70*46787734SManivannan Sadhasivam}; 71*46787734SManivannan Sadhasivam 72*46787734SManivannan Sadhasivam&vcc3v3_pcie { 73*46787734SManivannan Sadhasivam gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; 74*46787734SManivannan Sadhasivam}; 75*46787734SManivannan Sadhasivam 76*46787734SManivannan Sadhasivam&vcc5v0_host { 77*46787734SManivannan Sadhasivam gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 78*46787734SManivannan Sadhasivam}; 79