1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53", "arm,armv8"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39// clocks = <&cru ARMCLK>; 40 operating-points-v2 = <&cpu0_opp_table>; 41 }; 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0x0 0x1>; 46 enable-method = "psci"; 47 }; 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x2>; 52 enable-method = "psci"; 53 }; 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53", "arm,armv8"; 57 reg = <0x0 0x3>; 58 enable-method = "psci"; 59 }; 60 }; 61 62 cpu0_opp_table: opp_table0 { 63 compatible = "operating-points-v2"; 64 opp-shared; 65 66 opp@408000000 { 67 opp-hz = /bits/ 64 <408000000>; 68 opp-microvolt = <950000>; 69 clock-latency-ns = <40000>; 70 opp-suspend; 71 }; 72 opp@600000000 { 73 opp-hz = /bits/ 64 <600000000>; 74 opp-microvolt = <950000>; 75 clock-latency-ns = <40000>; 76 }; 77 opp@816000000 { 78 opp-hz = /bits/ 64 <816000000>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <40000>; 81 }; 82 opp@1008000000 { 83 opp-hz = /bits/ 64 <1008000000>; 84 opp-microvolt = <1100000>; 85 clock-latency-ns = <40000>; 86 }; 87 opp@1200000000 { 88 opp-hz = /bits/ 64 <1200000000>; 89 opp-microvolt = <1225000>; 90 clock-latency-ns = <40000>; 91 }; 92 opp@1296000000 { 93 opp-hz = /bits/ 64 <1296000000>; 94 opp-microvolt = <1300000>; 95 clock-latency-ns = <40000>; 96 }; 97 }; 98 99 arm-pmu { 100 compatible = "arm,cortex-a53-pmu"; 101 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0"; 110 method = "smc"; 111 }; 112 113 timer { 114 compatible = "arm,armv8-timer"; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 119 }; 120 121 xin24m: xin24m { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <24000000>; 125 clock-output-names = "xin24m"; 126 }; 127 128 i2s0: i2s@ff000000 { 129 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 130 reg = <0x0 0xff000000 0x0 0x1000>; 131 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 133 clock-names = "i2s_clk", "i2s_hclk"; 134 dmas = <&dmac 11>, <&dmac 12>; 135 #dma-cells = <2>; 136 dma-names = "tx", "rx"; 137 status = "disabled"; 138 }; 139 140 i2s1: i2s@ff010000 { 141 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 142 reg = <0x0 0xff010000 0x0 0x1000>; 143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 145 clock-names = "i2s_clk", "i2s_hclk"; 146 dmas = <&dmac 14>, <&dmac 15>; 147 #dma-cells = <2>; 148 dma-names = "tx", "rx"; 149 status = "disabled"; 150 }; 151 152 i2s2: i2s@ff020000 { 153 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 154 reg = <0x0 0xff020000 0x0 0x1000>; 155 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 157 clock-names = "i2s_clk", "i2s_hclk"; 158 dmas = <&dmac 0>, <&dmac 1>; 159 #dma-cells = <2>; 160 dma-names = "tx", "rx"; 161 pinctrl-names = "default", "sleep"; 162 pinctrl-0 = <&i2s2m0_mclk 163 &i2s2m0_sclk 164 &i2s2m0_lrcktx 165 &i2s2m0_lrckrx 166 &i2s2m0_sdo 167 &i2s2m0_sdi>; 168 pinctrl-1 = <&i2s2m0_sleep>; 169 status = "disabled"; 170 }; 171 172 spdif: spdif@ff030000 { 173 compatible = "rockchip,rk3328-spdif"; 174 reg = <0x0 0xff030000 0x0 0x1000>; 175 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 177 clock-names = "mclk", "hclk"; 178 dmas = <&dmac 10>; 179 #dma-cells = <1>; 180 dma-names = "tx"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&spdifm2_tx>; 183 status = "disabled"; 184 }; 185 186 grf: syscon@ff100000 { 187 u-boot,dm-pre-reloc; 188 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 189 reg = <0x0 0xff100000 0x0 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 193 io_domains: io-domains { 194 compatible = "rockchip,rk3328-io-voltage-domain"; 195 status = "disabled"; 196 }; 197 }; 198 199 uart0: serial@ff110000 { 200 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 201 reg = <0x0 0xff110000 0x0 0x100>; 202 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 204 clock-names = "baudclk", "apb_pclk"; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 dmas = <&dmac 2>, <&dmac 3>; 208 #dma-cells = <2>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 211 status = "disabled"; 212 }; 213 214 uart1: serial@ff120000 { 215 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 216 reg = <0x0 0xff120000 0x0 0x100>; 217 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 219 clock-names = "sclk_uart", "pclk_uart"; 220 reg-shift = <2>; 221 reg-io-width = <4>; 222 dmas = <&dmac 4>, <&dmac 5>; 223 #dma-cells = <2>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 226 status = "disabled"; 227 }; 228 229 uart2: serial@ff130000 { 230 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 231 reg = <0x0 0xff130000 0x0 0x100>; 232 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 234 clock-names = "baudclk", "apb_pclk"; 235 clock-frequency = <24000000>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 dmas = <&dmac 6>, <&dmac 7>; 239 #dma-cells = <2>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&uart2m1_xfer>; 242 status = "disabled"; 243 }; 244 245 pmu: power-management@ff140000 { 246 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 247 reg = <0x0 0xff140000 0x0 0x1000>; 248 }; 249 250 i2c0: i2c@ff150000 { 251 compatible = "rockchip,rk3328-i2c"; 252 reg = <0x0 0xff150000 0x0 0x1000>; 253 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 257 clock-names = "i2c", "pclk"; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&i2c0_xfer>; 260 status = "disabled"; 261 }; 262 263 i2c1: i2c@ff160000 { 264 compatible = "rockchip,rk3328-i2c"; 265 reg = <0x0 0xff160000 0x0 0x1000>; 266 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 270 clock-names = "i2c", "pclk"; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&i2c1_xfer>; 273 status = "disabled"; 274 }; 275 276 i2c2: i2c@ff170000 { 277 compatible = "rockchip,rk3328-i2c"; 278 reg = <0x0 0xff170000 0x0 0x1000>; 279 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 283 clock-names = "i2c", "pclk"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&i2c2_xfer>; 286 status = "disabled"; 287 }; 288 289 i2c3: i2c@ff180000 { 290 compatible = "rockchip,rk3328-i2c"; 291 reg = <0x0 0xff180000 0x0 0x1000>; 292 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 296 clock-names = "i2c", "pclk"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c3_xfer>; 299 status = "disabled"; 300 }; 301 302 spi0: spi@ff190000 { 303 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 304 reg = <0x0 0xff190000 0x0 0x1000>; 305 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 309 clock-names = "spiclk", "apb_pclk"; 310 dmas = <&dmac 8>, <&dmac 9>; 311 #dma-cells = <2>; 312 dma-names = "tx", "rx"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 315 status = "disabled"; 316 }; 317 318 wdt: watchdog@ff1a0000 { 319 compatible = "snps,dw-wdt"; 320 reg = <0x0 0xff1a0000 0x0 0x100>; 321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 322 status = "disabled"; 323 }; 324 325 amba { 326 compatible = "simple-bus"; 327 #address-cells = <2>; 328 #size-cells = <2>; 329 ranges; 330 331 dmac: dmac@ff1f0000 { 332 compatible = "arm,pl330", "arm,primecell"; 333 reg = <0x0 0xff1f0000 0x0 0x4000>; 334 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cru ACLK_DMAC>; 337 clock-names = "apb_pclk"; 338 #dma-cells = <1>; 339 }; 340 }; 341 342 saradc: saradc@ff280000 { 343 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 344 reg = <0x0 0xff280000 0x0 0x100>; 345 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 346 #io-channel-cells = <1>; 347 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 348 clock-names = "saradc", "apb_pclk"; 349 resets = <&cru SRST_SARADC_P>; 350 reset-names = "saradc-apb"; 351 status = "disabled"; 352 }; 353 354 dmc: dmc@ff400000 { 355 u-boot,dm-pre-reloc; 356 compatible = "rockchip,rk3328-dmc", "syscon"; 357 reg = <0x0 0xff400000 0x0 0x1000>; 358 }; 359 360 cru: clock-controller@ff440000 { 361 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 362 reg = <0x0 0xff440000 0x0 0x1000>; 363 rockchip,grf = <&grf>; 364 #clock-cells = <1>; 365 #reset-cells = <1>; 366 assigned-clocks = 367 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 368 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 369 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 370 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 371 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 372 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 373 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 374 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 375 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 376 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 377 <&cru SCLK_WIFI>, <&cru ARMCLK>, 378 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 379 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 380 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 381 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 382 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 383 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 384 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 385 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 386 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 387 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 388 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 389 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 390 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 391 assigned-clock-parents = 392 <&cru HDMIPHY>, <&cru PLL_APLL>, 393 <&cru PLL_GPLL>, <&xin24m>, 394 <&xin24m>, <&xin24m>; 395 assigned-clock-rates = 396 <0>, <61440000>, 397 <0>, <24000000>, 398 <24000000>, <24000000>, 399 <15000000>, <15000000>, 400 <100000000>, <100000000>, 401 <100000000>, <100000000>, 402 <50000000>, <100000000>, 403 <100000000>, <100000000>, 404 <50000000>, <50000000>, 405 <50000000>, <50000000>, 406 <24000000>, <600000000>, 407 <491520000>, <1200000000>, 408 <150000000>, <75000000>, 409 <75000000>, <150000000>, 410 <75000000>, <75000000>, 411 <300000000>, <100000000>, 412 <300000000>, <200000000>, 413 <400000000>, <500000000>, 414 <200000000>, <300000000>, 415 <300000000>, <250000000>, 416 <200000000>, <100000000>, 417 <24000000>, <100000000>, 418 <150000000>, <50000000>, 419 <32768>, <32768>; 420 }; 421 422 sdmmc: rksdmmc@ff500000 { 423 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 424 reg = <0x0 0xff500000 0x0 0x4000>; 425 max-frequency = <150000000>; 426 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 427 clock-names = "biu", "ciu"; 428 fifo-depth = <0x100>; 429 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 430 status = "disabled"; 431 }; 432 433 sdio: dwmmc@ff510000 { 434 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 435 reg = <0x0 0xff510000 0x0 0x4000>; 436 max-frequency = <150000000>; 437 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 438 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 439 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 440 fifo-depth = <0x100>; 441 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 442 status = "disabled"; 443 }; 444 445 emmc: rksdmmc@ff520000 { 446 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 447 reg = <0x0 0xff520000 0x0 0x4000>; 448 max-frequency = <150000000>; 449 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 450 clock-names = "biu", "ciu"; 451 fifo-depth = <0x100>; 452 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 453 status = "disabled"; 454 }; 455 456 usb_host0_ehci: usb@ff5c0000 { 457 compatible = "generic-ehci"; 458 reg = <0x0 0xff5c0000 0x0 0x10000>; 459 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 460 status = "disabled"; 461 }; 462 463 usb_host0_ohci: usb@ff5d0000 { 464 compatible = "generic-ohci"; 465 reg = <0x0 0xff5d0000 0x0 0x10000>; 466 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 467 status = "disabled"; 468 }; 469 470 usb20_otg: usb@ff580000 { 471 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 472 "snps,dwc2"; 473 reg = <0x0 0xff580000 0x0 0x40000>; 474 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 475 hnp-srp-disable; 476 dr_mode = "otg"; 477 status = "disabled"; 478 }; 479 480 sdmmc_ext: rksdmmc@ff5f0000 { 481 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 482 reg = <0x0 0xff5f0000 0x0 0x4000>; 483 max-frequency = <150000000>; 484 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 485 clock-names = "biu", "ciu"; 486 fifo-depth = <0x100>; 487 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 488 status = "disabled"; 489 }; 490 491 usb_host0_xhci: usb@ff600000 { 492 compatible = "rockchip,rk3328-xhci"; 493 reg = <0x0 0xff600000 0x0 0x100000>; 494 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 495 snps,dis-enblslpm-quirk; 496 snps,phyif-utmi-bits = <16>; 497 snps,dis-u2-freeclk-exists-quirk; 498 snps,dis-u2-susphy-quirk; 499 status = "disabled"; 500 }; 501 502 gic: interrupt-controller@ffb70000 { 503 compatible = "arm,gic-400"; 504 #interrupt-cells = <3>; 505 #address-cells = <0>; 506 interrupt-controller; 507 reg = <0x0 0xff811000 0 0x1000>, 508 <0x0 0xff812000 0 0x2000>, 509 <0x0 0xff814000 0 0x2000>, 510 <0x0 0xff816000 0 0x2000>; 511 interrupts = <GIC_PPI 9 512 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 513 }; 514 515 pinctrl: pinctrl { 516 compatible = "rockchip,rk3328-pinctrl"; 517 rockchip,grf = <&grf>; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges; 521 522 gpio0: gpio0@ff210000 { 523 compatible = "rockchip,gpio-bank"; 524 reg = <0x0 0xff210000 0x0 0x100>; 525 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cru PCLK_GPIO0>; 527 528 gpio-controller; 529 #gpio-cells = <2>; 530 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 }; 534 535 gpio1: gpio1@ff220000 { 536 compatible = "rockchip,gpio-bank"; 537 reg = <0x0 0xff220000 0x0 0x100>; 538 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cru PCLK_GPIO1>; 540 541 gpio-controller; 542 #gpio-cells = <2>; 543 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 548 gpio2: gpio2@ff230000 { 549 compatible = "rockchip,gpio-bank"; 550 reg = <0x0 0xff230000 0x0 0x100>; 551 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cru PCLK_GPIO2>; 553 554 gpio-controller; 555 #gpio-cells = <2>; 556 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 561 gpio3: gpio3@ff240000 { 562 compatible = "rockchip,gpio-bank"; 563 reg = <0x0 0xff240000 0x0 0x100>; 564 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cru PCLK_GPIO3>; 566 567 gpio-controller; 568 #gpio-cells = <2>; 569 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 }; 573 574 pcfg_pull_up: pcfg-pull-up { 575 bias-pull-up; 576 }; 577 578 pcfg_pull_down: pcfg-pull-down { 579 bias-pull-down; 580 }; 581 582 pcfg_pull_none: pcfg-pull-none { 583 bias-disable; 584 }; 585 586 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 587 bias-disable; 588 drive-strength = <2>; 589 }; 590 591 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 592 bias-pull-up; 593 drive-strength = <2>; 594 }; 595 596 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 597 bias-pull-up; 598 drive-strength = <4>; 599 }; 600 601 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 602 bias-disable; 603 drive-strength = <4>; 604 }; 605 606 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 607 bias-pull-down; 608 drive-strength = <4>; 609 }; 610 611 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 612 bias-disable; 613 drive-strength = <8>; 614 }; 615 616 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 617 bias-pull-up; 618 drive-strength = <8>; 619 }; 620 621 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 622 bias-disable; 623 drive-strength = <12>; 624 }; 625 626 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 627 bias-pull-up; 628 drive-strength = <12>; 629 }; 630 631 pcfg_output_high: pcfg-output-high { 632 output-high; 633 }; 634 635 pcfg_output_low: pcfg-output-low { 636 output-low; 637 }; 638 639 pcfg_input_high: pcfg-input-high { 640 bias-pull-up; 641 input-enable; 642 }; 643 644 pcfg_input: pcfg-input { 645 input-enable; 646 }; 647 648 i2c0 { 649 i2c0_xfer: i2c0-xfer { 650 rockchip,pins = 651 <2 24 RK_FUNC_1 &pcfg_pull_none>, 652 <2 25 RK_FUNC_1 &pcfg_pull_none>; 653 }; 654 }; 655 656 i2c1 { 657 i2c1_xfer: i2c1-xfer { 658 rockchip,pins = 659 <2 4 RK_FUNC_2 &pcfg_pull_none>, 660 <2 5 RK_FUNC_2 &pcfg_pull_none>; 661 }; 662 }; 663 664 i2c2 { 665 i2c2_xfer: i2c2-xfer { 666 rockchip,pins = 667 <2 13 RK_FUNC_1 &pcfg_pull_none>, 668 <2 14 RK_FUNC_1 &pcfg_pull_none>; 669 }; 670 }; 671 672 i2c3 { 673 i2c3_xfer: i2c3-xfer { 674 rockchip,pins = 675 <0 5 RK_FUNC_2 &pcfg_pull_none>, 676 <0 6 RK_FUNC_2 &pcfg_pull_none>; 677 }; 678 i2c3_gpio: i2c3-gpio { 679 rockchip,pins = 680 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 681 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 682 }; 683 }; 684 685 hdmi_i2c { 686 hdmii2c_xfer: hdmii2c-xfer { 687 rockchip,pins = 688 <0 5 RK_FUNC_1 &pcfg_pull_none>, 689 <0 6 RK_FUNC_1 &pcfg_pull_none>; 690 }; 691 }; 692 693 uart0 { 694 uart0_xfer: uart0-xfer { 695 rockchip,pins = 696 <1 9 RK_FUNC_1 &pcfg_pull_up>, 697 <1 8 RK_FUNC_1 &pcfg_pull_none>; 698 }; 699 700 uart0_cts: uart0-cts { 701 rockchip,pins = 702 <1 11 RK_FUNC_1 &pcfg_pull_none>; 703 }; 704 705 uart0_rts: uart0-rts { 706 rockchip,pins = 707 <1 10 RK_FUNC_1 &pcfg_pull_none>; 708 }; 709 710 uart0_rts_gpio: uart0-rts-gpio { 711 rockchip,pins = 712 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 713 }; 714 }; 715 716 uart1 { 717 uart1_xfer: uart1-xfer { 718 rockchip,pins = 719 <3 4 RK_FUNC_4 &pcfg_pull_up>, 720 <3 6 RK_FUNC_4 &pcfg_pull_none>; 721 }; 722 723 uart1_cts: uart1-cts { 724 rockchip,pins = 725 <3 7 RK_FUNC_4 &pcfg_pull_none>; 726 }; 727 728 uart1_rts: uart1-rts { 729 rockchip,pins = 730 <3 5 RK_FUNC_4 &pcfg_pull_none>; 731 }; 732 733 uart1_rts_gpio: uart1-rts-gpio { 734 rockchip,pins = 735 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 736 }; 737 }; 738 739 uart2-0 { 740 uart2m0_xfer: uart2m0-xfer { 741 rockchip,pins = 742 <1 0 RK_FUNC_2 &pcfg_pull_up>, 743 <1 1 RK_FUNC_2 &pcfg_pull_none>; 744 }; 745 }; 746 747 uart2-1 { 748 uart2m1_xfer: uart2m1-xfer { 749 rockchip,pins = 750 <2 0 RK_FUNC_1 &pcfg_pull_up>, 751 <2 1 RK_FUNC_1 &pcfg_pull_none>; 752 }; 753 }; 754 755 spi0-0 { 756 spi0m0_clk: spi0m0-clk { 757 rockchip,pins = 758 <2 8 RK_FUNC_1 &pcfg_pull_up>; 759 }; 760 761 spi0m0_cs0: spi0m0-cs0 { 762 rockchip,pins = 763 <2 11 RK_FUNC_1 &pcfg_pull_up>; 764 }; 765 766 spi0m0_tx: spi0m0-tx { 767 rockchip,pins = 768 <2 9 RK_FUNC_1 &pcfg_pull_up>; 769 }; 770 771 spi0m0_rx: spi0m0-rx { 772 rockchip,pins = 773 <2 10 RK_FUNC_1 &pcfg_pull_up>; 774 }; 775 776 spi0m0_cs1: spi0m0-cs1 { 777 rockchip,pins = 778 <2 12 RK_FUNC_1 &pcfg_pull_up>; 779 }; 780 }; 781 782 spi0-1 { 783 spi0m1_clk: spi0m1-clk { 784 rockchip,pins = 785 <3 23 RK_FUNC_2 &pcfg_pull_up>; 786 }; 787 788 spi0m1_cs0: spi0m1-cs0 { 789 rockchip,pins = 790 <3 26 RK_FUNC_2 &pcfg_pull_up>; 791 }; 792 793 spi0m1_tx: spi0m1-tx { 794 rockchip,pins = 795 <3 25 RK_FUNC_2 &pcfg_pull_up>; 796 }; 797 798 spi0m1_rx: spi0m1-rx { 799 rockchip,pins = 800 <3 24 RK_FUNC_2 &pcfg_pull_up>; 801 }; 802 803 spi0m1_cs1: spi0m1-cs1 { 804 rockchip,pins = 805 <3 27 RK_FUNC_2 &pcfg_pull_up>; 806 }; 807 }; 808 809 spi0-2 { 810 spi0m2_clk: spi0m2-clk { 811 rockchip,pins = 812 <3 0 RK_FUNC_4 &pcfg_pull_up>; 813 }; 814 815 spi0m2_cs0: spi0m2-cs0 { 816 rockchip,pins = 817 <3 8 RK_FUNC_3 &pcfg_pull_up>; 818 }; 819 820 spi0m2_tx: spi0m2-tx { 821 rockchip,pins = 822 <3 1 RK_FUNC_4 &pcfg_pull_up>; 823 }; 824 825 spi0m2_rx: spi0m2-rx { 826 rockchip,pins = 827 <3 2 RK_FUNC_4 &pcfg_pull_up>; 828 }; 829 }; 830 831 i2s1 { 832 i2s1_mclk: i2s1-mclk { 833 rockchip,pins = 834 <2 15 RK_FUNC_1 &pcfg_pull_none>; 835 }; 836 837 i2s1_sclk: i2s1-sclk { 838 rockchip,pins = 839 <2 18 RK_FUNC_1 &pcfg_pull_none>; 840 }; 841 842 i2s1_lrckrx: i2s1-lrckrx { 843 rockchip,pins = 844 <2 16 RK_FUNC_1 &pcfg_pull_none>; 845 }; 846 847 i2s1_lrcktx: i2s1-lrcktx { 848 rockchip,pins = 849 <2 17 RK_FUNC_1 &pcfg_pull_none>; 850 }; 851 852 i2s1_sdi: i2s1-sdi { 853 rockchip,pins = 854 <2 19 RK_FUNC_1 &pcfg_pull_none>; 855 }; 856 857 i2s1_sdo: i2s1-sdo { 858 rockchip,pins = 859 <2 23 RK_FUNC_1 &pcfg_pull_none>; 860 }; 861 862 i2s1_sdio1: i2s1-sdio1 { 863 rockchip,pins = 864 <2 20 RK_FUNC_1 &pcfg_pull_none>; 865 }; 866 867 i2s1_sdio2: i2s1-sdio2 { 868 rockchip,pins = 869 <2 21 RK_FUNC_1 &pcfg_pull_none>; 870 }; 871 872 i2s1_sdio3: i2s1-sdio3 { 873 rockchip,pins = 874 <2 22 RK_FUNC_1 &pcfg_pull_none>; 875 }; 876 877 i2s1_sleep: i2s1-sleep { 878 rockchip,pins = 879 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 880 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 881 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 882 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 883 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 884 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 885 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 886 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 887 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 888 }; 889 }; 890 891 i2s2-0 { 892 i2s2m0_mclk: i2s2m0-mclk { 893 rockchip,pins = 894 <1 21 RK_FUNC_1 &pcfg_pull_none>; 895 }; 896 897 i2s2m0_sclk: i2s2m0-sclk { 898 rockchip,pins = 899 <1 22 RK_FUNC_1 &pcfg_pull_none>; 900 }; 901 902 i2s2m0_lrckrx: i2s2m0-lrckrx { 903 rockchip,pins = 904 <1 26 RK_FUNC_1 &pcfg_pull_none>; 905 }; 906 907 i2s2m0_lrcktx: i2s2m0-lrcktx { 908 rockchip,pins = 909 <1 23 RK_FUNC_1 &pcfg_pull_none>; 910 }; 911 912 i2s2m0_sdi: i2s2m0-sdi { 913 rockchip,pins = 914 <1 24 RK_FUNC_1 &pcfg_pull_none>; 915 }; 916 917 i2s2m0_sdo: i2s2m0-sdo { 918 rockchip,pins = 919 <1 25 RK_FUNC_1 &pcfg_pull_none>; 920 }; 921 922 i2s2m0_sleep: i2s2m0-sleep { 923 rockchip,pins = 924 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 925 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 926 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 927 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 928 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 929 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 930 }; 931 }; 932 933 i2s2-1 { 934 i2s2m1_mclk: i2s2m1-mclk { 935 rockchip,pins = 936 <1 21 RK_FUNC_1 &pcfg_pull_none>; 937 }; 938 939 i2s2m1_sclk: i2s2m1-sclk { 940 rockchip,pins = 941 <3 0 RK_FUNC_6 &pcfg_pull_none>; 942 }; 943 944 i2s2m1_lrckrx: i2sm1-lrckrx { 945 rockchip,pins = 946 <3 8 RK_FUNC_6 &pcfg_pull_none>; 947 }; 948 949 i2s2m1_lrcktx: i2s2m1-lrcktx { 950 rockchip,pins = 951 <3 8 RK_FUNC_4 &pcfg_pull_none>; 952 }; 953 954 i2s2m1_sdi: i2s2m1-sdi { 955 rockchip,pins = 956 <3 2 RK_FUNC_6 &pcfg_pull_none>; 957 }; 958 959 i2s2m1_sdo: i2s2m1-sdo { 960 rockchip,pins = 961 <3 1 RK_FUNC_6 &pcfg_pull_none>; 962 }; 963 964 i2s2m1_sleep: i2s2m1-sleep { 965 rockchip,pins = 966 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 967 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 968 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 969 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 970 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 971 }; 972 }; 973 974 spdif-0 { 975 spdifm0_tx: spdifm0-tx { 976 rockchip,pins = 977 <0 27 RK_FUNC_1 &pcfg_pull_none>; 978 }; 979 }; 980 981 spdif-1 { 982 spdifm1_tx: spdifm1-tx { 983 rockchip,pins = 984 <2 17 RK_FUNC_2 &pcfg_pull_none>; 985 }; 986 }; 987 988 spdif-2 { 989 spdifm2_tx: spdifm2-tx { 990 rockchip,pins = 991 <0 2 RK_FUNC_2 &pcfg_pull_none>; 992 }; 993 }; 994 995 sdmmc0-0 { 996 sdmmc0m0_pwren: sdmmc0m0-pwren { 997 rockchip,pins = 998 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 999 }; 1000 1001 sdmmc0m0_gpio: sdmmc0m0-gpio { 1002 rockchip,pins = 1003 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1004 }; 1005 }; 1006 1007 sdmmc0-1 { 1008 sdmmc0m1_pwren: sdmmc0m1-pwren { 1009 rockchip,pins = 1010 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1011 }; 1012 1013 sdmmc0m1_gpio: sdmmc0m1-gpio { 1014 rockchip,pins = 1015 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1016 }; 1017 }; 1018 1019 sdmmc0 { 1020 sdmmc0_clk: sdmmc0-clk { 1021 rockchip,pins = 1022 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1023 }; 1024 1025 sdmmc0_cmd: sdmmc0-cmd { 1026 rockchip,pins = 1027 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1028 }; 1029 1030 sdmmc0_dectn: sdmmc0-dectn { 1031 rockchip,pins = 1032 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1033 }; 1034 1035 sdmmc0_wrprt: sdmmc0-wrprt { 1036 rockchip,pins = 1037 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1038 }; 1039 1040 sdmmc0_bus1: sdmmc0-bus1 { 1041 rockchip,pins = 1042 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1043 }; 1044 1045 sdmmc0_bus4: sdmmc0-bus4 { 1046 rockchip,pins = 1047 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1048 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1049 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1050 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1051 }; 1052 1053 sdmmc0_gpio: sdmmc0-gpio { 1054 rockchip,pins = 1055 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1056 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1057 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1058 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1059 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1060 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1061 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1062 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1063 }; 1064 }; 1065 1066 sdmmc0ext { 1067 sdmmc0ext_clk: sdmmc0ext-clk { 1068 rockchip,pins = 1069 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1070 }; 1071 1072 sdmmc0ext_cmd: sdmmc0ext-cmd { 1073 rockchip,pins = 1074 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1075 }; 1076 1077 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1078 rockchip,pins = 1079 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1080 }; 1081 1082 sdmmc0ext_dectn: sdmmc0ext-dectn { 1083 rockchip,pins = 1084 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1085 }; 1086 1087 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1088 rockchip,pins = 1089 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1090 }; 1091 1092 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1093 rockchip,pins = 1094 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1095 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1096 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1097 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1098 }; 1099 1100 sdmmc0ext_gpio: sdmmc0ext-gpio { 1101 rockchip,pins = 1102 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1103 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1104 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1105 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1106 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1107 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1108 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1109 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1110 }; 1111 }; 1112 1113 sdmmc1 { 1114 sdmmc1_clk: sdmmc1-clk { 1115 rockchip,pins = 1116 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1117 }; 1118 1119 sdmmc1_cmd: sdmmc1-cmd { 1120 rockchip,pins = 1121 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1122 }; 1123 1124 sdmmc1_pwren: sdmmc1-pwren { 1125 rockchip,pins = 1126 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1127 }; 1128 1129 sdmmc1_wrprt: sdmmc1-wrprt { 1130 rockchip,pins = 1131 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1132 }; 1133 1134 sdmmc1_dectn: sdmmc1-dectn { 1135 rockchip,pins = 1136 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1137 }; 1138 1139 sdmmc1_bus1: sdmmc1-bus1 { 1140 rockchip,pins = 1141 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1142 }; 1143 1144 sdmmc1_bus4: sdmmc1-bus4 { 1145 rockchip,pins = 1146 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1147 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1148 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1149 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1150 }; 1151 1152 sdmmc1_gpio: sdmmc1-gpio { 1153 rockchip,pins = 1154 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1155 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1156 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1157 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1158 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1159 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1160 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1161 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1162 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1163 }; 1164 }; 1165 1166 emmc { 1167 emmc_clk: emmc-clk { 1168 rockchip,pins = 1169 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1170 }; 1171 1172 emmc_cmd: emmc-cmd { 1173 rockchip,pins = 1174 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1175 }; 1176 1177 emmc_pwren: emmc-pwren { 1178 rockchip,pins = 1179 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1180 }; 1181 1182 emmc_rstnout: emmc-rstnout { 1183 rockchip,pins = 1184 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1185 }; 1186 1187 emmc_bus1: emmc-bus1 { 1188 rockchip,pins = 1189 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1190 }; 1191 1192 emmc_bus4: emmc-bus4 { 1193 rockchip,pins = 1194 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1195 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1196 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1197 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1198 }; 1199 1200 emmc_bus8: emmc-bus8 { 1201 rockchip,pins = 1202 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1203 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1204 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1205 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1206 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1207 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1208 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1209 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1210 }; 1211 }; 1212 1213 pwm0 { 1214 pwm0_pin: pwm0-pin { 1215 rockchip,pins = 1216 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1217 }; 1218 }; 1219 1220 pwm1 { 1221 pwm1_pin: pwm1-pin { 1222 rockchip,pins = 1223 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1224 }; 1225 }; 1226 1227 pwm2 { 1228 pwm2_pin: pwm2-pin { 1229 rockchip,pins = 1230 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1231 }; 1232 }; 1233 1234 pwmir { 1235 pwmir_pin: pwmir-pin { 1236 rockchip,pins = 1237 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1238 }; 1239 }; 1240 1241 gmac-0 { 1242 rgmiim0_pins: rgmiim0-pins { 1243 rockchip,pins = 1244 /* mac_txclk */ 1245 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1246 /* mac_rxclk */ 1247 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1248 /* mac_mdio */ 1249 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1250 /* mac_txen */ 1251 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1252 /* mac_clk */ 1253 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1254 /* mac_rxdv */ 1255 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1256 /* mac_mdc */ 1257 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1258 /* mac_rxd1 */ 1259 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1260 /* mac_rxd0 */ 1261 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1262 /* mac_txd1 */ 1263 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1264 /* mac_txd0 */ 1265 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1266 /* mac_rxd3 */ 1267 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1268 /* mac_rxd2 */ 1269 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1270 /* mac_txd3 */ 1271 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1272 /* mac_txd2 */ 1273 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1274 }; 1275 1276 rmiim0_pins: rmiim0-pins { 1277 rockchip,pins = 1278 /* mac_mdio */ 1279 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1280 /* mac_txen */ 1281 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1282 /* mac_clk */ 1283 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1284 /* mac_rxer */ 1285 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1286 /* mac_rxdv */ 1287 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1288 /* mac_mdc */ 1289 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1290 /* mac_rxd1 */ 1291 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1292 /* mac_rxd0 */ 1293 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1294 /* mac_txd1 */ 1295 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1296 /* mac_txd0 */ 1297 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1298 }; 1299 }; 1300 1301 gmac-1 { 1302 rgmiim1_pins: rgmiim1-pins { 1303 rockchip,pins = 1304 /* mac_txclk */ 1305 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1306 /* mac_rxclk */ 1307 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1308 /* mac_mdio */ 1309 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1310 /* mac_txen */ 1311 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1312 /* mac_clk */ 1313 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1314 /* mac_rxdv */ 1315 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1316 /* mac_mdc */ 1317 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1318 /* mac_rxd1 */ 1319 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1320 /* mac_rxd0 */ 1321 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1322 /* mac_txd1 */ 1323 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1324 /* mac_txd0 */ 1325 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1326 /* mac_rxd3 */ 1327 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1328 /* mac_rxd2 */ 1329 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1330 /* mac_txd3 */ 1331 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1332 /* mac_txd2 */ 1333 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1334 1335 /* mac_txclk */ 1336 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1337 /* mac_txen */ 1338 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1339 /* mac_clk */ 1340 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1341 /* mac_txd1 */ 1342 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1343 /* mac_txd0 */ 1344 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1345 /* mac_txd3 */ 1346 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1347 /* mac_txd2 */ 1348 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1349 }; 1350 1351 rmiim1_pins: rmiim1-pins { 1352 rockchip,pins = 1353 /* mac_mdio */ 1354 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1355 /* mac_txen */ 1356 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1357 /* mac_clk */ 1358 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1359 /* mac_rxer */ 1360 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1361 /* mac_rxdv */ 1362 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1363 /* mac_mdc */ 1364 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1365 /* mac_rxd1 */ 1366 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1367 /* mac_rxd0 */ 1368 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1369 /* mac_txd1 */ 1370 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1371 /* mac_txd0 */ 1372 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1373 1374 /* mac_mdio */ 1375 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1376 /* mac_txen */ 1377 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1378 /* mac_clk */ 1379 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1380 /* mac_mdc */ 1381 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1382 /* mac_txd1 */ 1383 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1384 /* mac_txd0 */ 1385 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1386 }; 1387 }; 1388 1389 gmac2phy { 1390 fephyled_speed100: fephyled-speed100 { 1391 rockchip,pins = 1392 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1393 }; 1394 1395 fephyled_speed10: fephyled-speed10 { 1396 rockchip,pins = 1397 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1398 }; 1399 1400 fephyled_duplex: fephyled-duplex { 1401 rockchip,pins = 1402 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1403 }; 1404 1405 fephyled_rxm0: fephyled-rxm0 { 1406 rockchip,pins = 1407 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1408 }; 1409 1410 fephyled_txm0: fephyled-txm0 { 1411 rockchip,pins = 1412 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1413 }; 1414 1415 fephyled_linkm0: fephyled-linkm0 { 1416 rockchip,pins = 1417 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1418 }; 1419 1420 fephyled_rxm1: fephyled-rxm1 { 1421 rockchip,pins = 1422 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1423 }; 1424 1425 fephyled_txm1: fephyled-txm1 { 1426 rockchip,pins = 1427 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1428 }; 1429 1430 fephyled_linkm1: fephyled-linkm1 { 1431 rockchip,pins = 1432 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1433 }; 1434 }; 1435 1436 tsadc_pin { 1437 tsadc_int: tsadc-int { 1438 rockchip,pins = 1439 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1440 }; 1441 tsadc_gpio: tsadc-gpio { 1442 rockchip,pins = 1443 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1444 }; 1445 }; 1446 1447 hdmi_pin { 1448 hdmi_cec: hdmi-cec { 1449 rockchip,pins = 1450 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1451 }; 1452 1453 hdmi_hpd: hdmi-hpd { 1454 rockchip,pins = 1455 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1456 }; 1457 }; 1458 1459 cif-0 { 1460 dvp_d2d9_m0:dvp-d2d9-m0 { 1461 rockchip,pins = 1462 /* cif_d0 */ 1463 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1464 /* cif_d1 */ 1465 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1466 /* cif_d2 */ 1467 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1468 /* cif_d3 */ 1469 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1470 /* cif_d4 */ 1471 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1472 /* cif_d5m0 */ 1473 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1474 /* cif_d6m0 */ 1475 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1476 /* cif_d7m0 */ 1477 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1478 /* cif_href */ 1479 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1480 /* cif_vsync */ 1481 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1482 /* cif_clkoutm0 */ 1483 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1484 /* cif_clkin */ 1485 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1486 }; 1487 }; 1488 1489 cif-1 { 1490 dvp_d2d9_m1:dvp-d2d9-m1 { 1491 rockchip,pins = 1492 /* cif_d0 */ 1493 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1494 /* cif_d1 */ 1495 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1496 /* cif_d2 */ 1497 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1498 /* cif_d3 */ 1499 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1500 /* cif_d4 */ 1501 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1502 /* cif_d5m1 */ 1503 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1504 /* cif_d6m1 */ 1505 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1506 /* cif_d7m1 */ 1507 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1508 /* cif_href */ 1509 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1510 /* cif_vsync */ 1511 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1512 /* cif_clkoutm1 */ 1513 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1514 /* cif_clkin */ 1515 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1516 }; 1517 }; 1518 }; 1519}; 1520