xref: /openbmc/u-boot/arch/arm/dts/ls1021a-twr.dtsi (revision 77c07e7ed36cae250a3562ee4bed0fa537960354)
183d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+
28b677614SBin Meng/*
38b677614SBin Meng * Freescale ls1021a TWR board common device tree source
48b677614SBin Meng *
58b677614SBin Meng * Copyright 2013-2015 Freescale Semiconductor, Inc.
68b677614SBin Meng */
78b677614SBin Meng
88b677614SBin Meng#include "ls1021a.dtsi"
98b677614SBin Meng
108b677614SBin Meng/ {
118b677614SBin Meng	model = "LS1021A TWR Board";
128b677614SBin Meng
138b677614SBin Meng	aliases {
14*220ce489SRajesh Bhagat		enet2-rgmii-phy = &rgmii_phy1;
15*220ce489SRajesh Bhagat		enet0-sgmii-phy = &sgmii_phy2;
16*220ce489SRajesh Bhagat		enet1-sgmii-phy = &sgmii_phy0;
178b677614SBin Meng		spi0 = &qspi;
188b677614SBin Meng		spi1 = &dspi1;
198b677614SBin Meng	};
208b677614SBin Meng
218b677614SBin Meng	chosen {
228b677614SBin Meng		stdout-path = &uart0;
238b677614SBin Meng	};
248b677614SBin Meng};
258b677614SBin Meng
268b677614SBin Meng&qspi {
278b677614SBin Meng	bus-num = <0>;
288b677614SBin Meng	status = "okay";
298b677614SBin Meng
308b677614SBin Meng	qflash0: n25q128a13@0 {
318b677614SBin Meng		#address-cells = <1>;
328b677614SBin Meng		#size-cells = <1>;
338b677614SBin Meng		compatible = "spi-flash";
348b677614SBin Meng		spi-max-frequency = <20000000>;
358b677614SBin Meng		reg = <0>;
368b677614SBin Meng	};
378b677614SBin Meng};
388b677614SBin Meng
398b677614SBin Meng&dspi1 {
408b677614SBin Meng	bus-num = <0>;
418b677614SBin Meng	status = "okay";
428b677614SBin Meng
438b677614SBin Meng	dspiflash: at26df081a@0 {
448b677614SBin Meng		#address-cells = <1>;
458b677614SBin Meng		#size-cells = <1>;
468b677614SBin Meng		compatible = "spi-flash";
478b677614SBin Meng		spi-max-frequency = <16000000>;
488b677614SBin Meng		spi-cpol;
498b677614SBin Meng		spi-cpha;
508b677614SBin Meng		reg = <0>;
518b677614SBin Meng	};
528b677614SBin Meng};
538b677614SBin Meng
548b677614SBin Meng&i2c0 {
558b677614SBin Meng	status = "okay";
568b677614SBin Meng};
578b677614SBin Meng
588b677614SBin Meng&i2c1 {
598b677614SBin Meng	status = "okay";
608b677614SBin Meng};
618b677614SBin Meng
628b677614SBin Meng&ifc {
638b677614SBin Meng	#address-cells = <2>;
648b677614SBin Meng	#size-cells = <1>;
658b677614SBin Meng	/* NOR Flash on board */
668b677614SBin Meng	ranges = <0x0 0x0 0x60000000 0x08000000>;
678b677614SBin Meng	status = "okay";
688b677614SBin Meng
698b677614SBin Meng	nor@0,0 {
708b677614SBin Meng		#address-cells = <1>;
718b677614SBin Meng		#size-cells = <1>;
728b677614SBin Meng		compatible = "cfi-flash";
738b677614SBin Meng		reg = <0x0 0x0 0x8000000>;
748b677614SBin Meng		bank-width = <2>;
758b677614SBin Meng		device-width = <1>;
768b677614SBin Meng	};
778b677614SBin Meng};
788b677614SBin Meng
798b677614SBin Meng&lpuart0 {
808b677614SBin Meng	status = "okay";
818b677614SBin Meng};
828b677614SBin Meng
838b677614SBin Meng&mdio0 {
848b677614SBin Meng	sgmii_phy0: ethernet-phy@0 {
858b677614SBin Meng		reg = <0x0>;
868b677614SBin Meng	};
878b677614SBin Meng	rgmii_phy1: ethernet-phy@1 {
888b677614SBin Meng		reg = <0x1>;
898b677614SBin Meng	};
908b677614SBin Meng	sgmii_phy2: ethernet-phy@2 {
918b677614SBin Meng		reg = <0x2>;
928b677614SBin Meng	};
938b677614SBin Meng	tbi1: tbi-phy@1f {
948b677614SBin Meng		reg = <0x1f>;
958b677614SBin Meng		device_type = "tbi-phy";
968b677614SBin Meng	};
978b677614SBin Meng};
988b677614SBin Meng
998b677614SBin Meng&uart0 {
1008b677614SBin Meng	status = "okay";
1018b677614SBin Meng};
1028b677614SBin Meng
1038b677614SBin Meng&uart1 {
1048b677614SBin Meng	status = "okay";
1058b677614SBin Meng};
1069ed5ec9bSPeng Ma
1079ed5ec9bSPeng Ma&sata {
1089ed5ec9bSPeng Ma	status = "okay";
1099ed5ec9bSPeng Ma};
110