1*67f165ddSAbel Vesa// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*67f165ddSAbel Vesa// 3*67f165ddSAbel Vesa// Copyright 2016 Freescale Semiconductor, Inc. 4*67f165ddSAbel Vesa 5*67f165ddSAbel Vesa#include "imx6q.dtsi" 6*67f165ddSAbel Vesa 7*67f165ddSAbel Vesa/ { 8*67f165ddSAbel Vesa soc { 9*67f165ddSAbel Vesa ocram2: sram@940000 { 10*67f165ddSAbel Vesa compatible = "mmio-sram"; 11*67f165ddSAbel Vesa reg = <0x00940000 0x20000>; 12*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_OCRAM>; 13*67f165ddSAbel Vesa }; 14*67f165ddSAbel Vesa 15*67f165ddSAbel Vesa ocram3: sram@960000 { 16*67f165ddSAbel Vesa compatible = "mmio-sram"; 17*67f165ddSAbel Vesa reg = <0x00960000 0x20000>; 18*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_OCRAM>; 19*67f165ddSAbel Vesa }; 20*67f165ddSAbel Vesa 21*67f165ddSAbel Vesa aips-bus@2100000 { 22*67f165ddSAbel Vesa pre1: pre@21c8000 { 23*67f165ddSAbel Vesa compatible = "fsl,imx6qp-pre"; 24*67f165ddSAbel Vesa reg = <0x021c8000 0x1000>; 25*67f165ddSAbel Vesa interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 26*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRE0>; 27*67f165ddSAbel Vesa clock-names = "axi"; 28*67f165ddSAbel Vesa fsl,iram = <&ocram2>; 29*67f165ddSAbel Vesa }; 30*67f165ddSAbel Vesa 31*67f165ddSAbel Vesa pre2: pre@21c9000 { 32*67f165ddSAbel Vesa compatible = "fsl,imx6qp-pre"; 33*67f165ddSAbel Vesa reg = <0x021c9000 0x1000>; 34*67f165ddSAbel Vesa interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; 35*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRE1>; 36*67f165ddSAbel Vesa clock-names = "axi"; 37*67f165ddSAbel Vesa fsl,iram = <&ocram2>; 38*67f165ddSAbel Vesa }; 39*67f165ddSAbel Vesa 40*67f165ddSAbel Vesa pre3: pre@21ca000 { 41*67f165ddSAbel Vesa compatible = "fsl,imx6qp-pre"; 42*67f165ddSAbel Vesa reg = <0x021ca000 0x1000>; 43*67f165ddSAbel Vesa interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>; 44*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRE2>; 45*67f165ddSAbel Vesa clock-names = "axi"; 46*67f165ddSAbel Vesa fsl,iram = <&ocram3>; 47*67f165ddSAbel Vesa }; 48*67f165ddSAbel Vesa 49*67f165ddSAbel Vesa pre4: pre@21cb000 { 50*67f165ddSAbel Vesa compatible = "fsl,imx6qp-pre"; 51*67f165ddSAbel Vesa reg = <0x021cb000 0x1000>; 52*67f165ddSAbel Vesa interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>; 53*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRE3>; 54*67f165ddSAbel Vesa clock-names = "axi"; 55*67f165ddSAbel Vesa fsl,iram = <&ocram3>; 56*67f165ddSAbel Vesa }; 57*67f165ddSAbel Vesa 58*67f165ddSAbel Vesa prg1: prg@21cc000 { 59*67f165ddSAbel Vesa compatible = "fsl,imx6qp-prg"; 60*67f165ddSAbel Vesa reg = <0x021cc000 0x1000>; 61*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRG0_APB>, 62*67f165ddSAbel Vesa <&clks IMX6QDL_CLK_PRG0_AXI>; 63*67f165ddSAbel Vesa clock-names = "ipg", "axi"; 64*67f165ddSAbel Vesa fsl,pres = <&pre1>, <&pre2>, <&pre3>; 65*67f165ddSAbel Vesa }; 66*67f165ddSAbel Vesa 67*67f165ddSAbel Vesa prg2: prg@21cd000 { 68*67f165ddSAbel Vesa compatible = "fsl,imx6qp-prg"; 69*67f165ddSAbel Vesa reg = <0x021cd000 0x1000>; 70*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_PRG1_APB>, 71*67f165ddSAbel Vesa <&clks IMX6QDL_CLK_PRG1_AXI>; 72*67f165ddSAbel Vesa clock-names = "ipg", "axi"; 73*67f165ddSAbel Vesa fsl,pres = <&pre4>, <&pre2>, <&pre3>; 74*67f165ddSAbel Vesa }; 75*67f165ddSAbel Vesa }; 76*67f165ddSAbel Vesa }; 77*67f165ddSAbel Vesa}; 78*67f165ddSAbel Vesa 79*67f165ddSAbel Vesa&fec { 80*67f165ddSAbel Vesa /delete-property/interrupts-extended; 81*67f165ddSAbel Vesa interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, 82*67f165ddSAbel Vesa <0 119 IRQ_TYPE_LEVEL_HIGH>; 83*67f165ddSAbel Vesa}; 84*67f165ddSAbel Vesa 85*67f165ddSAbel Vesa&gpc { 86*67f165ddSAbel Vesa compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; 87*67f165ddSAbel Vesa}; 88*67f165ddSAbel Vesa 89*67f165ddSAbel Vesa&ipu1 { 90*67f165ddSAbel Vesa compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; 91*67f165ddSAbel Vesa fsl,prg = <&prg1>; 92*67f165ddSAbel Vesa}; 93*67f165ddSAbel Vesa 94*67f165ddSAbel Vesa&ipu2 { 95*67f165ddSAbel Vesa compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; 96*67f165ddSAbel Vesa fsl,prg = <&prg2>; 97*67f165ddSAbel Vesa}; 98*67f165ddSAbel Vesa 99*67f165ddSAbel Vesa&ldb { 100*67f165ddSAbel Vesa clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 101*67f165ddSAbel Vesa <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, 102*67f165ddSAbel Vesa <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, 103*67f165ddSAbel Vesa <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; 104*67f165ddSAbel Vesa clock-names = "di0_pll", "di1_pll", 105*67f165ddSAbel Vesa "di0_sel", "di1_sel", "di2_sel", "di3_sel", 106*67f165ddSAbel Vesa "di0", "di1"; 107*67f165ddSAbel Vesa}; 108*67f165ddSAbel Vesa 109*67f165ddSAbel Vesa&mmdc0 { 110*67f165ddSAbel Vesa compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; 111*67f165ddSAbel Vesa}; 112*67f165ddSAbel Vesa 113*67f165ddSAbel Vesa&pcie { 114*67f165ddSAbel Vesa compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; 115*67f165ddSAbel Vesa}; 116