14909b89eSPriyanka Jain// SPDX-License-Identifier: GPL-2.0+ OR X11 24909b89eSPriyanka Jain/* 34909b89eSPriyanka Jain * NXP lx2160a SOC common device tree source 44909b89eSPriyanka Jain * 54909b89eSPriyanka Jain * Copyright 2018 NXP 64909b89eSPriyanka Jain * 74909b89eSPriyanka Jain */ 84909b89eSPriyanka Jain 94909b89eSPriyanka Jain/ { 104909b89eSPriyanka Jain compatible = "fsl,lx2160a"; 114909b89eSPriyanka Jain interrupt-parent = <&gic>; 124909b89eSPriyanka Jain #address-cells = <2>; 134909b89eSPriyanka Jain #size-cells = <2>; 144909b89eSPriyanka Jain 154909b89eSPriyanka Jain memory@80000000 { 164909b89eSPriyanka Jain device_type = "memory"; 174909b89eSPriyanka Jain reg = <0x00000000 0x80000000 0 0x80000000>; 184909b89eSPriyanka Jain /* DRAM space - 1, size : 2 GB DRAM */ 194909b89eSPriyanka Jain }; 204909b89eSPriyanka Jain 214909b89eSPriyanka Jain sysclk: sysclk { 224909b89eSPriyanka Jain compatible = "fixed-clock"; 234909b89eSPriyanka Jain #clock-cells = <0>; 244909b89eSPriyanka Jain clock-frequency = <100000000>; 254909b89eSPriyanka Jain clock-output-names = "sysclk"; 264909b89eSPriyanka Jain }; 274909b89eSPriyanka Jain 284909b89eSPriyanka Jain clockgen: clocking@1300000 { 294909b89eSPriyanka Jain compatible = "fsl,ls2080a-clockgen"; 304909b89eSPriyanka Jain reg = <0 0x1300000 0 0xa0000>; 314909b89eSPriyanka Jain #clock-cells = <2>; 324909b89eSPriyanka Jain clocks = <&sysclk>; 334909b89eSPriyanka Jain }; 344909b89eSPriyanka Jain 354909b89eSPriyanka Jain gic: interrupt-controller@6000000 { 364909b89eSPriyanka Jain compatible = "arm,gic-v3"; 374909b89eSPriyanka Jain reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 384909b89eSPriyanka Jain <0x0 0x06200000 0 0x100000>; /* GICR */ 394909b89eSPriyanka Jain #interrupt-cells = <3>; 404909b89eSPriyanka Jain interrupt-controller; 414909b89eSPriyanka Jain interrupts = <1 9 0x4>; 424909b89eSPriyanka Jain }; 434909b89eSPriyanka Jain 444909b89eSPriyanka Jain timer { 454909b89eSPriyanka Jain compatible = "arm,armv8-timer"; 464909b89eSPriyanka Jain interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 474909b89eSPriyanka Jain <1 14 0x8>, /* Physical NS PPI, active-low */ 484909b89eSPriyanka Jain <1 11 0x8>, /* Virtual PPI, active-low */ 494909b89eSPriyanka Jain <1 10 0x8>; /* Hypervisor PPI, active-low */ 504909b89eSPriyanka Jain }; 514909b89eSPriyanka Jain 524909b89eSPriyanka Jain uart0: serial@21c0000 { 534909b89eSPriyanka Jain compatible = "arm,pl011"; 544909b89eSPriyanka Jain reg = <0x0 0x21c0000 0x0 0x1000>; 554909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 564909b89eSPriyanka Jain }; 574909b89eSPriyanka Jain 584909b89eSPriyanka Jain uart1: serial@21d0000 { 594909b89eSPriyanka Jain compatible = "arm,pl011"; 604909b89eSPriyanka Jain reg = <0x0 0x21d0000 0x0 0x1000>; 614909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 624909b89eSPriyanka Jain }; 634909b89eSPriyanka Jain 644909b89eSPriyanka Jain uart2: serial@21e0000 { 654909b89eSPriyanka Jain compatible = "arm,pl011"; 664909b89eSPriyanka Jain reg = <0x0 0x21e0000 0x0 0x1000>; 674909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 684909b89eSPriyanka Jain status = "disabled"; 694909b89eSPriyanka Jain }; 704909b89eSPriyanka Jain 714909b89eSPriyanka Jain uart3: serial@21f0000 { 724909b89eSPriyanka Jain compatible = "arm,pl011"; 734909b89eSPriyanka Jain reg = <0x0 0x21f0000 0x0 0x1000>; 744909b89eSPriyanka Jain clocks = <&clockgen 4 0>; 754909b89eSPriyanka Jain status = "disabled"; 764909b89eSPriyanka Jain }; 774909b89eSPriyanka Jain 784909b89eSPriyanka Jain dspi0: dspi@2100000 { 794909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 804909b89eSPriyanka Jain #address-cells = <1>; 814909b89eSPriyanka Jain #size-cells = <0>; 824909b89eSPriyanka Jain reg = <0x0 0x2100000 0x0 0x10000>; 834909b89eSPriyanka Jain interrupts = <0 26 0x4>; /* Level high type */ 844909b89eSPriyanka Jain num-cs = <6>; 854909b89eSPriyanka Jain }; 864909b89eSPriyanka Jain 874909b89eSPriyanka Jain dspi1: dspi@2110000 { 884909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 894909b89eSPriyanka Jain #address-cells = <1>; 904909b89eSPriyanka Jain #size-cells = <0>; 914909b89eSPriyanka Jain reg = <0x0 0x2110000 0x0 0x10000>; 92*58c3e620SPriyanka Jain interrupts = <0 26 0x4>; /* Level high type */ 934909b89eSPriyanka Jain num-cs = <6>; 944909b89eSPriyanka Jain }; 954909b89eSPriyanka Jain 964909b89eSPriyanka Jain dspi2: dspi@2120000 { 974909b89eSPriyanka Jain compatible = "fsl,vf610-dspi"; 984909b89eSPriyanka Jain #address-cells = <1>; 994909b89eSPriyanka Jain #size-cells = <0>; 1004909b89eSPriyanka Jain reg = <0x0 0x2120000 0x0 0x10000>; 1014909b89eSPriyanka Jain interrupts = <0 241 0x4>; /* Level high type */ 1024909b89eSPriyanka Jain num-cs = <6>; 1034909b89eSPriyanka Jain }; 1044909b89eSPriyanka Jain 1054909b89eSPriyanka Jain usb0: usb3@3100000 { 1064909b89eSPriyanka Jain compatible = "fsl,layerscape-dwc3"; 1074909b89eSPriyanka Jain reg = <0x0 0x3100000 0x0 0x10000>; 1084909b89eSPriyanka Jain interrupts = <0 80 0x4>; /* Level high type */ 1094909b89eSPriyanka Jain dr_mode = "host"; 1104909b89eSPriyanka Jain }; 1114909b89eSPriyanka Jain 1124909b89eSPriyanka Jain usb1: usb3@3110000 { 1134909b89eSPriyanka Jain compatible = "fsl,layerscape-dwc3"; 1144909b89eSPriyanka Jain reg = <0x0 0x3110000 0x0 0x10000>; 1154909b89eSPriyanka Jain interrupts = <0 81 0x4>; /* Level high type */ 1164909b89eSPriyanka Jain dr_mode = "host"; 1174909b89eSPriyanka Jain }; 118*58c3e620SPriyanka Jain 119*58c3e620SPriyanka Jain esdhc0: esdhc@2140000 { 120*58c3e620SPriyanka Jain compatible = "fsl,esdhc"; 121*58c3e620SPriyanka Jain reg = <0x0 0x2140000 0x0 0x10000>; 122*58c3e620SPriyanka Jain interrupts = <0 28 0x4>; /* Level high type */ 123*58c3e620SPriyanka Jain clocks = <&clockgen 4 1>; 124*58c3e620SPriyanka Jain voltage-ranges = <1800 1800 3300 3300>; 125*58c3e620SPriyanka Jain sdhci,auto-cmd12; 126*58c3e620SPriyanka Jain little-endian; 127*58c3e620SPriyanka Jain bus-width = <4>; 128*58c3e620SPriyanka Jain status = "disabled"; 129*58c3e620SPriyanka Jain }; 130*58c3e620SPriyanka Jain 131*58c3e620SPriyanka Jain esdhc1: esdhc@2150000 { 132*58c3e620SPriyanka Jain compatible = "fsl,esdhc"; 133*58c3e620SPriyanka Jain reg = <0x0 0x2150000 0x0 0x10000>; 134*58c3e620SPriyanka Jain interrupts = <0 63 0x4>; /* Level high type */ 135*58c3e620SPriyanka Jain clocks = <&clockgen 4 1>; 136*58c3e620SPriyanka Jain voltage-ranges = <1800 1800 3300 3300>; 137*58c3e620SPriyanka Jain sdhci,auto-cmd12; 138*58c3e620SPriyanka Jain non-removable; 139*58c3e620SPriyanka Jain little-endian; 140*58c3e620SPriyanka Jain bus-width = <4>; 141*58c3e620SPriyanka Jain status = "disabled"; 142*58c3e620SPriyanka Jain }; 143*58c3e620SPriyanka Jain 144*58c3e620SPriyanka Jain sata0: sata@3200000 { 145*58c3e620SPriyanka Jain compatible = "fsl,ls2080a-ahci"; 146*58c3e620SPriyanka Jain reg = <0x0 0x3200000 0x0 0x10000>; 147*58c3e620SPriyanka Jain interrupts = <0 133 4>; 148*58c3e620SPriyanka Jain clocks = <&clockgen 4 3>; 149*58c3e620SPriyanka Jain status = "disabled"; 150*58c3e620SPriyanka Jain 151*58c3e620SPriyanka Jain }; 152*58c3e620SPriyanka Jain 153*58c3e620SPriyanka Jain sata1: sata@3210000 { 154*58c3e620SPriyanka Jain compatible = "fsl,ls2080a-ahci"; 155*58c3e620SPriyanka Jain reg = <0x0 0x3210000 0x0 0x10000>; 156*58c3e620SPriyanka Jain interrupts = <0 136 4>; 157*58c3e620SPriyanka Jain clocks = <&clockgen 4 3>; 158*58c3e620SPriyanka Jain status = "disabled"; 159*58c3e620SPriyanka Jain 160*58c3e620SPriyanka Jain }; 161*58c3e620SPriyanka Jain 162*58c3e620SPriyanka Jain sata2: sata@3220000 { 163*58c3e620SPriyanka Jain compatible = "fsl,ls2080a-ahci"; 164*58c3e620SPriyanka Jain reg = <0x0 0x3220000 0x0 0x10000>; 165*58c3e620SPriyanka Jain interrupts = <0 97 4>; 166*58c3e620SPriyanka Jain clocks = <&clockgen 4 3>; 167*58c3e620SPriyanka Jain status = "disabled"; 168*58c3e620SPriyanka Jain 169*58c3e620SPriyanka Jain }; 170*58c3e620SPriyanka Jain 171*58c3e620SPriyanka Jain sata3: sata@3230000 { 172*58c3e620SPriyanka Jain compatible = "fsl,ls2080a-ahci"; 173*58c3e620SPriyanka Jain reg = <0x0 0x3230000 0x0 0x10000>; 174*58c3e620SPriyanka Jain interrupts = <0 100 4>; 175*58c3e620SPriyanka Jain clocks = <&clockgen 4 3>; 176*58c3e620SPriyanka Jain status = "disabled"; 177*58c3e620SPriyanka Jain 178*58c3e620SPriyanka Jain }; 1794909b89eSPriyanka Jain}; 180