xref: /openbmc/u-boot/arch/arm/dts/fsl-ls1043a-rdb.dts (revision 4549e789c1d58a8c48e8a20f1b4bdb83e978c954)
1*4549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR X11
2e1cecb4dSGong Qianyu/*
3e1cecb4dSGong Qianyu * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4e1cecb4dSGong Qianyu *
5e1cecb4dSGong Qianyu * Copyright (C) 2015, Freescale Semiconductor
6e1cecb4dSGong Qianyu *
7e1cecb4dSGong Qianyu * Mingkai Hu <Mingkai.hu@freescale.com>
8e1cecb4dSGong Qianyu */
9e1cecb4dSGong Qianyu
10e1cecb4dSGong Qianyu/dts-v1/;
11e1cecb4dSGong Qianyu/include/ "fsl-ls1043a.dtsi"
12e1cecb4dSGong Qianyu
13e1cecb4dSGong Qianyu/ {
14e1cecb4dSGong Qianyu	model = "LS1043A RDB Board";
1528752cf8SGong Qianyu
1628752cf8SGong Qianyu        aliases {
1728752cf8SGong Qianyu		spi1 = &dspi0;
1828752cf8SGong Qianyu        };
1928752cf8SGong Qianyu
2028752cf8SGong Qianyu};
2128752cf8SGong Qianyu
2228752cf8SGong Qianyu&dspi0 {
2328752cf8SGong Qianyu	bus-num = <0>;
2428752cf8SGong Qianyu	status = "okay";
2528752cf8SGong Qianyu
2628752cf8SGong Qianyu	dspiflash: n25q12a {
2728752cf8SGong Qianyu		#address-cells = <1>;
2828752cf8SGong Qianyu		#size-cells = <1>;
2928752cf8SGong Qianyu		compatible = "spi-flash";
3028752cf8SGong Qianyu		reg = <0>;
3128752cf8SGong Qianyu		spi-max-frequency = <1000000>; /* input clock */
3228752cf8SGong Qianyu	};
3328752cf8SGong Qianyu
34e1cecb4dSGong Qianyu};
35e1cecb4dSGong Qianyu
36e1cecb4dSGong Qianyu&i2c0 {
37e1cecb4dSGong Qianyu	status = "okay";
38e1cecb4dSGong Qianyu	ina220@40 {
39e1cecb4dSGong Qianyu		compatible = "ti,ina220";
40e1cecb4dSGong Qianyu		reg = <0x40>;
41e1cecb4dSGong Qianyu		shunt-resistor = <1000>;
42e1cecb4dSGong Qianyu	};
43e1cecb4dSGong Qianyu	adt7461a@4c {
44e1cecb4dSGong Qianyu		compatible = "adi,adt7461a";
45e1cecb4dSGong Qianyu		reg = <0x4c>;
46e1cecb4dSGong Qianyu	};
47f667d86eSHou Zhiqiang	eeprom@52 {
48e1cecb4dSGong Qianyu		compatible = "at24,24c512";
49e1cecb4dSGong Qianyu		reg = <0x52>;
50e1cecb4dSGong Qianyu	};
51e1cecb4dSGong Qianyu
52f667d86eSHou Zhiqiang	eeprom@53 {
53e1cecb4dSGong Qianyu		compatible = "at24,24c512";
54e1cecb4dSGong Qianyu		reg = <0x53>;
55e1cecb4dSGong Qianyu	};
56e1cecb4dSGong Qianyu
57e1cecb4dSGong Qianyu	rtc@68 {
58e1cecb4dSGong Qianyu		compatible = "pericom,pt7c4338";
59e1cecb4dSGong Qianyu		reg = <0x68>;
60e1cecb4dSGong Qianyu	};
61e1cecb4dSGong Qianyu};
62e1cecb4dSGong Qianyu
63e1cecb4dSGong Qianyu&ifc {
64e1cecb4dSGong Qianyu	status = "okay";
65e1cecb4dSGong Qianyu	#address-cells = <2>;
66e1cecb4dSGong Qianyu	#size-cells = <1>;
67e1cecb4dSGong Qianyu	/* NOR, NAND Flashes and FPGA on board */
68e1cecb4dSGong Qianyu	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
694002eab2SHou Zhiqiang		  0x1 0x0 0x0 0x7e800000 0x00010000
704002eab2SHou Zhiqiang		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
71e1cecb4dSGong Qianyu
72e1cecb4dSGong Qianyu		nor@0,0 {
73e1cecb4dSGong Qianyu			compatible = "cfi-flash";
74e1cecb4dSGong Qianyu			#address-cells = <1>;
75e1cecb4dSGong Qianyu			#size-cells = <1>;
76e1cecb4dSGong Qianyu			reg = <0x0 0x0 0x8000000>;
77e1cecb4dSGong Qianyu			bank-width = <2>;
78e1cecb4dSGong Qianyu			device-width = <1>;
79e1cecb4dSGong Qianyu		};
80e1cecb4dSGong Qianyu
81e1cecb4dSGong Qianyu		nand@1,0 {
82e1cecb4dSGong Qianyu			compatible = "fsl,ifc-nand";
83e1cecb4dSGong Qianyu			#address-cells = <1>;
84e1cecb4dSGong Qianyu			#size-cells = <1>;
85e1cecb4dSGong Qianyu			reg = <0x1 0x0 0x10000>;
86e1cecb4dSGong Qianyu		};
87e1cecb4dSGong Qianyu
88e1cecb4dSGong Qianyu		cpld: board-control@2,0 {
89e1cecb4dSGong Qianyu			compatible = "fsl,ls1043ardb-cpld";
90e1cecb4dSGong Qianyu			reg = <0x2 0x0 0x0000100>;
91e1cecb4dSGong Qianyu		};
92e1cecb4dSGong Qianyu};
93e1cecb4dSGong Qianyu
94e1cecb4dSGong Qianyu&duart0 {
95e1cecb4dSGong Qianyu	status = "okay";
96e1cecb4dSGong Qianyu};
97e1cecb4dSGong Qianyu
98e1cecb4dSGong Qianyu&duart1 {
99e1cecb4dSGong Qianyu	status = "okay";
100e1cecb4dSGong Qianyu};
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