1b63b995bSLokesh Vutla/* 2b63b995bSLokesh Vutla * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ 3b63b995bSLokesh Vutla * 4b63b995bSLokesh Vutla * SPDX-License-Identifier: GPL-2.0+ 5b63b995bSLokesh Vutla */ 6b63b995bSLokesh Vutla 7b63b995bSLokesh Vutla#include "omap5-u-boot.dtsi" 8b63b995bSLokesh Vutla 9b63b995bSLokesh Vutla&pcf_gpio_21{ 10b63b995bSLokesh Vutla u-boot,i2c-offset-len = <0>; 11b63b995bSLokesh Vutla}; 12b63b995bSLokesh Vutla 13b63b995bSLokesh Vutla&pcf_hdmi{ 14b63b995bSLokesh Vutla u-boot,i2c-offset-len = <0>; 15b63b995bSLokesh Vutla}; 16b63b995bSLokesh Vutla 17b63b995bSLokesh Vutla&cpsw_emac0 { 18b63b995bSLokesh Vutla phy-handle = <&dp83867_0>; 19b63b995bSLokesh Vutla}; 20b63b995bSLokesh Vutla 21b63b995bSLokesh Vutla&cpsw_emac1 { 22b63b995bSLokesh Vutla phy-handle = <&dp83867_1>; 23b63b995bSLokesh Vutla}; 24*938c3cfbSJean-Jacques Hiblot 25*938c3cfbSJean-Jacques Hiblot&mmc2_pins_default { 26*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 27*938c3cfbSJean-Jacques Hiblot}; 28*938c3cfbSJean-Jacques Hiblot 29*938c3cfbSJean-Jacques Hiblot&mmc2_pins_hs { 30*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 31*938c3cfbSJean-Jacques Hiblot}; 32*938c3cfbSJean-Jacques Hiblot 33*938c3cfbSJean-Jacques Hiblot&mmc2_pins_ddr_rev20 { 34*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 35*938c3cfbSJean-Jacques Hiblot}; 36*938c3cfbSJean-Jacques Hiblot 37*938c3cfbSJean-Jacques Hiblot&mmc2_iodelay_ddr_conf { 38*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 39*938c3cfbSJean-Jacques Hiblot}; 40*938c3cfbSJean-Jacques Hiblot 41*938c3cfbSJean-Jacques Hiblot&mmc2_pins_hs200 { 42*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 43*938c3cfbSJean-Jacques Hiblot}; 44*938c3cfbSJean-Jacques Hiblot 45*938c3cfbSJean-Jacques Hiblot&mmc2_iodelay_hs200_rev20_conf { 46*938c3cfbSJean-Jacques Hiblot u-boot,dm-spl; 47*938c3cfbSJean-Jacques Hiblot}; 48