1#include <dt-bindings/clock/ast2600-clock.h> 2#include <dt-bindings/reset/ast2600-reset.h> 3 4#include "ast2600.dtsi" 5 6/ { 7 scu: clock-controller@1e6e2000 { 8 compatible = "aspeed,ast2600-scu"; 9 reg = <0x1e6e2000 0x1000>; 10 u-boot,dm-pre-reloc; 11 #clock-cells = <1>; 12 #reset-cells = <1>; 13 }; 14 15 rst: reset-controller { 16 u-boot,dm-pre-reloc; 17 compatible = "aspeed,ast2600-reset"; 18 aspeed,wdt = <&wdt1>; 19 #reset-cells = <1>; 20 }; 21 22#if 0 23 sdrammc: sdrammc@1e6e0000 { 24 u-boot,dm-pre-reloc; 25 compatible = "aspeed,ast2600-sdrammc"; 26 reg = <0x1e6e0000 0x100 27 0x1e6e0100 0x300 28 0x1e6e0400 0x200 >; 29 #reset-cells = <1>; 30 clocks = <&scu ASPEED_CLK_MPLL>; 31 resets = <&rst AST_RESET_SDRAM>; 32 }; 33#endif 34 ahb { 35 u-boot,dm-pre-reloc; 36 37 apb { 38 u-boot,dm-pre-reloc; 39 }; 40 41 }; 42}; 43 44&uart1 { 45 clock-frequency = <1846154>; 46}; 47 48&uart2 { 49 clock-frequency = <1846154>; 50}; 51 52&uart3 { 53 clock-frequency = <1846154>; 54}; 55 56&uart4 { 57 clock-frequency = <1846154>; 58}; 59 60&uart5 { 61#if 0 62 clock-frequency = <1846154>; 63#endif 64 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 65}; 66 67&mac0 { 68 clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; 69}; 70 71&mac1 { 72 clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; 73}; 74 75&fmc { 76 clocks = <&scu ASPEED_CLK_AHB>; 77}; 78 79&spi1 { 80 clocks = <&scu ASPEED_CLK_AHB>; 81}; 82 83&spi2 { 84 clocks = <&scu ASPEED_CLK_AHB>; 85}; 86