1#include <dt-bindings/clock/ast2600-clock.h> 2#include <dt-bindings/reset/ast2600-reset.h> 3 4#include "ast2600.dtsi" 5 6/ { 7 scu: clock-controller@1e6e2000 { 8 compatible = "aspeed,ast2600-scu"; 9 reg = <0x1e6e2000 0x1000>; 10 u-boot,dm-pre-reloc; 11 #clock-cells = <1>; 12 #reset-cells = <1>; 13 }; 14 15 rst: reset-controller { 16 u-boot,dm-pre-reloc; 17 compatible = "aspeed,ast2600-reset"; 18 aspeed,wdt = <&wdt1>; 19 #reset-cells = <1>; 20 }; 21 22#if 0 23 sdrammc: sdrammc@1e6e0000 { 24 u-boot,dm-pre-reloc; 25 compatible = "aspeed,ast2600-sdrammc"; 26 reg = <0x1e6e0000 0x100 27 0x1e6e0100 0x600 >; 28 #reset-cells = <1>; 29 clocks = <&scu ASPEED_CLK_MPLL>; 30 resets = <&rst AST_RESET_SDRAM>; 31 }; 32#endif 33 ahb { 34 u-boot,dm-pre-reloc; 35 36 apb { 37 u-boot,dm-pre-reloc; 38 }; 39 40 }; 41}; 42 43&uart1 { 44 clock-frequency = <1846154>; 45}; 46 47&uart2 { 48 clock-frequency = <1846154>; 49}; 50 51&uart3 { 52 clock-frequency = <1846154>; 53}; 54 55&uart4 { 56 clock-frequency = <1846154>; 57}; 58 59&uart5 { 60#if 0 61 clock-frequency = <1846154>; 62#endif 63 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 64}; 65 66&mac0 { 67 clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; 68}; 69 70&mac1 { 71 clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; 72}; 73 74&fmc { 75 clocks = <&scu ASPEED_CLK_AHB>; 76}; 77 78&spi1 { 79 clocks = <&scu ASPEED_CLK_AHB>; 80}; 81 82&spi2 { 83 clocks = <&scu ASPEED_CLK_AHB>; 84}; 85