1#include <dt-bindings/clock/ast2600-clock.h> 2#include <dt-bindings/reset/ast2600-reset.h> 3 4#include "ast2600.dtsi" 5 6/ { 7 scu: clock-controller@1e6e2000 { 8 compatible = "aspeed,ast2600-scu"; 9 reg = <0x1e6e2000 0x1000>; 10 u-boot,dm-pre-reloc; 11 #clock-cells = <1>; 12 #reset-cells = <1>; 13 }; 14 15 rst: reset-controller { 16 u-boot,dm-pre-reloc; 17 compatible = "aspeed,ast2600-reset"; 18 aspeed,wdt = <&wdt1>; 19 #reset-cells = <1>; 20 }; 21 22 sdrammc: sdrammc@1e6e0000 { 23 u-boot,dm-pre-reloc; 24 compatible = "aspeed,ast2600-sdrammc"; 25 reg = <0x1e6e0000 0x100 26 0x1e6e0100 0x300 27 0x1e6e0400 0x200 >; 28 #reset-cells = <1>; 29 clocks = <&scu ASPEED_CLK_MPLL>; 30#if 0 31 resets = <&rst AST_RESET_SDRAM>; 32#endif 33 }; 34 35 ahb { 36 u-boot,dm-pre-reloc; 37 38 apb { 39 u-boot,dm-pre-reloc; 40 }; 41 42 }; 43}; 44 45&uart1 { 46 clock-frequency = <1846154>; 47}; 48 49&uart2 { 50 clock-frequency = <1846154>; 51}; 52 53&uart3 { 54 clock-frequency = <1846154>; 55}; 56 57&uart4 { 58 clock-frequency = <1846154>; 59}; 60 61&uart5 { 62#if 0 63 clock-frequency = <1846154>; 64#endif 65 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 66}; 67 68&mac0 { 69 clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; 70}; 71 72&mac1 { 73 clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; 74}; 75 76&fmc { 77 clocks = <&scu ASPEED_CLK_AHB>; 78}; 79 80&spi1 { 81 clocks = <&scu ASPEED_CLK_AHB>; 82}; 83 84&spi2 { 85 clocks = <&scu ASPEED_CLK_AHB>; 86}; 87