121fbc057SRyan Chen/dts-v1/; 221fbc057SRyan Chen 321fbc057SRyan Chen#include "ast2600-u-boot.dtsi" 421fbc057SRyan Chen 521fbc057SRyan Chen/ { 6ba6ce662SJoel Stanley model = "AST2600 EVB"; 7ba6ce662SJoel Stanley compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 8ba6ce662SJoel Stanley 921fbc057SRyan Chen memory { 1021fbc057SRyan Chen device_type = "memory"; 1121fbc057SRyan Chen reg = <0x80000000 0x40000000>; 1221fbc057SRyan Chen }; 1321fbc057SRyan Chen 1421fbc057SRyan Chen chosen { 1521fbc057SRyan Chen stdout-path = &uart5; 1621fbc057SRyan Chen }; 1721fbc057SRyan Chen 1821fbc057SRyan Chen aliases { 1921fbc057SRyan Chen mmc0 = &emmc_slot0; 2021fbc057SRyan Chen mmc1 = &sdhci_slot0; 2121fbc057SRyan Chen mmc2 = &sdhci_slot1; 2221fbc057SRyan Chen spi0 = &fmc; 2321fbc057SRyan Chen spi1 = &spi1; 2421fbc057SRyan Chen spi2 = &spi2; 2521fbc057SRyan Chen ethernet0 = &mac0; 2621fbc057SRyan Chen ethernet1 = &mac1; 2721fbc057SRyan Chen ethernet2 = &mac2; 2821fbc057SRyan Chen ethernet3 = &mac3; 2921fbc057SRyan Chen }; 3021fbc057SRyan Chen 3121fbc057SRyan Chen cpus { 3221fbc057SRyan Chen cpu@0 { 3321fbc057SRyan Chen clock-frequency = <800000000>; 3421fbc057SRyan Chen }; 3521fbc057SRyan Chen cpu@1 { 3621fbc057SRyan Chen clock-frequency = <800000000>; 3721fbc057SRyan Chen }; 3821fbc057SRyan Chen }; 3921fbc057SRyan Chen}; 4021fbc057SRyan Chen 4121fbc057SRyan Chen&uart5 { 4221fbc057SRyan Chen u-boot,dm-pre-reloc; 4321fbc057SRyan Chen status = "okay"; 4421fbc057SRyan Chen}; 4521fbc057SRyan Chen 4621fbc057SRyan Chen&sdrammc { 4721fbc057SRyan Chen clock-frequency = <400000000>; 4821fbc057SRyan Chen}; 4921fbc057SRyan Chen 5021fbc057SRyan Chen&wdt1 { 5121fbc057SRyan Chen status = "okay"; 5221fbc057SRyan Chen}; 5321fbc057SRyan Chen 5421fbc057SRyan Chen&wdt2 { 5521fbc057SRyan Chen status = "okay"; 5621fbc057SRyan Chen}; 5721fbc057SRyan Chen 5821fbc057SRyan Chen&wdt3 { 5921fbc057SRyan Chen status = "okay"; 6021fbc057SRyan Chen}; 6121fbc057SRyan Chen 6221fbc057SRyan Chen&mdio { 6321fbc057SRyan Chen status = "okay"; 6421fbc057SRyan Chen pinctrl-names = "default"; 6521fbc057SRyan Chen pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default 6621fbc057SRyan Chen &pinctrl_mdio3_default &pinctrl_mdio4_default>; 6721fbc057SRyan Chen #address-cells = <1>; 6821fbc057SRyan Chen #size-cells = <0>; 6921fbc057SRyan Chen ethphy0: ethernet-phy@0 { 7021fbc057SRyan Chen reg = <0>; 7121fbc057SRyan Chen }; 7221fbc057SRyan Chen 7321fbc057SRyan Chen ethphy1: ethernet-phy@1 { 7421fbc057SRyan Chen reg = <0>; 7521fbc057SRyan Chen }; 7621fbc057SRyan Chen 7721fbc057SRyan Chen ethphy2: ethernet-phy@2 { 7821fbc057SRyan Chen reg = <0>; 7921fbc057SRyan Chen }; 8021fbc057SRyan Chen 8121fbc057SRyan Chen ethphy3: ethernet-phy@3 { 8221fbc057SRyan Chen reg = <0>; 8321fbc057SRyan Chen }; 8421fbc057SRyan Chen}; 8521fbc057SRyan Chen 8621fbc057SRyan Chen&mac0 { 8721fbc057SRyan Chen status = "okay"; 88a2737e7dSDylan Hung phy-mode = "rgmii-rxid"; 8921fbc057SRyan Chen phy-handle = <ðphy0>; 9021fbc057SRyan Chen pinctrl-names = "default"; 91c7c4c2d9SDylan Hung pinctrl-0 = <&pinctrl_rgmii1_default>; 9221fbc057SRyan Chen}; 9321fbc057SRyan Chen 9421fbc057SRyan Chen&mac1 { 9521fbc057SRyan Chen status = "okay"; 96a2737e7dSDylan Hung phy-mode = "rgmii-rxid"; 9721fbc057SRyan Chen phy-handle = <ðphy1>; 9821fbc057SRyan Chen pinctrl-names = "default"; 99c7c4c2d9SDylan Hung pinctrl-0 = <&pinctrl_rgmii2_default>; 10021fbc057SRyan Chen}; 10121fbc057SRyan Chen 10221fbc057SRyan Chen&mac2 { 10321fbc057SRyan Chen status = "okay"; 10421fbc057SRyan Chen phy-mode = "rgmii"; 10521fbc057SRyan Chen phy-handle = <ðphy2>; 10621fbc057SRyan Chen pinctrl-names = "default"; 107c7c4c2d9SDylan Hung pinctrl-0 = <&pinctrl_rgmii3_default>; 10821fbc057SRyan Chen}; 10921fbc057SRyan Chen 11021fbc057SRyan Chen&mac3 { 11121fbc057SRyan Chen status = "okay"; 11221fbc057SRyan Chen phy-mode = "rgmii"; 11321fbc057SRyan Chen phy-handle = <ðphy3>; 11421fbc057SRyan Chen pinctrl-names = "default"; 115c7c4c2d9SDylan Hung pinctrl-0 = <&pinctrl_rgmii4_default>; 11621fbc057SRyan Chen}; 11721fbc057SRyan Chen 11821fbc057SRyan Chen&fmc { 11921fbc057SRyan Chen status = "okay"; 12021fbc057SRyan Chen 12121fbc057SRyan Chen pinctrl-names = "default"; 12221fbc057SRyan Chen pinctrl-0 = <&pinctrl_fmcquad_default>; 12321fbc057SRyan Chen 12421fbc057SRyan Chen flash@0 { 12521fbc057SRyan Chen status = "okay"; 12621fbc057SRyan Chen spi-max-frequency = <50000000>; 12721fbc057SRyan Chen spi-tx-bus-width = <4>; 12821fbc057SRyan Chen spi-rx-bus-width = <4>; 12921fbc057SRyan Chen }; 13021fbc057SRyan Chen 13121fbc057SRyan Chen flash@1 { 13221fbc057SRyan Chen status = "okay"; 13321fbc057SRyan Chen spi-max-frequency = <50000000>; 13421fbc057SRyan Chen spi-tx-bus-width = <4>; 13521fbc057SRyan Chen spi-rx-bus-width = <4>; 13621fbc057SRyan Chen }; 13721fbc057SRyan Chen 13821fbc057SRyan Chen flash@2 { 139c6770dd5SChin-Ting Kuo status = "disabled"; 14021fbc057SRyan Chen spi-max-frequency = <50000000>; 14121fbc057SRyan Chen spi-tx-bus-width = <4>; 14221fbc057SRyan Chen spi-rx-bus-width = <4>; 14321fbc057SRyan Chen }; 14421fbc057SRyan Chen}; 14521fbc057SRyan Chen 14621fbc057SRyan Chen&spi1 { 14721fbc057SRyan Chen status = "okay"; 14821fbc057SRyan Chen 14921fbc057SRyan Chen pinctrl-names = "default"; 15021fbc057SRyan Chen pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default 15121fbc057SRyan Chen &pinctrl_spi1cs1_default &pinctrl_spi1wp_default 15221fbc057SRyan Chen &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; 15321fbc057SRyan Chen 15421fbc057SRyan Chen flash@0 { 15521fbc057SRyan Chen status = "okay"; 15621fbc057SRyan Chen spi-max-frequency = <50000000>; 15721fbc057SRyan Chen spi-tx-bus-width = <4>; 15821fbc057SRyan Chen spi-rx-bus-width = <4>; 15921fbc057SRyan Chen }; 16021fbc057SRyan Chen 16121fbc057SRyan Chen flash@1 { 162c6770dd5SChin-Ting Kuo status = "disabled"; 16321fbc057SRyan Chen spi-max-frequency = <50000000>; 16421fbc057SRyan Chen spi-tx-bus-width = <4>; 16521fbc057SRyan Chen spi-rx-bus-width = <4>; 16621fbc057SRyan Chen }; 16721fbc057SRyan Chen}; 16821fbc057SRyan Chen 16921fbc057SRyan Chen&spi2 { 17021fbc057SRyan Chen status = "okay"; 17121fbc057SRyan Chen 17221fbc057SRyan Chen pinctrl-names = "default"; 17321fbc057SRyan Chen pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default 17421fbc057SRyan Chen &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; 17521fbc057SRyan Chen 17621fbc057SRyan Chen flash@0 { 17721fbc057SRyan Chen status = "okay"; 17821fbc057SRyan Chen spi-max-frequency = <50000000>; 17921fbc057SRyan Chen spi-tx-bus-width = <4>; 18021fbc057SRyan Chen spi-rx-bus-width = <4>; 18121fbc057SRyan Chen }; 18221fbc057SRyan Chen 18321fbc057SRyan Chen flash@1 { 184c6770dd5SChin-Ting Kuo status = "disabled"; 18521fbc057SRyan Chen spi-max-frequency = <50000000>; 18621fbc057SRyan Chen spi-tx-bus-width = <4>; 18721fbc057SRyan Chen spi-rx-bus-width = <4>; 18821fbc057SRyan Chen }; 18921fbc057SRyan Chen 19021fbc057SRyan Chen flash@2 { 191c6770dd5SChin-Ting Kuo status = "disabled"; 19221fbc057SRyan Chen spi-max-frequency = <50000000>; 19321fbc057SRyan Chen spi-tx-bus-width = <4>; 19421fbc057SRyan Chen spi-rx-bus-width = <4>; 19521fbc057SRyan Chen }; 19621fbc057SRyan Chen}; 19721fbc057SRyan Chen 19821fbc057SRyan Chen&emmc { 19921fbc057SRyan Chen u-boot,dm-pre-reloc; 200fd45780cSChin-Ting Kuo timing-phase = <0x000f0097>; 20121fbc057SRyan Chen}; 20221fbc057SRyan Chen 20321fbc057SRyan Chen&emmc_slot0 { 20421fbc057SRyan Chen u-boot,dm-pre-reloc; 20521fbc057SRyan Chen status = "okay"; 20621fbc057SRyan Chen bus-width = <4>; 20721fbc057SRyan Chen pinctrl-names = "default"; 20821fbc057SRyan Chen pinctrl-0 = <&pinctrl_emmc_default>; 20921fbc057SRyan Chen sdhci-drive-type = <1>; 21021fbc057SRyan Chen}; 21121fbc057SRyan Chen 21221fbc057SRyan Chen&sdhci { 213fd45780cSChin-Ting Kuo timing-phase = <0x00c6375f>; 21421fbc057SRyan Chen}; 21521fbc057SRyan Chen 21621fbc057SRyan Chen&sdhci_slot0 { 21721fbc057SRyan Chen status = "okay"; 21821fbc057SRyan Chen bus-width = <4>; 21921fbc057SRyan Chen pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 22021fbc057SRyan Chen pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 22121fbc057SRyan Chen pinctrl-names = "default"; 22221fbc057SRyan Chen pinctrl-0 = <&pinctrl_sd1_default>; 22321fbc057SRyan Chen sdhci-drive-type = <1>; 22421fbc057SRyan Chen}; 22521fbc057SRyan Chen 22621fbc057SRyan Chen&sdhci_slot1 { 22721fbc057SRyan Chen status = "okay"; 22821fbc057SRyan Chen bus-width = <4>; 22921fbc057SRyan Chen pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 23021fbc057SRyan Chen pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 23121fbc057SRyan Chen pinctrl-names = "default"; 23221fbc057SRyan Chen pinctrl-0 = <&pinctrl_sd2_default>; 23321fbc057SRyan Chen sdhci-drive-type = <1>; 23421fbc057SRyan Chen}; 23521fbc057SRyan Chen 23621fbc057SRyan Chen&i2c4 { 23721fbc057SRyan Chen status = "okay"; 23821fbc057SRyan Chen 23921fbc057SRyan Chen pinctrl-names = "default"; 24021fbc057SRyan Chen pinctrl-0 = <&pinctrl_i2c5_default>; 24121fbc057SRyan Chen}; 24221fbc057SRyan Chen 24321fbc057SRyan Chen&i2c5 { 24421fbc057SRyan Chen status = "okay"; 24521fbc057SRyan Chen 24621fbc057SRyan Chen pinctrl-names = "default"; 24721fbc057SRyan Chen pinctrl-0 = <&pinctrl_i2c6_default>; 24821fbc057SRyan Chen}; 24921fbc057SRyan Chen 25021fbc057SRyan Chen&i2c6 { 25121fbc057SRyan Chen status = "okay"; 25221fbc057SRyan Chen 25321fbc057SRyan Chen pinctrl-names = "default"; 25421fbc057SRyan Chen pinctrl-0 = <&pinctrl_i2c7_default>; 25521fbc057SRyan Chen}; 25621fbc057SRyan Chen 25721fbc057SRyan Chen&i2c7 { 25821fbc057SRyan Chen status = "okay"; 25921fbc057SRyan Chen 26021fbc057SRyan Chen pinctrl-names = "default"; 26121fbc057SRyan Chen pinctrl-0 = <&pinctrl_i2c8_default>; 26221fbc057SRyan Chen}; 26321fbc057SRyan Chen 26421fbc057SRyan Chen&i2c8 { 26521fbc057SRyan Chen status = "okay"; 26621fbc057SRyan Chen 26721fbc057SRyan Chen pinctrl-names = "default"; 26821fbc057SRyan Chen pinctrl-0 = <&pinctrl_i2c9_default>; 26921fbc057SRyan Chen}; 27021fbc057SRyan Chen 271*47ac369cSryan_chen&pcie_phy1 { 27221fbc057SRyan Chen status = "okay"; 27321fbc057SRyan Chen}; 27421fbc057SRyan Chen 27589e8db20SRyan Chen&pcie_bridge { 27621fbc057SRyan Chen status = "okay"; 27721fbc057SRyan Chen}; 27821fbc057SRyan Chen 27921fbc057SRyan Chen#if 0 28021fbc057SRyan Chen&fsim0 { 28121fbc057SRyan Chen status = "okay"; 28221fbc057SRyan Chen}; 28321fbc057SRyan Chen 28421fbc057SRyan Chen&fsim1 { 28521fbc057SRyan Chen status = "okay"; 28621fbc057SRyan Chen}; 28721fbc057SRyan Chen#endif 28821fbc057SRyan Chen 289f1f7e107Sneal_liu#if 0 290f1f7e107Sneal_liu&vhub { 291f1f7e107Sneal_liu status = "okay"; 292f1f7e107Sneal_liu}; 293f1f7e107Sneal_liu#endif 294f1f7e107Sneal_liu 29521fbc057SRyan Chen&ehci1 { 29621fbc057SRyan Chen status = "okay"; 29721fbc057SRyan Chen}; 29821fbc057SRyan Chen 29921fbc057SRyan Chen&display_port { 30021fbc057SRyan Chen status = "okay"; 30121fbc057SRyan Chen}; 30221fbc057SRyan Chen 30321fbc057SRyan Chen&scu { 304758c0fd5SDylan Hung mac0-clk-delay = <0x10 0x0a 305a2737e7dSDylan Hung 0x10 0x10 306a2737e7dSDylan Hung 0x10 0x10>; 307758c0fd5SDylan Hung mac1-clk-delay = <0x10 0x0a 30821fbc057SRyan Chen 0x10 0x10 30921fbc057SRyan Chen 0x10 0x10>; 310758c0fd5SDylan Hung mac2-clk-delay = <0x08 0x04 31121fbc057SRyan Chen 0x08 0x04 31221fbc057SRyan Chen 0x08 0x04>; 313758c0fd5SDylan Hung mac3-clk-delay = <0x08 0x04 31421fbc057SRyan Chen 0x08 0x04 31521fbc057SRyan Chen 0x08 0x04>; 31621fbc057SRyan Chen}; 317381dd975SChia-Wei Wang 318381dd975SChia-Wei Wang&hace { 319381dd975SChia-Wei Wang u-boot,dm-pre-reloc; 320381dd975SChia-Wei Wang status = "okay"; 321381dd975SChia-Wei Wang}; 322294abd88SChia-Wei Wang 3234f7bd3b2SChia-Wei Wang&acry { 324294abd88SChia-Wei Wang u-boot,dm-pre-reloc; 325294abd88SChia-Wei Wang status = "okay"; 326294abd88SChia-Wei Wang}; 327