180af1a9eSMarek Behún// SPDX-License-Identifier: GPL-2.0+ or X11 280af1a9eSMarek Behún/* 380af1a9eSMarek Behún * Device Tree file for CZ.NIC Turris Mox Board 480af1a9eSMarek Behún * 2018 by Marek Behun <marek.behun@nic.cz> 580af1a9eSMarek Behún * 680af1a9eSMarek Behún * Based on armada-3720-espressobin.dts by: 780af1a9eSMarek Behún * Gregory CLEMENT <gregory.clement@free-electrons.com> 880af1a9eSMarek Behún * Konstantin Porotchkin <kostap@marvell.com> 980af1a9eSMarek Behún */ 1080af1a9eSMarek Behún 1180af1a9eSMarek Behún/dts-v1/; 1280af1a9eSMarek Behún 1380af1a9eSMarek Behún#include <dt-bindings/gpio/gpio.h> 1480af1a9eSMarek Behún#include "armada-372x.dtsi" 1580af1a9eSMarek Behún 1680af1a9eSMarek Behún/ { 1780af1a9eSMarek Behún model = "CZ.NIC Turris Mox Board"; 1880af1a9eSMarek Behún compatible = "cznic,turris-mox", "marvell,armada3720", 1980af1a9eSMarek Behún "marvell,armada3710"; 2080af1a9eSMarek Behún 2180af1a9eSMarek Behún chosen { 2280af1a9eSMarek Behún stdout-path = "serial0:115200n8"; 2380af1a9eSMarek Behún }; 2480af1a9eSMarek Behún 2580af1a9eSMarek Behún aliases { 2680af1a9eSMarek Behún ethernet0 = ð0; 27*3dc2f454SMarek Behún ethernet1 = ð1; 2880af1a9eSMarek Behún i2c0 = &i2c0; 2980af1a9eSMarek Behún spi0 = &spi0; 3080af1a9eSMarek Behún }; 3180af1a9eSMarek Behún 3280af1a9eSMarek Behún memory { 3380af1a9eSMarek Behún device_type = "memory"; 3480af1a9eSMarek Behún reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 3580af1a9eSMarek Behún }; 3680af1a9eSMarek Behún 3780af1a9eSMarek Behún reg_usb3_vbus: usb3_vbus@0 { 3880af1a9eSMarek Behún compatible = "regulator-fixed"; 3980af1a9eSMarek Behún regulator-name = "usb3-vbus"; 4080af1a9eSMarek Behún regulator-min-microvolt = <5000000>; 4180af1a9eSMarek Behún regulator-max-microvolt = <5000000>; 42*3dc2f454SMarek Behún startup-delay-us = <2000000>; 4380af1a9eSMarek Behún shutdown-delay-us = <1000000>; 4480af1a9eSMarek Behún gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 4580af1a9eSMarek Behún regulator-boot-on; 4680af1a9eSMarek Behún }; 4780af1a9eSMarek Behún 4880af1a9eSMarek Behún mdio { 49*3dc2f454SMarek Behún #address-cells = <1>; 50*3dc2f454SMarek Behún #size-cells = <0>; 51*3dc2f454SMarek Behún 5280af1a9eSMarek Behún eth_phy1: ethernet-phy@1 { 5380af1a9eSMarek Behún reg = <1>; 5480af1a9eSMarek Behún }; 5580af1a9eSMarek Behún }; 5680af1a9eSMarek Behún}; 5780af1a9eSMarek Behún 5880af1a9eSMarek Behún&comphy { 5980af1a9eSMarek Behún max-lanes = <3>; 6080af1a9eSMarek Behún phy0 { 6180af1a9eSMarek Behún phy-type = <PHY_TYPE_SGMII1>; 6280af1a9eSMarek Behún phy-speed = <PHY_SPEED_3_125G>; 6380af1a9eSMarek Behún }; 6480af1a9eSMarek Behún 6580af1a9eSMarek Behún phy1 { 6680af1a9eSMarek Behún phy-type = <PHY_TYPE_PEX0>; 67*3dc2f454SMarek Behún phy-speed = <PHY_SPEED_5G>; 6880af1a9eSMarek Behún }; 6980af1a9eSMarek Behún 7080af1a9eSMarek Behún phy2 { 7180af1a9eSMarek Behún phy-type = <PHY_TYPE_USB3_HOST0>; 7280af1a9eSMarek Behún phy-speed = <PHY_SPEED_5G>; 7380af1a9eSMarek Behún }; 7480af1a9eSMarek Behún}; 7580af1a9eSMarek Behún 7680af1a9eSMarek Behúnð0 { 7780af1a9eSMarek Behún status = "okay"; 7880af1a9eSMarek Behún pinctrl-names = "default"; 7980af1a9eSMarek Behún pinctrl-0 = <&rgmii_pins>, <&smi_pins>; 8080af1a9eSMarek Behún phy-mode = "rgmii"; 8180af1a9eSMarek Behún phy = <ð_phy1>; 8280af1a9eSMarek Behún}; 8380af1a9eSMarek Behún 8480af1a9eSMarek Behún&i2c0 { 8580af1a9eSMarek Behún pinctrl-names = "default"; 8680af1a9eSMarek Behún pinctrl-0 = <&i2c1_pins>; 8780af1a9eSMarek Behún status = "okay"; 88*3dc2f454SMarek Behún 89*3dc2f454SMarek Behún rtc@6f { 90*3dc2f454SMarek Behún compatible = "microchip,mcp7941x"; 91*3dc2f454SMarek Behún reg = <0x6f>; 92*3dc2f454SMarek Behún }; 9380af1a9eSMarek Behún}; 9480af1a9eSMarek Behún 9580af1a9eSMarek Behún&sdhci1 { 9680af1a9eSMarek Behún bus-width = <4>; 9780af1a9eSMarek Behún status = "okay"; 9880af1a9eSMarek Behún}; 9980af1a9eSMarek Behún 10080af1a9eSMarek Behún&pinctrl_nb { 10180af1a9eSMarek Behún spi_cs1_pins: spi-cs1-pins { 10280af1a9eSMarek Behún groups = "spi_cs1"; 10380af1a9eSMarek Behún function = "spi"; 10480af1a9eSMarek Behún }; 10580af1a9eSMarek Behún}; 10680af1a9eSMarek Behún 10780af1a9eSMarek Behún&spi0 { 10880af1a9eSMarek Behún status = "okay"; 10980af1a9eSMarek Behún pinctrl-names = "default"; 11080af1a9eSMarek Behún pinctrl-0 = <&spi_cs1_pins>; 1110f6686e2SMarek Behún assigned-clocks = <&nb_periph_clk 7>; 1120f6686e2SMarek Behún assigned-clock-parents = <&tbg 1>; 1130f6686e2SMarek Behún assigned-clock-rates = <20000000>; 11480af1a9eSMarek Behún 11580af1a9eSMarek Behún spi-flash@0 { 11680af1a9eSMarek Behún #address-cells = <1>; 11780af1a9eSMarek Behún #size-cells = <1>; 11880af1a9eSMarek Behún compatible = "st,s25fl064l", "spi-flash"; 11980af1a9eSMarek Behún reg = <0>; 12080af1a9eSMarek Behún spi-max-frequency = <20000000>; 12180af1a9eSMarek Behún m25p,fast-read; 12280af1a9eSMarek Behún }; 1237dd7c2e7SMarek Behún 1247dd7c2e7SMarek Behún moxtet@1 { 1257dd7c2e7SMarek Behún #address-cells = <1>; 1267dd7c2e7SMarek Behún #size-cells = <0>; 1277dd7c2e7SMarek Behún compatible = "cznic,moxtet"; 1287dd7c2e7SMarek Behún reg = <1>; 1297dd7c2e7SMarek Behún reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 1307dd7c2e7SMarek Behún spi-max-frequency = <1000000>; 1317dd7c2e7SMarek Behún spi-cpol; 1327dd7c2e7SMarek Behún spi-cpha; 1337dd7c2e7SMarek Behún }; 13480af1a9eSMarek Behún}; 13580af1a9eSMarek Behún 13680af1a9eSMarek Behún&uart0 { 13780af1a9eSMarek Behún pinctrl-names = "default"; 13880af1a9eSMarek Behún pinctrl-0 = <&uart1_pins>; 13980af1a9eSMarek Behún status = "okay"; 14080af1a9eSMarek Behún}; 14180af1a9eSMarek Behún 14280af1a9eSMarek Behún&usb2 { 14380af1a9eSMarek Behún status = "okay"; 14480af1a9eSMarek Behún}; 14580af1a9eSMarek Behún 14680af1a9eSMarek Behún&usb3 { 14780af1a9eSMarek Behún vbus-supply = <®_usb3_vbus>; 14880af1a9eSMarek Behún status = "okay"; 14980af1a9eSMarek Behún}; 150863949e3SMarek Behún 151863949e3SMarek Behún&pcie0 { 152863949e3SMarek Behún pinctrl-names = "default"; 153863949e3SMarek Behún pinctrl-0 = <&pcie_pins>; 154863949e3SMarek Behún reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>; 155863949e3SMarek Behún status = "disabled"; 156863949e3SMarek Behún}; 157