1*7dd12830SLokesh Vutla/* 2*7dd12830SLokesh Vutla * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3*7dd12830SLokesh Vutla * 4*7dd12830SLokesh Vutla * This program is free software; you can redistribute it and/or modify 5*7dd12830SLokesh Vutla * it under the terms of the GNU General Public License version 2 as 6*7dd12830SLokesh Vutla * published by the Free Software Foundation. 7*7dd12830SLokesh Vutla */ 8*7dd12830SLokesh Vutla 9*7dd12830SLokesh Vutla/* AM43x EPOS EVM */ 10*7dd12830SLokesh Vutla 11*7dd12830SLokesh Vutla/dts-v1/; 12*7dd12830SLokesh Vutla 13*7dd12830SLokesh Vutla#include "am4372.dtsi" 14*7dd12830SLokesh Vutla#include <dt-bindings/pinctrl/am43xx.h> 15*7dd12830SLokesh Vutla#include <dt-bindings/gpio/gpio.h> 16*7dd12830SLokesh Vutla#include <dt-bindings/pwm/pwm.h> 17*7dd12830SLokesh Vutla#include <dt-bindings/sound/tlv320aic31xx-micbias.h> 18*7dd12830SLokesh Vutla 19*7dd12830SLokesh Vutla/ { 20*7dd12830SLokesh Vutla model = "TI AM43x EPOS EVM"; 21*7dd12830SLokesh Vutla compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; 22*7dd12830SLokesh Vutla 23*7dd12830SLokesh Vutla aliases { 24*7dd12830SLokesh Vutla display0 = &lcd0; 25*7dd12830SLokesh Vutla }; 26*7dd12830SLokesh Vutla 27*7dd12830SLokesh Vutla chosen { 28*7dd12830SLokesh Vutla stdout-path = &uart0; 29*7dd12830SLokesh Vutla tick-timer = &timer2; 30*7dd12830SLokesh Vutla }; 31*7dd12830SLokesh Vutla 32*7dd12830SLokesh Vutla vmmcsd_fixed: fixedregulator-sd { 33*7dd12830SLokesh Vutla compatible = "regulator-fixed"; 34*7dd12830SLokesh Vutla regulator-name = "vmmcsd_fixed"; 35*7dd12830SLokesh Vutla regulator-min-microvolt = <3300000>; 36*7dd12830SLokesh Vutla regulator-max-microvolt = <3300000>; 37*7dd12830SLokesh Vutla enable-active-high; 38*7dd12830SLokesh Vutla }; 39*7dd12830SLokesh Vutla 40*7dd12830SLokesh Vutla vbat: fixedregulator@0 { 41*7dd12830SLokesh Vutla compatible = "regulator-fixed"; 42*7dd12830SLokesh Vutla regulator-name = "vbat"; 43*7dd12830SLokesh Vutla regulator-min-microvolt = <5000000>; 44*7dd12830SLokesh Vutla regulator-max-microvolt = <5000000>; 45*7dd12830SLokesh Vutla regulator-boot-on; 46*7dd12830SLokesh Vutla }; 47*7dd12830SLokesh Vutla 48*7dd12830SLokesh Vutla lcd0: display { 49*7dd12830SLokesh Vutla compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; 50*7dd12830SLokesh Vutla label = "lcd"; 51*7dd12830SLokesh Vutla 52*7dd12830SLokesh Vutla panel-timing { 53*7dd12830SLokesh Vutla clock-frequency = <33000000>; 54*7dd12830SLokesh Vutla hactive = <800>; 55*7dd12830SLokesh Vutla vactive = <480>; 56*7dd12830SLokesh Vutla hfront-porch = <210>; 57*7dd12830SLokesh Vutla hback-porch = <16>; 58*7dd12830SLokesh Vutla hsync-len = <30>; 59*7dd12830SLokesh Vutla vback-porch = <10>; 60*7dd12830SLokesh Vutla vfront-porch = <22>; 61*7dd12830SLokesh Vutla vsync-len = <13>; 62*7dd12830SLokesh Vutla hsync-active = <0>; 63*7dd12830SLokesh Vutla vsync-active = <0>; 64*7dd12830SLokesh Vutla de-active = <1>; 65*7dd12830SLokesh Vutla pixelclk-active = <1>; 66*7dd12830SLokesh Vutla }; 67*7dd12830SLokesh Vutla 68*7dd12830SLokesh Vutla port { 69*7dd12830SLokesh Vutla lcd_in: endpoint { 70*7dd12830SLokesh Vutla remote-endpoint = <&dpi_out>; 71*7dd12830SLokesh Vutla }; 72*7dd12830SLokesh Vutla }; 73*7dd12830SLokesh Vutla }; 74*7dd12830SLokesh Vutla 75*7dd12830SLokesh Vutla matrix_keypad: matrix_keypad@0 { 76*7dd12830SLokesh Vutla compatible = "gpio-matrix-keypad"; 77*7dd12830SLokesh Vutla debounce-delay-ms = <5>; 78*7dd12830SLokesh Vutla col-scan-delay-us = <2>; 79*7dd12830SLokesh Vutla 80*7dd12830SLokesh Vutla row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 81*7dd12830SLokesh Vutla &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 82*7dd12830SLokesh Vutla &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 83*7dd12830SLokesh Vutla &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 84*7dd12830SLokesh Vutla 85*7dd12830SLokesh Vutla col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 86*7dd12830SLokesh Vutla &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 87*7dd12830SLokesh Vutla &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 88*7dd12830SLokesh Vutla &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 89*7dd12830SLokesh Vutla 90*7dd12830SLokesh Vutla linux,keymap = <0x00000201 /* P1 */ 91*7dd12830SLokesh Vutla 0x01000204 /* P4 */ 92*7dd12830SLokesh Vutla 0x02000207 /* P7 */ 93*7dd12830SLokesh Vutla 0x0300020a /* NUMERIC_STAR */ 94*7dd12830SLokesh Vutla 0x00010202 /* P2 */ 95*7dd12830SLokesh Vutla 0x01010205 /* P5 */ 96*7dd12830SLokesh Vutla 0x02010208 /* P8 */ 97*7dd12830SLokesh Vutla 0x03010200 /* P0 */ 98*7dd12830SLokesh Vutla 0x00020203 /* P3 */ 99*7dd12830SLokesh Vutla 0x01020206 /* P6 */ 100*7dd12830SLokesh Vutla 0x02020209 /* P9 */ 101*7dd12830SLokesh Vutla 0x0302020b /* NUMERIC_POUND */ 102*7dd12830SLokesh Vutla 0x00030067 /* UP */ 103*7dd12830SLokesh Vutla 0x0103006a /* RIGHT */ 104*7dd12830SLokesh Vutla 0x0203006c /* DOWN */ 105*7dd12830SLokesh Vutla 0x03030069>; /* LEFT */ 106*7dd12830SLokesh Vutla }; 107*7dd12830SLokesh Vutla 108*7dd12830SLokesh Vutla backlight { 109*7dd12830SLokesh Vutla compatible = "pwm-backlight"; 110*7dd12830SLokesh Vutla pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 111*7dd12830SLokesh Vutla brightness-levels = <0 51 53 56 62 75 101 152 255>; 112*7dd12830SLokesh Vutla default-brightness-level = <8>; 113*7dd12830SLokesh Vutla }; 114*7dd12830SLokesh Vutla 115*7dd12830SLokesh Vutla sound0: sound@0 { 116*7dd12830SLokesh Vutla compatible = "simple-audio-card"; 117*7dd12830SLokesh Vutla simple-audio-card,name = "AM43-EPOS-EVM"; 118*7dd12830SLokesh Vutla simple-audio-card,widgets = 119*7dd12830SLokesh Vutla "Microphone", "Microphone Jack", 120*7dd12830SLokesh Vutla "Headphone", "Headphone Jack", 121*7dd12830SLokesh Vutla "Speaker", "Speaker"; 122*7dd12830SLokesh Vutla simple-audio-card,routing = 123*7dd12830SLokesh Vutla "MIC1LP", "Microphone Jack", 124*7dd12830SLokesh Vutla "MIC1RP", "Microphone Jack", 125*7dd12830SLokesh Vutla "MIC1LP", "MICBIAS", 126*7dd12830SLokesh Vutla "MIC1RP", "MICBIAS", 127*7dd12830SLokesh Vutla "Headphone Jack", "HPL", 128*7dd12830SLokesh Vutla "Headphone Jack", "HPR", 129*7dd12830SLokesh Vutla "Speaker", "SPL", 130*7dd12830SLokesh Vutla "Speaker", "SPR"; 131*7dd12830SLokesh Vutla simple-audio-card,format = "dsp_b"; 132*7dd12830SLokesh Vutla simple-audio-card,bitclock-master = <&sound0_master>; 133*7dd12830SLokesh Vutla simple-audio-card,frame-master = <&sound0_master>; 134*7dd12830SLokesh Vutla simple-audio-card,bitclock-inversion; 135*7dd12830SLokesh Vutla 136*7dd12830SLokesh Vutla simple-audio-card,cpu { 137*7dd12830SLokesh Vutla sound-dai = <&mcasp1>; 138*7dd12830SLokesh Vutla system-clock-frequency = <12000000>; 139*7dd12830SLokesh Vutla }; 140*7dd12830SLokesh Vutla 141*7dd12830SLokesh Vutla sound0_master: simple-audio-card,codec { 142*7dd12830SLokesh Vutla sound-dai = <&tlv320aic3111>; 143*7dd12830SLokesh Vutla system-clock-frequency = <12000000>; 144*7dd12830SLokesh Vutla }; 145*7dd12830SLokesh Vutla }; 146*7dd12830SLokesh Vutla}; 147*7dd12830SLokesh Vutla 148*7dd12830SLokesh Vutla&am43xx_pinmux { 149*7dd12830SLokesh Vutla cpsw_default: cpsw_default { 150*7dd12830SLokesh Vutla pinctrl-single,pins = < 151*7dd12830SLokesh Vutla /* Slave 1 */ 152*7dd12830SLokesh Vutla AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 153*7dd12830SLokesh Vutla AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 154*7dd12830SLokesh Vutla AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 155*7dd12830SLokesh Vutla AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 156*7dd12830SLokesh Vutla AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 157*7dd12830SLokesh Vutla AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 158*7dd12830SLokesh Vutla AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 159*7dd12830SLokesh Vutla AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 160*7dd12830SLokesh Vutla AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 161*7dd12830SLokesh Vutla >; 162*7dd12830SLokesh Vutla }; 163*7dd12830SLokesh Vutla 164*7dd12830SLokesh Vutla cpsw_sleep: cpsw_sleep { 165*7dd12830SLokesh Vutla pinctrl-single,pins = < 166*7dd12830SLokesh Vutla /* Slave 1 reset value */ 167*7dd12830SLokesh Vutla AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 168*7dd12830SLokesh Vutla AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 169*7dd12830SLokesh Vutla AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 170*7dd12830SLokesh Vutla AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 171*7dd12830SLokesh Vutla AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 172*7dd12830SLokesh Vutla AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 173*7dd12830SLokesh Vutla AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 174*7dd12830SLokesh Vutla AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 175*7dd12830SLokesh Vutla AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 176*7dd12830SLokesh Vutla >; 177*7dd12830SLokesh Vutla }; 178*7dd12830SLokesh Vutla 179*7dd12830SLokesh Vutla davinci_mdio_default: davinci_mdio_default { 180*7dd12830SLokesh Vutla pinctrl-single,pins = < 181*7dd12830SLokesh Vutla /* MDIO */ 182*7dd12830SLokesh Vutla AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 183*7dd12830SLokesh Vutla AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 184*7dd12830SLokesh Vutla >; 185*7dd12830SLokesh Vutla }; 186*7dd12830SLokesh Vutla 187*7dd12830SLokesh Vutla davinci_mdio_sleep: davinci_mdio_sleep { 188*7dd12830SLokesh Vutla pinctrl-single,pins = < 189*7dd12830SLokesh Vutla /* MDIO reset value */ 190*7dd12830SLokesh Vutla AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 191*7dd12830SLokesh Vutla AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 192*7dd12830SLokesh Vutla >; 193*7dd12830SLokesh Vutla }; 194*7dd12830SLokesh Vutla 195*7dd12830SLokesh Vutla i2c0_pins: pinmux_i2c0_pins { 196*7dd12830SLokesh Vutla pinctrl-single,pins = < 197*7dd12830SLokesh Vutla AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 198*7dd12830SLokesh Vutla AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 199*7dd12830SLokesh Vutla >; 200*7dd12830SLokesh Vutla }; 201*7dd12830SLokesh Vutla 202*7dd12830SLokesh Vutla nand_flash_x8: nand_flash_x8 { 203*7dd12830SLokesh Vutla pinctrl-single,pins = < 204*7dd12830SLokesh Vutla AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 205*7dd12830SLokesh Vutla AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 206*7dd12830SLokesh Vutla AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 207*7dd12830SLokesh Vutla AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 208*7dd12830SLokesh Vutla AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 209*7dd12830SLokesh Vutla AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 210*7dd12830SLokesh Vutla AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 211*7dd12830SLokesh Vutla AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 212*7dd12830SLokesh Vutla AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 213*7dd12830SLokesh Vutla AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 214*7dd12830SLokesh Vutla AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 215*7dd12830SLokesh Vutla AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 216*7dd12830SLokesh Vutla AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 217*7dd12830SLokesh Vutla AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 218*7dd12830SLokesh Vutla AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 219*7dd12830SLokesh Vutla AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 220*7dd12830SLokesh Vutla >; 221*7dd12830SLokesh Vutla }; 222*7dd12830SLokesh Vutla 223*7dd12830SLokesh Vutla ecap0_pins: backlight_pins { 224*7dd12830SLokesh Vutla pinctrl-single,pins = < 225*7dd12830SLokesh Vutla AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 226*7dd12830SLokesh Vutla >; 227*7dd12830SLokesh Vutla }; 228*7dd12830SLokesh Vutla 229*7dd12830SLokesh Vutla i2c2_pins: pinmux_i2c2_pins { 230*7dd12830SLokesh Vutla pinctrl-single,pins = < 231*7dd12830SLokesh Vutla AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 232*7dd12830SLokesh Vutla AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 233*7dd12830SLokesh Vutla >; 234*7dd12830SLokesh Vutla }; 235*7dd12830SLokesh Vutla 236*7dd12830SLokesh Vutla spi0_pins: pinmux_spi0_pins { 237*7dd12830SLokesh Vutla pinctrl-single,pins = < 238*7dd12830SLokesh Vutla AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 239*7dd12830SLokesh Vutla AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 240*7dd12830SLokesh Vutla AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 241*7dd12830SLokesh Vutla AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 242*7dd12830SLokesh Vutla >; 243*7dd12830SLokesh Vutla }; 244*7dd12830SLokesh Vutla 245*7dd12830SLokesh Vutla spi1_pins: pinmux_spi1_pins { 246*7dd12830SLokesh Vutla pinctrl-single,pins = < 247*7dd12830SLokesh Vutla AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 248*7dd12830SLokesh Vutla AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 249*7dd12830SLokesh Vutla AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 250*7dd12830SLokesh Vutla AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 251*7dd12830SLokesh Vutla >; 252*7dd12830SLokesh Vutla }; 253*7dd12830SLokesh Vutla 254*7dd12830SLokesh Vutla mmc1_pins: pinmux_mmc1_pins { 255*7dd12830SLokesh Vutla pinctrl-single,pins = < 256*7dd12830SLokesh Vutla AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 257*7dd12830SLokesh Vutla >; 258*7dd12830SLokesh Vutla }; 259*7dd12830SLokesh Vutla 260*7dd12830SLokesh Vutla qspi1_default: qspi1_default { 261*7dd12830SLokesh Vutla pinctrl-single,pins = < 262*7dd12830SLokesh Vutla AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) 263*7dd12830SLokesh Vutla AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) 264*7dd12830SLokesh Vutla AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) 265*7dd12830SLokesh Vutla AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) 266*7dd12830SLokesh Vutla AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) 267*7dd12830SLokesh Vutla AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) 268*7dd12830SLokesh Vutla >; 269*7dd12830SLokesh Vutla }; 270*7dd12830SLokesh Vutla 271*7dd12830SLokesh Vutla pixcir_ts_pins: pixcir_ts_pins { 272*7dd12830SLokesh Vutla pinctrl-single,pins = < 273*7dd12830SLokesh Vutla AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 274*7dd12830SLokesh Vutla >; 275*7dd12830SLokesh Vutla }; 276*7dd12830SLokesh Vutla 277*7dd12830SLokesh Vutla hdq_pins: pinmux_hdq_pins { 278*7dd12830SLokesh Vutla pinctrl-single,pins = < 279*7dd12830SLokesh Vutla AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 280*7dd12830SLokesh Vutla >; 281*7dd12830SLokesh Vutla }; 282*7dd12830SLokesh Vutla 283*7dd12830SLokesh Vutla dss_pins: dss_pins { 284*7dd12830SLokesh Vutla pinctrl-single,pins = < 285*7dd12830SLokesh Vutla AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 286*7dd12830SLokesh Vutla AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) 287*7dd12830SLokesh Vutla AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) 288*7dd12830SLokesh Vutla AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) 289*7dd12830SLokesh Vutla AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) 290*7dd12830SLokesh Vutla AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) 291*7dd12830SLokesh Vutla AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) 292*7dd12830SLokesh Vutla AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 293*7dd12830SLokesh Vutla AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 294*7dd12830SLokesh Vutla AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) 295*7dd12830SLokesh Vutla AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) 296*7dd12830SLokesh Vutla AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) 297*7dd12830SLokesh Vutla AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) 298*7dd12830SLokesh Vutla AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) 299*7dd12830SLokesh Vutla AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) 300*7dd12830SLokesh Vutla AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) 301*7dd12830SLokesh Vutla AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) 302*7dd12830SLokesh Vutla AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) 303*7dd12830SLokesh Vutla AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) 304*7dd12830SLokesh Vutla AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) 305*7dd12830SLokesh Vutla AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) 306*7dd12830SLokesh Vutla AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) 307*7dd12830SLokesh Vutla AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) 308*7dd12830SLokesh Vutla AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 309*7dd12830SLokesh Vutla AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 310*7dd12830SLokesh Vutla AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 311*7dd12830SLokesh Vutla AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 312*7dd12830SLokesh Vutla AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 313*7dd12830SLokesh Vutla >; 314*7dd12830SLokesh Vutla }; 315*7dd12830SLokesh Vutla 316*7dd12830SLokesh Vutla display_mux_pins: display_mux_pins { 317*7dd12830SLokesh Vutla pinctrl-single,pins = < 318*7dd12830SLokesh Vutla /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 319*7dd12830SLokesh Vutla AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) 320*7dd12830SLokesh Vutla >; 321*7dd12830SLokesh Vutla }; 322*7dd12830SLokesh Vutla 323*7dd12830SLokesh Vutla vpfe1_pins_default: vpfe1_pins_default { 324*7dd12830SLokesh Vutla pinctrl-single,pins = < 325*7dd12830SLokesh Vutla AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 326*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 327*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 328*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 329*7dd12830SLokesh Vutla AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 330*7dd12830SLokesh Vutla AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 331*7dd12830SLokesh Vutla AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 332*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 333*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 334*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 335*7dd12830SLokesh Vutla AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 336*7dd12830SLokesh Vutla AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 337*7dd12830SLokesh Vutla AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 338*7dd12830SLokesh Vutla >; 339*7dd12830SLokesh Vutla }; 340*7dd12830SLokesh Vutla 341*7dd12830SLokesh Vutla vpfe1_pins_sleep: vpfe1_pins_sleep { 342*7dd12830SLokesh Vutla pinctrl-single,pins = < 343*7dd12830SLokesh Vutla AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 344*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 345*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 346*7dd12830SLokesh Vutla AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 347*7dd12830SLokesh Vutla AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 348*7dd12830SLokesh Vutla AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 349*7dd12830SLokesh Vutla AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 350*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 351*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 352*7dd12830SLokesh Vutla AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 353*7dd12830SLokesh Vutla AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 354*7dd12830SLokesh Vutla AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 355*7dd12830SLokesh Vutla AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 356*7dd12830SLokesh Vutla >; 357*7dd12830SLokesh Vutla }; 358*7dd12830SLokesh Vutla 359*7dd12830SLokesh Vutla mcasp1_pins: mcasp1_pins { 360*7dd12830SLokesh Vutla pinctrl-single,pins = < 361*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ 362*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ 363*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ 364*7dd12830SLokesh Vutla AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ 365*7dd12830SLokesh Vutla >; 366*7dd12830SLokesh Vutla }; 367*7dd12830SLokesh Vutla 368*7dd12830SLokesh Vutla mcasp1_sleep_pins: mcasp1_sleep_pins { 369*7dd12830SLokesh Vutla pinctrl-single,pins = < 370*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) 371*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) 372*7dd12830SLokesh Vutla AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) 373*7dd12830SLokesh Vutla AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) 374*7dd12830SLokesh Vutla >; 375*7dd12830SLokesh Vutla }; 376*7dd12830SLokesh Vutla}; 377*7dd12830SLokesh Vutla 378*7dd12830SLokesh Vutla&mmc1 { 379*7dd12830SLokesh Vutla status = "okay"; 380*7dd12830SLokesh Vutla vmmc-supply = <&vmmcsd_fixed>; 381*7dd12830SLokesh Vutla bus-width = <4>; 382*7dd12830SLokesh Vutla pinctrl-names = "default"; 383*7dd12830SLokesh Vutla pinctrl-0 = <&mmc1_pins>; 384*7dd12830SLokesh Vutla cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 385*7dd12830SLokesh Vutla}; 386*7dd12830SLokesh Vutla 387*7dd12830SLokesh Vutla&mac { 388*7dd12830SLokesh Vutla pinctrl-names = "default", "sleep"; 389*7dd12830SLokesh Vutla pinctrl-0 = <&cpsw_default>; 390*7dd12830SLokesh Vutla pinctrl-1 = <&cpsw_sleep>; 391*7dd12830SLokesh Vutla status = "okay"; 392*7dd12830SLokesh Vutla}; 393*7dd12830SLokesh Vutla 394*7dd12830SLokesh Vutla&davinci_mdio { 395*7dd12830SLokesh Vutla pinctrl-names = "default", "sleep"; 396*7dd12830SLokesh Vutla pinctrl-0 = <&davinci_mdio_default>; 397*7dd12830SLokesh Vutla pinctrl-1 = <&davinci_mdio_sleep>; 398*7dd12830SLokesh Vutla status = "okay"; 399*7dd12830SLokesh Vutla}; 400*7dd12830SLokesh Vutla 401*7dd12830SLokesh Vutla&cpsw_emac0 { 402*7dd12830SLokesh Vutla phy_id = <&davinci_mdio>, <16>; 403*7dd12830SLokesh Vutla phy-mode = "rmii"; 404*7dd12830SLokesh Vutla}; 405*7dd12830SLokesh Vutla 406*7dd12830SLokesh Vutla&cpsw_emac1 { 407*7dd12830SLokesh Vutla phy_id = <&davinci_mdio>, <1>; 408*7dd12830SLokesh Vutla phy-mode = "rmii"; 409*7dd12830SLokesh Vutla}; 410*7dd12830SLokesh Vutla 411*7dd12830SLokesh Vutla&phy_sel { 412*7dd12830SLokesh Vutla rmii-clock-ext; 413*7dd12830SLokesh Vutla}; 414*7dd12830SLokesh Vutla 415*7dd12830SLokesh Vutla&i2c0 { 416*7dd12830SLokesh Vutla status = "okay"; 417*7dd12830SLokesh Vutla pinctrl-names = "default"; 418*7dd12830SLokesh Vutla pinctrl-0 = <&i2c0_pins>; 419*7dd12830SLokesh Vutla clock-frequency = <400000>; 420*7dd12830SLokesh Vutla 421*7dd12830SLokesh Vutla tps65218: tps65218@24 { 422*7dd12830SLokesh Vutla reg = <0x24>; 423*7dd12830SLokesh Vutla compatible = "ti,tps65218"; 424*7dd12830SLokesh Vutla interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 425*7dd12830SLokesh Vutla interrupt-controller; 426*7dd12830SLokesh Vutla #interrupt-cells = <2>; 427*7dd12830SLokesh Vutla 428*7dd12830SLokesh Vutla dcdc1: regulator-dcdc1 { 429*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc1"; 430*7dd12830SLokesh Vutla regulator-name = "vdd_core"; 431*7dd12830SLokesh Vutla regulator-min-microvolt = <912000>; 432*7dd12830SLokesh Vutla regulator-max-microvolt = <1144000>; 433*7dd12830SLokesh Vutla regulator-boot-on; 434*7dd12830SLokesh Vutla regulator-always-on; 435*7dd12830SLokesh Vutla }; 436*7dd12830SLokesh Vutla 437*7dd12830SLokesh Vutla dcdc2: regulator-dcdc2 { 438*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc2"; 439*7dd12830SLokesh Vutla regulator-name = "vdd_mpu"; 440*7dd12830SLokesh Vutla regulator-min-microvolt = <912000>; 441*7dd12830SLokesh Vutla regulator-max-microvolt = <1378000>; 442*7dd12830SLokesh Vutla regulator-boot-on; 443*7dd12830SLokesh Vutla regulator-always-on; 444*7dd12830SLokesh Vutla }; 445*7dd12830SLokesh Vutla 446*7dd12830SLokesh Vutla dcdc3: regulator-dcdc3 { 447*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc3"; 448*7dd12830SLokesh Vutla regulator-name = "vdcdc3"; 449*7dd12830SLokesh Vutla regulator-min-microvolt = <1500000>; 450*7dd12830SLokesh Vutla regulator-max-microvolt = <1500000>; 451*7dd12830SLokesh Vutla regulator-boot-on; 452*7dd12830SLokesh Vutla regulator-always-on; 453*7dd12830SLokesh Vutla }; 454*7dd12830SLokesh Vutla 455*7dd12830SLokesh Vutla dcdc4: regulator-dcdc4 { 456*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc4"; 457*7dd12830SLokesh Vutla regulator-name = "vdcdc4"; 458*7dd12830SLokesh Vutla regulator-min-microvolt = <3300000>; 459*7dd12830SLokesh Vutla regulator-max-microvolt = <3300000>; 460*7dd12830SLokesh Vutla regulator-boot-on; 461*7dd12830SLokesh Vutla regulator-always-on; 462*7dd12830SLokesh Vutla }; 463*7dd12830SLokesh Vutla 464*7dd12830SLokesh Vutla dcdc5: regulator-dcdc5 { 465*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc5"; 466*7dd12830SLokesh Vutla regulator-name = "v1_0bat"; 467*7dd12830SLokesh Vutla regulator-min-microvolt = <1000000>; 468*7dd12830SLokesh Vutla regulator-max-microvolt = <1000000>; 469*7dd12830SLokesh Vutla }; 470*7dd12830SLokesh Vutla 471*7dd12830SLokesh Vutla dcdc6: regulator-dcdc6 { 472*7dd12830SLokesh Vutla compatible = "ti,tps65218-dcdc6"; 473*7dd12830SLokesh Vutla regulator-name = "v1_8bat"; 474*7dd12830SLokesh Vutla regulator-min-microvolt = <1800000>; 475*7dd12830SLokesh Vutla regulator-max-microvolt = <1800000>; 476*7dd12830SLokesh Vutla }; 477*7dd12830SLokesh Vutla 478*7dd12830SLokesh Vutla ldo1: regulator-ldo1 { 479*7dd12830SLokesh Vutla compatible = "ti,tps65218-ldo1"; 480*7dd12830SLokesh Vutla regulator-min-microvolt = <1800000>; 481*7dd12830SLokesh Vutla regulator-max-microvolt = <1800000>; 482*7dd12830SLokesh Vutla regulator-boot-on; 483*7dd12830SLokesh Vutla regulator-always-on; 484*7dd12830SLokesh Vutla }; 485*7dd12830SLokesh Vutla }; 486*7dd12830SLokesh Vutla 487*7dd12830SLokesh Vutla at24@50 { 488*7dd12830SLokesh Vutla compatible = "at24,24c256"; 489*7dd12830SLokesh Vutla pagesize = <64>; 490*7dd12830SLokesh Vutla reg = <0x50>; 491*7dd12830SLokesh Vutla }; 492*7dd12830SLokesh Vutla 493*7dd12830SLokesh Vutla pixcir_ts@5c { 494*7dd12830SLokesh Vutla compatible = "pixcir,pixcir_tangoc"; 495*7dd12830SLokesh Vutla pinctrl-names = "default"; 496*7dd12830SLokesh Vutla pinctrl-0 = <&pixcir_ts_pins>; 497*7dd12830SLokesh Vutla reg = <0x5c>; 498*7dd12830SLokesh Vutla interrupt-parent = <&gpio1>; 499*7dd12830SLokesh Vutla interrupts = <17 IRQ_TYPE_EDGE_FALLING>; 500*7dd12830SLokesh Vutla 501*7dd12830SLokesh Vutla attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 502*7dd12830SLokesh Vutla 503*7dd12830SLokesh Vutla touchscreen-size-x = <1024>; 504*7dd12830SLokesh Vutla touchscreen-size-y = <600>; 505*7dd12830SLokesh Vutla }; 506*7dd12830SLokesh Vutla 507*7dd12830SLokesh Vutla tlv320aic3111: tlv320aic3111@18 { 508*7dd12830SLokesh Vutla #sound-dai-cells = <0>; 509*7dd12830SLokesh Vutla compatible = "ti,tlv320aic3111"; 510*7dd12830SLokesh Vutla reg = <0x18>; 511*7dd12830SLokesh Vutla status = "okay"; 512*7dd12830SLokesh Vutla 513*7dd12830SLokesh Vutla ai31xx-micbias-vg = <MICBIAS_2_0V>; 514*7dd12830SLokesh Vutla 515*7dd12830SLokesh Vutla /* Regulators */ 516*7dd12830SLokesh Vutla HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 517*7dd12830SLokesh Vutla SPRVDD-supply = <&vbat>; /* vbat */ 518*7dd12830SLokesh Vutla SPLVDD-supply = <&vbat>; /* vbat */ 519*7dd12830SLokesh Vutla AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 520*7dd12830SLokesh Vutla IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ 521*7dd12830SLokesh Vutla DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ 522*7dd12830SLokesh Vutla }; 523*7dd12830SLokesh Vutla}; 524*7dd12830SLokesh Vutla 525*7dd12830SLokesh Vutla&i2c2 { 526*7dd12830SLokesh Vutla pinctrl-names = "default"; 527*7dd12830SLokesh Vutla pinctrl-0 = <&i2c2_pins>; 528*7dd12830SLokesh Vutla status = "okay"; 529*7dd12830SLokesh Vutla}; 530*7dd12830SLokesh Vutla 531*7dd12830SLokesh Vutla&gpio0 { 532*7dd12830SLokesh Vutla status = "okay"; 533*7dd12830SLokesh Vutla}; 534*7dd12830SLokesh Vutla 535*7dd12830SLokesh Vutla&gpio1 { 536*7dd12830SLokesh Vutla status = "okay"; 537*7dd12830SLokesh Vutla}; 538*7dd12830SLokesh Vutla 539*7dd12830SLokesh Vutla&gpio2 { 540*7dd12830SLokesh Vutla pinctrl-names = "default"; 541*7dd12830SLokesh Vutla pinctrl-0 = <&display_mux_pins>; 542*7dd12830SLokesh Vutla status = "okay"; 543*7dd12830SLokesh Vutla 544*7dd12830SLokesh Vutla p1 { 545*7dd12830SLokesh Vutla /* 546*7dd12830SLokesh Vutla * SelLCDorHDMI selects between display and audio paths: 547*7dd12830SLokesh Vutla * Low: HDMI display with audio via HDMI 548*7dd12830SLokesh Vutla * High: LCD display with analog audio via aic3111 codec 549*7dd12830SLokesh Vutla */ 550*7dd12830SLokesh Vutla gpio-hog; 551*7dd12830SLokesh Vutla gpios = <1 GPIO_ACTIVE_HIGH>; 552*7dd12830SLokesh Vutla output-high; 553*7dd12830SLokesh Vutla line-name = "SelLCDorHDMI"; 554*7dd12830SLokesh Vutla }; 555*7dd12830SLokesh Vutla}; 556*7dd12830SLokesh Vutla 557*7dd12830SLokesh Vutla&gpio3 { 558*7dd12830SLokesh Vutla status = "okay"; 559*7dd12830SLokesh Vutla}; 560*7dd12830SLokesh Vutla 561*7dd12830SLokesh Vutla&elm { 562*7dd12830SLokesh Vutla status = "okay"; 563*7dd12830SLokesh Vutla}; 564*7dd12830SLokesh Vutla 565*7dd12830SLokesh Vutla&gpmc { 566*7dd12830SLokesh Vutla status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 567*7dd12830SLokesh Vutla pinctrl-names = "default"; 568*7dd12830SLokesh Vutla pinctrl-0 = <&nand_flash_x8>; 569*7dd12830SLokesh Vutla ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 570*7dd12830SLokesh Vutla nand@0,0 { 571*7dd12830SLokesh Vutla compatible = "ti,omap2-nand"; 572*7dd12830SLokesh Vutla reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 573*7dd12830SLokesh Vutla interrupt-parent = <&gpmc>; 574*7dd12830SLokesh Vutla interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 575*7dd12830SLokesh Vutla <1 IRQ_TYPE_NONE>; /* termcount */ 576*7dd12830SLokesh Vutla ti,nand-ecc-opt = "bch16"; 577*7dd12830SLokesh Vutla ti,elm-id = <&elm>; 578*7dd12830SLokesh Vutla nand-bus-width = <8>; 579*7dd12830SLokesh Vutla gpmc,device-width = <1>; 580*7dd12830SLokesh Vutla gpmc,sync-clk-ps = <0>; 581*7dd12830SLokesh Vutla gpmc,cs-on-ns = <0>; 582*7dd12830SLokesh Vutla gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 583*7dd12830SLokesh Vutla gpmc,cs-wr-off-ns = <40>; 584*7dd12830SLokesh Vutla gpmc,adv-on-ns = <0>; /* cs-on-ns */ 585*7dd12830SLokesh Vutla gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 586*7dd12830SLokesh Vutla gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 587*7dd12830SLokesh Vutla gpmc,we-on-ns = <0>; /* cs-on-ns */ 588*7dd12830SLokesh Vutla gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 589*7dd12830SLokesh Vutla gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 590*7dd12830SLokesh Vutla gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 591*7dd12830SLokesh Vutla gpmc,access-ns = <30>; /* tCEA + 4*/ 592*7dd12830SLokesh Vutla gpmc,rd-cycle-ns = <40>; 593*7dd12830SLokesh Vutla gpmc,wr-cycle-ns = <40>; 594*7dd12830SLokesh Vutla gpmc,bus-turnaround-ns = <0>; 595*7dd12830SLokesh Vutla gpmc,cycle2cycle-delay-ns = <0>; 596*7dd12830SLokesh Vutla gpmc,clk-activation-ns = <0>; 597*7dd12830SLokesh Vutla gpmc,wr-access-ns = <40>; 598*7dd12830SLokesh Vutla gpmc,wr-data-mux-bus-ns = <0>; 599*7dd12830SLokesh Vutla /* MTD partition table */ 600*7dd12830SLokesh Vutla /* All SPL-* partitions are sized to minimal length 601*7dd12830SLokesh Vutla * which can be independently programmable. For 602*7dd12830SLokesh Vutla * NAND flash this is equal to size of erase-block */ 603*7dd12830SLokesh Vutla #address-cells = <1>; 604*7dd12830SLokesh Vutla #size-cells = <1>; 605*7dd12830SLokesh Vutla partition@0 { 606*7dd12830SLokesh Vutla label = "NAND.SPL"; 607*7dd12830SLokesh Vutla reg = <0x00000000 0x00040000>; 608*7dd12830SLokesh Vutla }; 609*7dd12830SLokesh Vutla partition@1 { 610*7dd12830SLokesh Vutla label = "NAND.SPL.backup1"; 611*7dd12830SLokesh Vutla reg = <0x00040000 0x00040000>; 612*7dd12830SLokesh Vutla }; 613*7dd12830SLokesh Vutla partition@2 { 614*7dd12830SLokesh Vutla label = "NAND.SPL.backup2"; 615*7dd12830SLokesh Vutla reg = <0x00080000 0x00040000>; 616*7dd12830SLokesh Vutla }; 617*7dd12830SLokesh Vutla partition@3 { 618*7dd12830SLokesh Vutla label = "NAND.SPL.backup3"; 619*7dd12830SLokesh Vutla reg = <0x000C0000 0x00040000>; 620*7dd12830SLokesh Vutla }; 621*7dd12830SLokesh Vutla partition@4 { 622*7dd12830SLokesh Vutla label = "NAND.u-boot-spl-os"; 623*7dd12830SLokesh Vutla reg = <0x00100000 0x00080000>; 624*7dd12830SLokesh Vutla }; 625*7dd12830SLokesh Vutla partition@5 { 626*7dd12830SLokesh Vutla label = "NAND.u-boot"; 627*7dd12830SLokesh Vutla reg = <0x00180000 0x00100000>; 628*7dd12830SLokesh Vutla }; 629*7dd12830SLokesh Vutla partition@6 { 630*7dd12830SLokesh Vutla label = "NAND.u-boot-env"; 631*7dd12830SLokesh Vutla reg = <0x00280000 0x00040000>; 632*7dd12830SLokesh Vutla }; 633*7dd12830SLokesh Vutla partition@7 { 634*7dd12830SLokesh Vutla label = "NAND.u-boot-env.backup1"; 635*7dd12830SLokesh Vutla reg = <0x002C0000 0x00040000>; 636*7dd12830SLokesh Vutla }; 637*7dd12830SLokesh Vutla partition@8 { 638*7dd12830SLokesh Vutla label = "NAND.kernel"; 639*7dd12830SLokesh Vutla reg = <0x00300000 0x00700000>; 640*7dd12830SLokesh Vutla }; 641*7dd12830SLokesh Vutla partition@9 { 642*7dd12830SLokesh Vutla label = "NAND.file-system"; 643*7dd12830SLokesh Vutla reg = <0x00a00000 0x1f600000>; 644*7dd12830SLokesh Vutla }; 645*7dd12830SLokesh Vutla }; 646*7dd12830SLokesh Vutla}; 647*7dd12830SLokesh Vutla 648*7dd12830SLokesh Vutla&epwmss0 { 649*7dd12830SLokesh Vutla status = "okay"; 650*7dd12830SLokesh Vutla}; 651*7dd12830SLokesh Vutla 652*7dd12830SLokesh Vutla&tscadc { 653*7dd12830SLokesh Vutla status = "okay"; 654*7dd12830SLokesh Vutla 655*7dd12830SLokesh Vutla adc { 656*7dd12830SLokesh Vutla ti,adc-channels = <0 1 2 3 4 5 6 7>; 657*7dd12830SLokesh Vutla }; 658*7dd12830SLokesh Vutla}; 659*7dd12830SLokesh Vutla 660*7dd12830SLokesh Vutla&ecap0 { 661*7dd12830SLokesh Vutla status = "okay"; 662*7dd12830SLokesh Vutla pinctrl-names = "default"; 663*7dd12830SLokesh Vutla pinctrl-0 = <&ecap0_pins>; 664*7dd12830SLokesh Vutla}; 665*7dd12830SLokesh Vutla 666*7dd12830SLokesh Vutla&spi0 { 667*7dd12830SLokesh Vutla pinctrl-names = "default"; 668*7dd12830SLokesh Vutla pinctrl-0 = <&spi0_pins>; 669*7dd12830SLokesh Vutla status = "okay"; 670*7dd12830SLokesh Vutla}; 671*7dd12830SLokesh Vutla 672*7dd12830SLokesh Vutla&spi1 { 673*7dd12830SLokesh Vutla pinctrl-names = "default"; 674*7dd12830SLokesh Vutla pinctrl-0 = <&spi1_pins>; 675*7dd12830SLokesh Vutla status = "okay"; 676*7dd12830SLokesh Vutla}; 677*7dd12830SLokesh Vutla 678*7dd12830SLokesh Vutla&usb2_phy1 { 679*7dd12830SLokesh Vutla status = "okay"; 680*7dd12830SLokesh Vutla}; 681*7dd12830SLokesh Vutla 682*7dd12830SLokesh Vutla&usb1 { 683*7dd12830SLokesh Vutla dr_mode = "peripheral"; 684*7dd12830SLokesh Vutla status = "okay"; 685*7dd12830SLokesh Vutla}; 686*7dd12830SLokesh Vutla 687*7dd12830SLokesh Vutla&usb2_phy2 { 688*7dd12830SLokesh Vutla status = "okay"; 689*7dd12830SLokesh Vutla}; 690*7dd12830SLokesh Vutla 691*7dd12830SLokesh Vutla&usb2 { 692*7dd12830SLokesh Vutla dr_mode = "host"; 693*7dd12830SLokesh Vutla status = "okay"; 694*7dd12830SLokesh Vutla}; 695*7dd12830SLokesh Vutla 696*7dd12830SLokesh Vutla&qspi { 697*7dd12830SLokesh Vutla status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 698*7dd12830SLokesh Vutla pinctrl-names = "default"; 699*7dd12830SLokesh Vutla pinctrl-0 = <&qspi1_default>; 700*7dd12830SLokesh Vutla 701*7dd12830SLokesh Vutla spi-max-frequency = <48000000>; 702*7dd12830SLokesh Vutla m25p80@0 { 703*7dd12830SLokesh Vutla compatible = "mx66l51235l"; 704*7dd12830SLokesh Vutla spi-max-frequency = <48000000>; 705*7dd12830SLokesh Vutla reg = <0>; 706*7dd12830SLokesh Vutla spi-cpol; 707*7dd12830SLokesh Vutla spi-cpha; 708*7dd12830SLokesh Vutla spi-tx-bus-width = <1>; 709*7dd12830SLokesh Vutla spi-rx-bus-width = <4>; 710*7dd12830SLokesh Vutla #address-cells = <1>; 711*7dd12830SLokesh Vutla #size-cells = <1>; 712*7dd12830SLokesh Vutla 713*7dd12830SLokesh Vutla /* MTD partition table. 714*7dd12830SLokesh Vutla * The ROM checks the first 512KiB 715*7dd12830SLokesh Vutla * for a valid file to boot(XIP). 716*7dd12830SLokesh Vutla */ 717*7dd12830SLokesh Vutla partition@0 { 718*7dd12830SLokesh Vutla label = "QSPI.U_BOOT"; 719*7dd12830SLokesh Vutla reg = <0x00000000 0x000080000>; 720*7dd12830SLokesh Vutla }; 721*7dd12830SLokesh Vutla partition@1 { 722*7dd12830SLokesh Vutla label = "QSPI.U_BOOT.backup"; 723*7dd12830SLokesh Vutla reg = <0x00080000 0x00080000>; 724*7dd12830SLokesh Vutla }; 725*7dd12830SLokesh Vutla partition@2 { 726*7dd12830SLokesh Vutla label = "QSPI.U-BOOT-SPL_OS"; 727*7dd12830SLokesh Vutla reg = <0x00100000 0x00010000>; 728*7dd12830SLokesh Vutla }; 729*7dd12830SLokesh Vutla partition@3 { 730*7dd12830SLokesh Vutla label = "QSPI.U_BOOT_ENV"; 731*7dd12830SLokesh Vutla reg = <0x00110000 0x00010000>; 732*7dd12830SLokesh Vutla }; 733*7dd12830SLokesh Vutla partition@4 { 734*7dd12830SLokesh Vutla label = "QSPI.U-BOOT-ENV.backup"; 735*7dd12830SLokesh Vutla reg = <0x00120000 0x00010000>; 736*7dd12830SLokesh Vutla }; 737*7dd12830SLokesh Vutla partition@5 { 738*7dd12830SLokesh Vutla label = "QSPI.KERNEL"; 739*7dd12830SLokesh Vutla reg = <0x00130000 0x0800000>; 740*7dd12830SLokesh Vutla }; 741*7dd12830SLokesh Vutla partition@6 { 742*7dd12830SLokesh Vutla label = "QSPI.FILESYSTEM"; 743*7dd12830SLokesh Vutla reg = <0x00930000 0x36D0000>; 744*7dd12830SLokesh Vutla }; 745*7dd12830SLokesh Vutla }; 746*7dd12830SLokesh Vutla}; 747*7dd12830SLokesh Vutla 748*7dd12830SLokesh Vutla&hdq { 749*7dd12830SLokesh Vutla status = "okay"; 750*7dd12830SLokesh Vutla pinctrl-names = "default"; 751*7dd12830SLokesh Vutla pinctrl-0 = <&hdq_pins>; 752*7dd12830SLokesh Vutla}; 753*7dd12830SLokesh Vutla 754*7dd12830SLokesh Vutla&dss { 755*7dd12830SLokesh Vutla status = "ok"; 756*7dd12830SLokesh Vutla 757*7dd12830SLokesh Vutla pinctrl-names = "default"; 758*7dd12830SLokesh Vutla pinctrl-0 = <&dss_pins>; 759*7dd12830SLokesh Vutla 760*7dd12830SLokesh Vutla port { 761*7dd12830SLokesh Vutla dpi_out: endpoint@0 { 762*7dd12830SLokesh Vutla remote-endpoint = <&lcd_in>; 763*7dd12830SLokesh Vutla data-lines = <24>; 764*7dd12830SLokesh Vutla }; 765*7dd12830SLokesh Vutla }; 766*7dd12830SLokesh Vutla}; 767*7dd12830SLokesh Vutla 768*7dd12830SLokesh Vutla&vpfe1 { 769*7dd12830SLokesh Vutla status = "okay"; 770*7dd12830SLokesh Vutla pinctrl-names = "default", "sleep"; 771*7dd12830SLokesh Vutla pinctrl-0 = <&vpfe1_pins_default>; 772*7dd12830SLokesh Vutla pinctrl-1 = <&vpfe1_pins_sleep>; 773*7dd12830SLokesh Vutla 774*7dd12830SLokesh Vutla port { 775*7dd12830SLokesh Vutla vpfe1_ep: endpoint { 776*7dd12830SLokesh Vutla /* remote-endpoint = <&sensor>; add once we have it */ 777*7dd12830SLokesh Vutla ti,am437x-vpfe-interface = <0>; 778*7dd12830SLokesh Vutla bus-width = <8>; 779*7dd12830SLokesh Vutla hsync-active = <0>; 780*7dd12830SLokesh Vutla vsync-active = <0>; 781*7dd12830SLokesh Vutla }; 782*7dd12830SLokesh Vutla }; 783*7dd12830SLokesh Vutla}; 784*7dd12830SLokesh Vutla 785*7dd12830SLokesh Vutla&mcasp1 { 786*7dd12830SLokesh Vutla #sound-dai-cells = <0>; 787*7dd12830SLokesh Vutla pinctrl-names = "default", "sleep"; 788*7dd12830SLokesh Vutla pinctrl-0 = <&mcasp1_pins>; 789*7dd12830SLokesh Vutla pinctrl-1 = <&mcasp1_sleep_pins>; 790*7dd12830SLokesh Vutla 791*7dd12830SLokesh Vutla status = "okay"; 792*7dd12830SLokesh Vutla 793*7dd12830SLokesh Vutla op-mode = <0>; /* MCASP_IIS_MODE */ 794*7dd12830SLokesh Vutla tdm-slots = <2>; 795*7dd12830SLokesh Vutla /* 4 serializer */ 796*7dd12830SLokesh Vutla serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 797*7dd12830SLokesh Vutla 1 2 0 0 798*7dd12830SLokesh Vutla >; 799*7dd12830SLokesh Vutla tx-num-evt = <32>; 800*7dd12830SLokesh Vutla rx-num-evt = <32>; 801*7dd12830SLokesh Vutla}; 802*7dd12830SLokesh Vutla 803*7dd12830SLokesh Vutla&synctimer_32kclk { 804*7dd12830SLokesh Vutla assigned-clocks = <&mux_synctimer32k_ck>; 805*7dd12830SLokesh Vutla assigned-clock-parents = <&clkdiv32k_ick>; 806*7dd12830SLokesh Vutla}; 807