1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Z�pke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77 .word CONFIG_SYS_TEXT_BASE 78 79/* 80 * These are defined in the board-specific linker script. 81 */ 82.globl _bss_start 83_bss_start: 84 .word __bss_start 85 86.globl _bss_end 87_bss_end: 88 .word _end 89 90#ifdef CONFIG_USE_IRQ 91/* IRQ stack memory (calculated at run-time) */ 92.globl IRQ_STACK_START 93IRQ_STACK_START: 94 .word 0x0badc0de 95 96/* IRQ stack memory (calculated at run-time) */ 97.globl FIQ_STACK_START 98FIQ_STACK_START: 99 .word 0x0badc0de 100#endif 101 102/* IRQ stack memory (calculated at run-time) + 8 bytes */ 103.globl IRQ_STACK_START_IN 104IRQ_STACK_START_IN: 105 .word 0x0badc0de 106 107.globl _datarel_start 108_datarel_start: 109 .word __datarel_start 110 111.globl _datarelrolocal_start 112_datarelrolocal_start: 113 .word __datarelrolocal_start 114 115.globl _datarellocal_start 116_datarellocal_start: 117 .word __datarellocal_start 118 119.globl _datarelro_start 120_datarelro_start: 121 .word __datarelro_start 122 123.globl _got_start 124_got_start: 125 .word __got_start 126 127.globl _got_end 128_got_end: 129 .word __got_end 130 131/* 132 * the actual reset code 133 */ 134 135reset: 136 /* 137 * set the cpu to SVC32 mode 138 */ 139 mrs r0,cpsr 140 bic r0,r0,#0x1f 141 orr r0,r0,#0xd3 142 msr cpsr,r0 143 144 /* 145 * we do sys-critical inits only at reboot, 146 * not when booting from ram! 147 */ 148#ifndef CONFIG_SKIP_LOWLEVEL_INIT 149 bl cpu_init_crit 150#endif 151 152/* Set stackpointer in internal RAM to call board_init_f */ 153call_board_init_f: 154 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 155 ldr r0,=0x00000000 156 bl board_init_f 157 158/*------------------------------------------------------------------------------*/ 159 160/* 161 * void relocate_code (addr_sp, gd, addr_moni) 162 * 163 * This "function" does not return, instead it continues in RAM 164 * after relocating the monitor code. 165 * 166 */ 167 .globl relocate_code 168relocate_code: 169 mov r4, r0 /* save addr_sp */ 170 mov r5, r1 /* save addr of gd */ 171 mov r6, r2 /* save addr of destination */ 172 mov r7, r2 /* save addr of destination */ 173 174 /* Set up the stack */ 175stack_setup: 176 mov sp, r4 177 178 adr r0, _start 179 ldr r2, _TEXT_BASE 180 ldr r3, _bss_start 181 sub r2, r3, r2 /* r2 <- size of armboot */ 182 add r2, r0, r2 /* r2 <- source end address */ 183 cmp r0, r6 184 beq clear_bss 185 186copy_loop: 187 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 188 stmia r6!, {r9-r10} /* copy to target address [r1] */ 189 cmp r0, r2 /* until source end address [r2] */ 190 blo copy_loop 191 192#ifndef CONFIG_PRELOADER 193 /* fix got entries */ 194 ldr r1, _TEXT_BASE /* Text base */ 195 mov r0, r7 /* reloc addr */ 196 ldr r2, _got_start /* addr in Flash */ 197 ldr r3, _got_end /* addr in Flash */ 198 sub r3, r3, r1 199 add r3, r3, r0 200 sub r2, r2, r1 201 add r2, r2, r0 202 203fixloop: 204 ldr r4, [r2] 205 sub r4, r4, r1 206 add r4, r4, r0 207 str r4, [r2] 208 add r2, r2, #4 209 cmp r2, r3 210 blo fixloop 211#endif 212 213clear_bss: 214#ifndef CONFIG_PRELOADER 215 ldr r0, _bss_start 216 ldr r1, _bss_end 217 ldr r3, _TEXT_BASE /* Text base */ 218 mov r4, r7 /* reloc addr */ 219 sub r0, r0, r3 220 add r0, r0, r4 221 sub r1, r1, r3 222 add r1, r1, r4 223 mov r2, #0x00000000 /* clear */ 224 225clbss_l:str r2, [r0] /* clear loop... */ 226 add r0, r0, #4 227 cmp r0, r1 228 bne clbss_l 229#endif 230 231/* 232 * We are done. Do not return, instead branch to second part of board 233 * initialization, now running from RAM. 234 */ 235 ldr r0, _TEXT_BASE 236 ldr r2, _board_init_r 237 sub r2, r2, r0 238 add r2, r2, r7 /* position from board_init_r in RAM */ 239 /* setup parameters for board_init_r */ 240 mov r0, r5 /* gd_t */ 241 mov r1, r7 /* dest_addr */ 242 /* jump to it ... */ 243 mov lr, r2 244 mov pc, lr 245 246_board_init_r: .word board_init_r 247 248/* 249 ************************************************************************* 250 * 251 * CPU_init_critical registers 252 * 253 * setup important registers 254 * setup memory timing 255 * 256 ************************************************************************* 257 */ 258 259 260/* Interupt-Controller base address */ 261IC_BASE: .word 0x90050000 262#define ICMR 0x04 263 264 265/* Reset-Controller */ 266RST_BASE: .word 0x90030000 267#define RSRR 0x00 268#define RCSR 0x04 269 270 271/* PWR */ 272PWR_BASE: .word 0x90020000 273#define PSPR 0x08 274#define PPCR 0x14 275cpuspeed: .word CONFIG_SYS_CPUSPEED 276 277 278cpu_init_crit: 279 /* 280 * mask all IRQs 281 */ 282 ldr r0, IC_BASE 283 mov r1, #0x00 284 str r1, [r0, #ICMR] 285 286 /* set clock speed */ 287 ldr r0, PWR_BASE 288 ldr r1, cpuspeed 289 str r1, [r0, #PPCR] 290 291 /* 292 * before relocating, we have to setup RAM timing 293 * because memory timing is board-dependend, you will 294 * find a lowlevel_init.S in your board directory. 295 */ 296 mov ip, lr 297 bl lowlevel_init 298 mov lr, ip 299 300 /* 301 * disable MMU stuff and enable I-cache 302 */ 303 mrc p15,0,r0,c1,c0 304 bic r0, r0, #0x00002000 @ clear bit 13 (X) 305 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 306 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 307 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 308 mcr p15,0,r0,c1,c0 309 310 /* 311 * flush v4 I/D caches 312 */ 313 mov r0, #0 314 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 315 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 316 317 mov pc, lr 318 319 320/* 321 ************************************************************************* 322 * 323 * Interrupt handling 324 * 325 ************************************************************************* 326 */ 327 328@ 329@ IRQ stack frame. 330@ 331#define S_FRAME_SIZE 72 332 333#define S_OLD_R0 68 334#define S_PSR 64 335#define S_PC 60 336#define S_LR 56 337#define S_SP 52 338 339#define S_IP 48 340#define S_FP 44 341#define S_R10 40 342#define S_R9 36 343#define S_R8 32 344#define S_R7 28 345#define S_R6 24 346#define S_R5 20 347#define S_R4 16 348#define S_R3 12 349#define S_R2 8 350#define S_R1 4 351#define S_R0 0 352 353#define MODE_SVC 0x13 354#define I_BIT 0x80 355 356/* 357 * use bad_save_user_regs for abort/prefetch/undef/swi ... 358 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 359 */ 360 361 .macro bad_save_user_regs 362 sub sp, sp, #S_FRAME_SIZE 363 stmia sp, {r0 - r12} @ Calling r0-r12 364 add r8, sp, #S_PC 365 366 ldr r2, IRQ_STACK_START_IN 367 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 368 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 369 370 add r5, sp, #S_SP 371 mov r1, lr 372 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 373 mov r0, sp 374 .endm 375 376 .macro irq_save_user_regs 377 sub sp, sp, #S_FRAME_SIZE 378 stmia sp, {r0 - r12} @ Calling r0-r12 379 add r8, sp, #S_PC 380 stmdb r8, {sp, lr}^ @ Calling SP, LR 381 str lr, [r8, #0] @ Save calling PC 382 mrs r6, spsr 383 str r6, [r8, #4] @ Save CPSR 384 str r0, [r8, #8] @ Save OLD_R0 385 mov r0, sp 386 .endm 387 388 .macro irq_restore_user_regs 389 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 390 mov r0, r0 391 ldr lr, [sp, #S_PC] @ Get PC 392 add sp, sp, #S_FRAME_SIZE 393 subs pc, lr, #4 @ return & move spsr_svc into cpsr 394 .endm 395 396 .macro get_bad_stack 397 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 398 399 str lr, [r13] @ save caller lr / spsr 400 mrs lr, spsr 401 str lr, [r13, #4] 402 403 mov r13, #MODE_SVC @ prepare SVC-Mode 404 msr spsr_c, r13 405 mov lr, pc 406 movs pc, lr 407 .endm 408 409 .macro get_irq_stack @ setup IRQ stack 410 ldr sp, IRQ_STACK_START 411 .endm 412 413 .macro get_fiq_stack @ setup FIQ stack 414 ldr sp, FIQ_STACK_START 415 .endm 416 417/* 418 * exception handlers 419 */ 420 .align 5 421undefined_instruction: 422 get_bad_stack 423 bad_save_user_regs 424 bl do_undefined_instruction 425 426 .align 5 427software_interrupt: 428 get_bad_stack 429 bad_save_user_regs 430 bl do_software_interrupt 431 432 .align 5 433prefetch_abort: 434 get_bad_stack 435 bad_save_user_regs 436 bl do_prefetch_abort 437 438 .align 5 439data_abort: 440 get_bad_stack 441 bad_save_user_regs 442 bl do_data_abort 443 444 .align 5 445not_used: 446 get_bad_stack 447 bad_save_user_regs 448 bl do_not_used 449 450#ifdef CONFIG_USE_IRQ 451 452 .align 5 453irq: 454 get_irq_stack 455 irq_save_user_regs 456 bl do_irq 457 irq_restore_user_regs 458 459 .align 5 460fiq: 461 get_fiq_stack 462 /* someone ought to write a more effiction fiq_save_user_regs */ 463 irq_save_user_regs 464 bl do_fiq 465 irq_restore_user_regs 466 467#else 468 469 .align 5 470irq: 471 get_bad_stack 472 bad_save_user_regs 473 bl do_irq 474 475 .align 5 476fiq: 477 get_bad_stack 478 bad_save_user_regs 479 bl do_fiq 480 481#endif 482 483 .align 5 484.globl reset_cpu 485reset_cpu: 486 ldr r0, RST_BASE 487 mov r1, #0x0 @ set bit 3-0 ... 488 str r1, [r0, #RCSR] @ ... to clear in RCSR 489 mov r1, #0x1 490 str r1, [r0, #RSRR] @ and perform reset 491 b reset_cpu @ silly, but repeat endlessly 492