1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Z�pke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77 .word CONFIG_SYS_TEXT_BASE 78 79/* 80 * These are defined in the board-specific linker script. 81 * Subtracting _start from them lets the linker put their 82 * relative position in the executable instead of leaving 83 * them null. 84 */ 85.globl _bss_start_ofs 86_bss_start_ofs: 87 .word __bss_start - _start 88 89.globl _bss_end_ofs 90_bss_end_ofs: 91 .word _end - _start 92 93#ifdef CONFIG_USE_IRQ 94/* IRQ stack memory (calculated at run-time) */ 95.globl IRQ_STACK_START 96IRQ_STACK_START: 97 .word 0x0badc0de 98 99/* IRQ stack memory (calculated at run-time) */ 100.globl FIQ_STACK_START 101FIQ_STACK_START: 102 .word 0x0badc0de 103#endif 104 105/* IRQ stack memory (calculated at run-time) + 8 bytes */ 106.globl IRQ_STACK_START_IN 107IRQ_STACK_START_IN: 108 .word 0x0badc0de 109 110/* 111 * the actual reset code 112 */ 113 114reset: 115 /* 116 * set the cpu to SVC32 mode 117 */ 118 mrs r0,cpsr 119 bic r0,r0,#0x1f 120 orr r0,r0,#0xd3 121 msr cpsr,r0 122 123 /* 124 * we do sys-critical inits only at reboot, 125 * not when booting from ram! 126 */ 127#ifndef CONFIG_SKIP_LOWLEVEL_INIT 128 bl cpu_init_crit 129#endif 130 131/* Set stackpointer in internal RAM to call board_init_f */ 132call_board_init_f: 133 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 134 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 135 ldr r0,=0x00000000 136 bl board_init_f 137 138/*------------------------------------------------------------------------------*/ 139 140/* 141 * void relocate_code (addr_sp, gd, addr_moni) 142 * 143 * This "function" does not return, instead it continues in RAM 144 * after relocating the monitor code. 145 * 146 */ 147 .globl relocate_code 148relocate_code: 149 mov r4, r0 /* save addr_sp */ 150 mov r5, r1 /* save addr of gd */ 151 mov r6, r2 /* save addr of destination */ 152 153 /* Set up the stack */ 154stack_setup: 155 mov sp, r4 156 157 adr r0, _start 158 cmp r0, r6 159 beq clear_bss /* skip relocation */ 160 mov r1, r6 /* r1 <- scratch for copy_loop */ 161 ldr r2, _TEXT_BASE 162 ldr r3, _bss_start_ofs 163 add r2, r0, r3 /* r2 <- source end address */ 164 165copy_loop: 166 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 167 stmia r1!, {r9-r10} /* copy to target address [r1] */ 168 cmp r0, r2 /* until source end address [r2] */ 169 blo copy_loop 170 171#ifndef CONFIG_PRELOADER 172 /* 173 * fix .rel.dyn relocations 174 */ 175 ldr r0, _TEXT_BASE /* r0 <- Text base */ 176 sub r9, r6, r0 /* r9 <- relocation offset */ 177 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 178 add r10, r10, r0 /* r10 <- sym table in FLASH */ 179 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 180 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 181 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 182 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 183fixloop: 184 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 185 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 186 ldr r1, [r2, #4] 187 and r7, r1, #0xff 188 cmp r7, #23 /* relative fixup? */ 189 beq fixrel 190 cmp r7, #2 /* absolute fixup? */ 191 beq fixabs 192 /* ignore unknown type of fixup */ 193 b fixnext 194fixabs: 195 /* absolute fix: set location to (offset) symbol value */ 196 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 197 add r1, r10, r1 /* r1 <- address of symbol in table */ 198 ldr r1, [r1, #4] /* r1 <- symbol value */ 199 add r1, r1, r9 /* r1 <- relocated sym addr */ 200 b fixnext 201fixrel: 202 /* relative fix: increase location by offset */ 203 ldr r1, [r0] 204 add r1, r1, r9 205fixnext: 206 str r1, [r0] 207 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 208 cmp r2, r3 209 blo fixloop 210#endif 211 212clear_bss: 213#ifndef CONFIG_PRELOADER 214 ldr r0, _bss_start_ofs 215 ldr r1, _bss_end_ofs 216 ldr r3, _TEXT_BASE /* Text base */ 217 mov r4, r6 /* reloc addr */ 218 add r0, r0, r4 219 add r1, r1, r4 220 mov r2, #0x00000000 /* clear */ 221 222clbss_l:str r2, [r0] /* clear loop... */ 223 add r0, r0, #4 224 cmp r0, r1 225 bne clbss_l 226#endif 227 228/* 229 * We are done. Do not return, instead branch to second part of board 230 * initialization, now running from RAM. 231 */ 232 ldr r0, _board_init_r_ofs 233 adr r1, _start 234 add lr, r0, r1 235 add lr, lr, r9 236 /* setup parameters for board_init_r */ 237 mov r0, r5 /* gd_t */ 238 mov r1, r6 /* dest_addr */ 239 /* jump to it ... */ 240 mov pc, lr 241 242_board_init_r_ofs: 243 .word board_init_r - _start 244 245_rel_dyn_start_ofs: 246 .word __rel_dyn_start - _start 247_rel_dyn_end_ofs: 248 .word __rel_dyn_end - _start 249_dynsym_start_ofs: 250 .word __dynsym_start - _start 251 252/* 253 ************************************************************************* 254 * 255 * CPU_init_critical registers 256 * 257 * setup important registers 258 * setup memory timing 259 * 260 ************************************************************************* 261 */ 262 263 264/* Interupt-Controller base address */ 265IC_BASE: .word 0x90050000 266#define ICMR 0x04 267 268 269/* Reset-Controller */ 270RST_BASE: .word 0x90030000 271#define RSRR 0x00 272#define RCSR 0x04 273 274 275/* PWR */ 276PWR_BASE: .word 0x90020000 277#define PSPR 0x08 278#define PPCR 0x14 279cpuspeed: .word CONFIG_SYS_CPUSPEED 280 281 282cpu_init_crit: 283 /* 284 * mask all IRQs 285 */ 286 ldr r0, IC_BASE 287 mov r1, #0x00 288 str r1, [r0, #ICMR] 289 290 /* set clock speed */ 291 ldr r0, PWR_BASE 292 ldr r1, cpuspeed 293 str r1, [r0, #PPCR] 294 295 /* 296 * before relocating, we have to setup RAM timing 297 * because memory timing is board-dependend, you will 298 * find a lowlevel_init.S in your board directory. 299 */ 300 mov ip, lr 301 bl lowlevel_init 302 mov lr, ip 303 304 /* 305 * disable MMU stuff and enable I-cache 306 */ 307 mrc p15,0,r0,c1,c0 308 bic r0, r0, #0x00002000 @ clear bit 13 (X) 309 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 310 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 311 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 312 mcr p15,0,r0,c1,c0 313 314 /* 315 * flush v4 I/D caches 316 */ 317 mov r0, #0 318 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 319 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 320 321 mov pc, lr 322 323 324/* 325 ************************************************************************* 326 * 327 * Interrupt handling 328 * 329 ************************************************************************* 330 */ 331 332@ 333@ IRQ stack frame. 334@ 335#define S_FRAME_SIZE 72 336 337#define S_OLD_R0 68 338#define S_PSR 64 339#define S_PC 60 340#define S_LR 56 341#define S_SP 52 342 343#define S_IP 48 344#define S_FP 44 345#define S_R10 40 346#define S_R9 36 347#define S_R8 32 348#define S_R7 28 349#define S_R6 24 350#define S_R5 20 351#define S_R4 16 352#define S_R3 12 353#define S_R2 8 354#define S_R1 4 355#define S_R0 0 356 357#define MODE_SVC 0x13 358#define I_BIT 0x80 359 360/* 361 * use bad_save_user_regs for abort/prefetch/undef/swi ... 362 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 363 */ 364 365 .macro bad_save_user_regs 366 sub sp, sp, #S_FRAME_SIZE 367 stmia sp, {r0 - r12} @ Calling r0-r12 368 add r8, sp, #S_PC 369 370 ldr r2, IRQ_STACK_START_IN 371 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 372 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 373 374 add r5, sp, #S_SP 375 mov r1, lr 376 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 377 mov r0, sp 378 .endm 379 380 .macro irq_save_user_regs 381 sub sp, sp, #S_FRAME_SIZE 382 stmia sp, {r0 - r12} @ Calling r0-r12 383 add r8, sp, #S_PC 384 stmdb r8, {sp, lr}^ @ Calling SP, LR 385 str lr, [r8, #0] @ Save calling PC 386 mrs r6, spsr 387 str r6, [r8, #4] @ Save CPSR 388 str r0, [r8, #8] @ Save OLD_R0 389 mov r0, sp 390 .endm 391 392 .macro irq_restore_user_regs 393 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 394 mov r0, r0 395 ldr lr, [sp, #S_PC] @ Get PC 396 add sp, sp, #S_FRAME_SIZE 397 subs pc, lr, #4 @ return & move spsr_svc into cpsr 398 .endm 399 400 .macro get_bad_stack 401 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 402 403 str lr, [r13] @ save caller lr / spsr 404 mrs lr, spsr 405 str lr, [r13, #4] 406 407 mov r13, #MODE_SVC @ prepare SVC-Mode 408 msr spsr_c, r13 409 mov lr, pc 410 movs pc, lr 411 .endm 412 413 .macro get_irq_stack @ setup IRQ stack 414 ldr sp, IRQ_STACK_START 415 .endm 416 417 .macro get_fiq_stack @ setup FIQ stack 418 ldr sp, FIQ_STACK_START 419 .endm 420 421/* 422 * exception handlers 423 */ 424 .align 5 425undefined_instruction: 426 get_bad_stack 427 bad_save_user_regs 428 bl do_undefined_instruction 429 430 .align 5 431software_interrupt: 432 get_bad_stack 433 bad_save_user_regs 434 bl do_software_interrupt 435 436 .align 5 437prefetch_abort: 438 get_bad_stack 439 bad_save_user_regs 440 bl do_prefetch_abort 441 442 .align 5 443data_abort: 444 get_bad_stack 445 bad_save_user_regs 446 bl do_data_abort 447 448 .align 5 449not_used: 450 get_bad_stack 451 bad_save_user_regs 452 bl do_not_used 453 454#ifdef CONFIG_USE_IRQ 455 456 .align 5 457irq: 458 get_irq_stack 459 irq_save_user_regs 460 bl do_irq 461 irq_restore_user_regs 462 463 .align 5 464fiq: 465 get_fiq_stack 466 /* someone ought to write a more effiction fiq_save_user_regs */ 467 irq_save_user_regs 468 bl do_fiq 469 irq_restore_user_regs 470 471#else 472 473 .align 5 474irq: 475 get_bad_stack 476 bad_save_user_regs 477 bl do_irq 478 479 .align 5 480fiq: 481 get_bad_stack 482 bad_save_user_regs 483 bl do_fiq 484 485#endif 486 487 .align 5 488.globl reset_cpu 489reset_cpu: 490 ldr r0, RST_BASE 491 mov r1, #0x0 @ set bit 3-0 ... 492 str r1, [r0, #RCSR] @ ... to clear in RCSR 493 mov r1, #0x1 494 str r1, [r0, #RSRR] @ and perform reset 495 b reset_cpu @ silly, but repeat endlessly 496