1*4909b89eSPriyanka Jain // SPDX-License-Identifier: GPL-2.0+
2*4909b89eSPriyanka Jain /*
3*4909b89eSPriyanka Jain * Copyright 2018 NXP
4*4909b89eSPriyanka Jain */
5*4909b89eSPriyanka Jain
6*4909b89eSPriyanka Jain #include <common.h>
7*4909b89eSPriyanka Jain #include <asm/arch/fsl_serdes.h>
8*4909b89eSPriyanka Jain
9*4909b89eSPriyanka Jain struct serdes_config {
10*4909b89eSPriyanka Jain u8 protocol;
11*4909b89eSPriyanka Jain u8 lanes[SRDS_MAX_LANES];
12*4909b89eSPriyanka Jain };
13*4909b89eSPriyanka Jain
14*4909b89eSPriyanka Jain static struct serdes_config serdes1_cfg_tbl[] = {
15*4909b89eSPriyanka Jain /* SerDes 1 */
16*4909b89eSPriyanka Jain {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
17*4909b89eSPriyanka Jain {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } },
18*4909b89eSPriyanka Jain {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4,
19*4909b89eSPriyanka Jain XFI3 } },
20*4909b89eSPriyanka Jain {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4,
21*4909b89eSPriyanka Jain SGMII3 } },
22*4909b89eSPriyanka Jain {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1,
23*4909b89eSPriyanka Jain PCIE1 } },
24*4909b89eSPriyanka Jain {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4,
25*4909b89eSPriyanka Jain XFI3 } },
26*4909b89eSPriyanka Jain {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4,
27*4909b89eSPriyanka Jain XFI3 } },
28*4909b89eSPriyanka Jain {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } },
29*4909b89eSPriyanka Jain {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4,
30*4909b89eSPriyanka Jain PCIE1 } },
31*4909b89eSPriyanka Jain {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } },
32*4909b89eSPriyanka Jain {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } },
33*4909b89eSPriyanka Jain {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
34*4909b89eSPriyanka Jain {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1,
35*4909b89eSPriyanka Jain _100GE1 } },
36*4909b89eSPriyanka Jain {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1,
37*4909b89eSPriyanka Jain _100GE1 } },
38*4909b89eSPriyanka Jain {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } },
39*4909b89eSPriyanka Jain {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } },
40*4909b89eSPriyanka Jain {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } },
41*4909b89eSPriyanka Jain {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4,
42*4909b89eSPriyanka Jain XFI3 } },
43*4909b89eSPriyanka Jain {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } },
44*4909b89eSPriyanka Jain {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1,
45*4909b89eSPriyanka Jain _40GE1 } },
46*4909b89eSPriyanka Jain {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4,
47*4909b89eSPriyanka Jain _25GE3 } },
48*4909b89eSPriyanka Jain {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
49*4909b89eSPriyanka Jain {}
50*4909b89eSPriyanka Jain };
51*4909b89eSPriyanka Jain
52*4909b89eSPriyanka Jain static struct serdes_config serdes2_cfg_tbl[] = {
53*4909b89eSPriyanka Jain /* SerDes 2 */
54*4909b89eSPriyanka Jain {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } },
55*4909b89eSPriyanka Jain {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
56*4909b89eSPriyanka Jain {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
57*4909b89eSPriyanka Jain {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
58*4909b89eSPriyanka Jain {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } },
59*4909b89eSPriyanka Jain {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13,
60*4909b89eSPriyanka Jain XFI14 } },
61*4909b89eSPriyanka Jain {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13,
62*4909b89eSPriyanka Jain XFI14 } },
63*4909b89eSPriyanka Jain {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } },
64*4909b89eSPriyanka Jain {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13,
65*4909b89eSPriyanka Jain SGMII14} },
66*4909b89eSPriyanka Jain {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4,
67*4909b89eSPriyanka Jain PCIE4 } },
68*4909b89eSPriyanka Jain {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13,
69*4909b89eSPriyanka Jain SGMII14 } },
70*4909b89eSPriyanka Jain {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1,
71*4909b89eSPriyanka Jain SATA2 } },
72*4909b89eSPriyanka Jain {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } },
73*4909b89eSPriyanka Jain {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13,
74*4909b89eSPriyanka Jain SGMII14 } },
75*4909b89eSPriyanka Jain {}
76*4909b89eSPriyanka Jain };
77*4909b89eSPriyanka Jain
78*4909b89eSPriyanka Jain static struct serdes_config serdes3_cfg_tbl[] = {
79*4909b89eSPriyanka Jain /* SerDes 3 */
80*4909b89eSPriyanka Jain {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } },
81*4909b89eSPriyanka Jain {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } },
82*4909b89eSPriyanka Jain {}
83*4909b89eSPriyanka Jain };
84*4909b89eSPriyanka Jain
85*4909b89eSPriyanka Jain static struct serdes_config *serdes_cfg_tbl[] = {
86*4909b89eSPriyanka Jain serdes1_cfg_tbl,
87*4909b89eSPriyanka Jain serdes2_cfg_tbl,
88*4909b89eSPriyanka Jain serdes3_cfg_tbl,
89*4909b89eSPriyanka Jain };
90*4909b89eSPriyanka Jain
serdes_get_prtcl(int serdes,int cfg,int lane)91*4909b89eSPriyanka Jain enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
92*4909b89eSPriyanka Jain {
93*4909b89eSPriyanka Jain struct serdes_config *ptr;
94*4909b89eSPriyanka Jain
95*4909b89eSPriyanka Jain if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
96*4909b89eSPriyanka Jain return 0;
97*4909b89eSPriyanka Jain
98*4909b89eSPriyanka Jain ptr = serdes_cfg_tbl[serdes];
99*4909b89eSPriyanka Jain while (ptr->protocol) {
100*4909b89eSPriyanka Jain if (ptr->protocol == cfg)
101*4909b89eSPriyanka Jain return ptr->lanes[lane];
102*4909b89eSPriyanka Jain ptr++;
103*4909b89eSPriyanka Jain }
104*4909b89eSPriyanka Jain
105*4909b89eSPriyanka Jain return 0;
106*4909b89eSPriyanka Jain }
107*4909b89eSPriyanka Jain
is_serdes_prtcl_valid(int serdes,u32 prtcl)108*4909b89eSPriyanka Jain int is_serdes_prtcl_valid(int serdes, u32 prtcl)
109*4909b89eSPriyanka Jain {
110*4909b89eSPriyanka Jain int i;
111*4909b89eSPriyanka Jain struct serdes_config *ptr;
112*4909b89eSPriyanka Jain
113*4909b89eSPriyanka Jain if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
114*4909b89eSPriyanka Jain return 0;
115*4909b89eSPriyanka Jain
116*4909b89eSPriyanka Jain ptr = serdes_cfg_tbl[serdes];
117*4909b89eSPriyanka Jain while (ptr->protocol) {
118*4909b89eSPriyanka Jain if (ptr->protocol == prtcl)
119*4909b89eSPriyanka Jain break;
120*4909b89eSPriyanka Jain ptr++;
121*4909b89eSPriyanka Jain }
122*4909b89eSPriyanka Jain
123*4909b89eSPriyanka Jain if (!ptr->protocol)
124*4909b89eSPriyanka Jain return 0;
125*4909b89eSPriyanka Jain
126*4909b89eSPriyanka Jain for (i = 0; i < SRDS_MAX_LANES; i++) {
127*4909b89eSPriyanka Jain if (ptr->lanes[i] != NONE)
128*4909b89eSPriyanka Jain return 1;
129*4909b89eSPriyanka Jain }
130*4909b89eSPriyanka Jain
131*4909b89eSPriyanka Jain return 0;
132*4909b89eSPriyanka Jain }
133