1/* 2 * (C) Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Extracted from armv8/start.S 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/gic.h> 12#include <asm/macro.h> 13#ifdef CONFIG_MP 14#include <asm/arch/mp.h> 15#endif 16 17ENTRY(lowlevel_init) 18 mov x29, lr /* Save LR */ 19 20#ifdef CONFIG_FSL_LSCH3 21 22 /* Set Wuo bit for RN-I 20 */ 23#ifdef CONFIG_LS2080A 24 ldr x0, =CCI_AUX_CONTROL_BASE(20) 25 ldr x1, =0x00000010 26 bl ccn504_set_aux 27#endif 28 29 /* Add fully-coherent masters to DVM domain */ 30 ldr x0, =CCI_MN_BASE 31 ldr x1, =CCI_MN_RNF_NODEID_LIST 32 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET 33 bl ccn504_add_masters_to_dvm 34 35 /* Set all RN-I ports to QoS of 15 */ 36 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) 37 ldr x1, =0x00FF000C 38 bl ccn504_set_qos 39 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) 40 ldr x1, =0x00FF000C 41 bl ccn504_set_qos 42 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) 43 ldr x1, =0x00FF000C 44 bl ccn504_set_qos 45 46 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) 47 ldr x1, =0x00FF000C 48 bl ccn504_set_qos 49 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) 50 ldr x1, =0x00FF000C 51 bl ccn504_set_qos 52 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) 53 ldr x1, =0x00FF000C 54 bl ccn504_set_qos 55 56 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) 57 ldr x1, =0x00FF000C 58 bl ccn504_set_qos 59 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) 60 ldr x1, =0x00FF000C 61 bl ccn504_set_qos 62 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) 63 ldr x1, =0x00FF000C 64 bl ccn504_set_qos 65 66 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) 67 ldr x1, =0x00FF000C 68 bl ccn504_set_qos 69 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) 70 ldr x1, =0x00FF000C 71 bl ccn504_set_qos 72 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) 73 ldr x1, =0x00FF000C 74 bl ccn504_set_qos 75 76 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) 77 ldr x1, =0x00FF000C 78 bl ccn504_set_qos 79 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) 80 ldr x1, =0x00FF000C 81 bl ccn504_set_qos 82 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) 83 ldr x1, =0x00FF000C 84 bl ccn504_set_qos 85 86 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) 87 ldr x1, =0x00FF000C 88 bl ccn504_set_qos 89 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) 90 ldr x1, =0x00FF000C 91 bl ccn504_set_qos 92 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) 93 ldr x1, =0x00FF000C 94 bl ccn504_set_qos 95#endif 96 97#ifdef SMMU_BASE 98 /* Set the SMMU page size in the sACR register */ 99 ldr x1, =SMMU_BASE 100 ldr w0, [x1, #0x10] 101 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ 102 str w0, [x1, #0x10] 103#endif 104 105 /* Initialize GIC Secure Bank Status */ 106#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 107 branch_if_slave x0, 1f 108 ldr x0, =GICD_BASE 109 bl gic_init_secure 1101: 111#ifdef CONFIG_GICV3 112 ldr x0, =GICR_BASE 113 bl gic_init_secure_percpu 114#elif defined(CONFIG_GICV2) 115 ldr x0, =GICD_BASE 116 ldr x1, =GICC_BASE 117 bl gic_init_secure_percpu 118#endif 119#endif 120 121 branch_if_master x0, x1, 2f 122 123#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) 124 ldr x0, =secondary_boot_func 125 blr x0 126#endif 127 1282: 129#ifdef CONFIG_FSL_TZPC_BP147 130 /* Set Non Secure access for all devices protected via TZPC */ 131 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ 132 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */ 133 str w0, [x1] 134 135 isb 136 dsb sy 137#endif 138 139#ifdef CONFIG_FSL_TZASC_400 140 /* Set TZASC so that: 141 * a. We use only Region0 whose global secure write/read is EN 142 * b. We use only Region0 whose NSAID write/read is EN 143 * 144 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just 145 * placeholders. 146 */ 147 ldr x1, =TZASC_GATE_KEEPER(0) 148 ldr x0, [x1] /* Filter 0 Gate Keeper Register */ 149 orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ 150 str x0, [x1] 151 152 ldr x1, =TZASC_GATE_KEEPER(1) 153 ldr x0, [x1] /* Filter 0 Gate Keeper Register */ 154 orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ 155 str x0, [x1] 156 157 ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) 158 ldr x0, [x1] /* Region-0 Attributes Register */ 159 orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ 160 orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ 161 str x0, [x1] 162 163 ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) 164 ldr x0, [x1] /* Region-1 Attributes Register */ 165 orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ 166 orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ 167 str x0, [x1] 168 169 ldr x1, =TZASC_REGION_ID_ACCESS_0(0) 170 ldr w0, [x1] /* Region-0 Access Register */ 171 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ 172 str w0, [x1] 173 174 ldr x1, =TZASC_REGION_ID_ACCESS_0(1) 175 ldr w0, [x1] /* Region-1 Attributes Register */ 176 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ 177 str w0, [x1] 178 179 isb 180 dsb sy 181#endif 182 183#ifdef CONFIG_ARCH_LS1046A 184 /* Initialize the L2 RAM latency */ 185 mrs x1, S3_1_c11_c0_2 186 mov x0, #0x1C7 187 /* Clear L2 Tag RAM latency and L2 Data RAM latency */ 188 bic x1, x1, x0 189 /* Set L2 data ram latency bits [2:0] */ 190 orr x1, x1, #0x2 191 /* set L2 tag ram latency bits [8:6] */ 192 orr x1, x1, #0x80 193 msr S3_1_c11_c0_2, x1 194 isb 195#endif 196 197 mov lr, x29 /* Restore LR */ 198 ret 199ENDPROC(lowlevel_init) 200 201#ifdef CONFIG_FSL_LSCH3 202hnf_pstate_poll: 203 /* x0 has the desired status, return 0 for success, 1 for timeout 204 * clobber x1, x2, x3, x4, x6, x7 205 */ 206 mov x1, x0 207 mov x7, #0 /* flag for timeout */ 208 mrs x3, cntpct_el0 /* read timer */ 209 add x3, x3, #1200 /* timeout after 100 microseconds */ 210 mov x0, #0x18 211 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ 212 mov w6, #8 /* HN-F node count */ 2131: 214 ldr x2, [x0] 215 cmp x2, x1 /* check status */ 216 b.eq 2f 217 mrs x4, cntpct_el0 218 cmp x4, x3 219 b.ls 1b 220 mov x7, #1 /* timeout */ 221 b 3f 2222: 223 add x0, x0, #0x10000 /* move to next node */ 224 subs w6, w6, #1 225 cbnz w6, 1b 2263: 227 mov x0, x7 228 ret 229 230hnf_set_pstate: 231 /* x0 has the desired state, clobber x1, x2, x6 */ 232 mov x1, x0 233 /* power state to SFONLY */ 234 mov w6, #8 /* HN-F node count */ 235 mov x0, #0x10 236 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */ 2371: /* set pstate to sfonly */ 238 ldr x2, [x0] 239 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ 240 orr x2, x2, x1 241 str x2, [x0] 242 add x0, x0, #0x10000 /* move to next node */ 243 subs w6, w6, #1 244 cbnz w6, 1b 245 246 ret 247 248ENTRY(__asm_flush_l3_cache) 249 /* 250 * Return status in x0 251 * success 0 252 * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both 253 */ 254 mov x29, lr 255 mov x8, #0 256 257 dsb sy 258 mov x0, #0x1 /* HNFPSTAT_SFONLY */ 259 bl hnf_set_pstate 260 261 mov x0, #0x4 /* SFONLY status */ 262 bl hnf_pstate_poll 263 cbz x0, 1f 264 mov x8, #1 /* timeout */ 2651: 266 dsb sy 267 mov x0, #0x3 /* HNFPSTAT_FAM */ 268 bl hnf_set_pstate 269 270 mov x0, #0xc /* FAM status */ 271 bl hnf_pstate_poll 272 cbz x0, 1f 273 add x8, x8, #0x2 2741: 275 mov x0, x8 276 mov lr, x29 277 ret 278ENDPROC(__asm_flush_l3_cache) 279#endif 280 281#ifdef CONFIG_MP 282 /* Keep literals not used by the secondary boot code outside it */ 283 .ltorg 284 285 /* Using 64 bit alignment since the spin table is accessed as data */ 286 .align 4 287 .global secondary_boot_code 288 /* Secondary Boot Code starts here */ 289secondary_boot_code: 290 .global __spin_table 291__spin_table: 292 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE 293 294 .align 2 295ENTRY(secondary_boot_func) 296 /* 297 * MPIDR_EL1 Fields: 298 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) 299 * MPIDR[7:2] = AFF0_RES 300 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) 301 * MPIDR[23:16] = AFF2_CLUSTERID 302 * MPIDR[24] = MT 303 * MPIDR[29:25] = RES0 304 * MPIDR[30] = U 305 * MPIDR[31] = ME 306 * MPIDR[39:32] = AFF3 307 * 308 * Linear Processor ID (LPID) calculation from MPIDR_EL1: 309 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now 310 * until AFF2_CLUSTERID and AFF3 have non-zero values) 311 * 312 * LPID = MPIDR[15:8] | MPIDR[1:0] 313 */ 314 mrs x0, mpidr_el1 315 ubfm x1, x0, #8, #15 316 ubfm x2, x0, #0, #1 317 orr x10, x2, x1, lsl #2 /* x10 has LPID */ 318 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ 319 /* 320 * offset of the spin table element for this core from start of spin 321 * table (each elem is padded to 64 bytes) 322 */ 323 lsl x1, x10, #6 324 ldr x0, =__spin_table 325 /* physical address of this cpus spin table element */ 326 add x11, x1, x0 327 328 ldr x0, =__real_cntfrq 329 ldr x0, [x0] 330 msr cntfrq_el0, x0 /* set with real frequency */ 331 str x9, [x11, #16] /* LPID */ 332 mov x4, #1 333 str x4, [x11, #8] /* STATUS */ 334 dsb sy 335#if defined(CONFIG_GICV3) 336 gic_wait_for_interrupt_m x0 337#elif defined(CONFIG_GICV2) 338 ldr x0, =GICC_BASE 339 gic_wait_for_interrupt_m x0, w1 340#endif 341 342 bl secondary_switch_to_el2 343#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 344 bl secondary_switch_to_el1 345#endif 346 347slave_cpu: 348 wfe 349 ldr x0, [x11] 350 cbz x0, slave_cpu 351#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 352 mrs x1, sctlr_el2 353#else 354 mrs x1, sctlr_el1 355#endif 356 tbz x1, #25, cpu_is_le 357 rev x0, x0 /* BE to LE conversion */ 358cpu_is_le: 359 br x0 /* branch to the given address */ 360ENDPROC(secondary_boot_func) 361 362ENTRY(secondary_switch_to_el2) 363 switch_el x0, 1f, 0f, 0f 3640: ret 3651: armv8_switch_to_el2_m x0 366ENDPROC(secondary_switch_to_el2) 367 368ENTRY(secondary_switch_to_el1) 369 switch_el x0, 0f, 1f, 0f 3700: ret 3711: armv8_switch_to_el1_m x0, x1 372ENDPROC(secondary_switch_to_el1) 373 374 /* Ensure that the literals used by the secondary boot code are 375 * assembled within it (this is required so that we can protect 376 * this area with a single memreserve region 377 */ 378 .ltorg 379 380 /* 64 bit alignment for elements accessed as data */ 381 .align 4 382 .global __real_cntfrq 383__real_cntfrq: 384 .quad COUNTER_FREQUENCY 385 .globl __secondary_boot_code_size 386 .type __secondary_boot_code_size, %object 387 /* Secondary Boot Code ends here */ 388__secondary_boot_code_size: 389 .quad .-secondary_boot_code 390#endif 391