19f3183d2SMingkai Hu /* 29f3183d2SMingkai Hu * Copyright 2014-2015 Freescale Semiconductor, Inc. 39f3183d2SMingkai Hu * 49f3183d2SMingkai Hu * SPDX-License-Identifier: GPL-2.0+ 59f3183d2SMingkai Hu */ 69f3183d2SMingkai Hu 79f3183d2SMingkai Hu #include <common.h> 85a37a2f0SAlexander Graf #include <efi_loader.h> 99f3183d2SMingkai Hu #include <libfdt.h> 109f3183d2SMingkai Hu #include <fdt_support.h> 119f3183d2SMingkai Hu #include <phy.h> 129f3183d2SMingkai Hu #ifdef CONFIG_FSL_LSCH3 139f3183d2SMingkai Hu #include <asm/arch/fdt.h> 149f3183d2SMingkai Hu #endif 159f3183d2SMingkai Hu #ifdef CONFIG_FSL_ESDHC 169f3183d2SMingkai Hu #include <fsl_esdhc.h> 179f3183d2SMingkai Hu #endif 180e52b6feSQianyu Gong #ifdef CONFIG_SYS_DPAA_FMAN 190e52b6feSQianyu Gong #include <fsl_fman.h> 200e52b6feSQianyu Gong #endif 219f3183d2SMingkai Hu #ifdef CONFIG_MP 229f3183d2SMingkai Hu #include <asm/arch/mp.h> 239f3183d2SMingkai Hu #endif 24f13c99c2SAlex Porosanu #include <fsl_sec.h> 25f13c99c2SAlex Porosanu #include <asm/arch-fsl-layerscape/soc.h> 26032d5bb4SHou Zhiqiang #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT 27032d5bb4SHou Zhiqiang #include <asm/armv8/sec_firmware.h> 28032d5bb4SHou Zhiqiang #endif 299f3183d2SMingkai Hu 30e8297341SShaohui Xie int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) 31e8297341SShaohui Xie { 32e8297341SShaohui Xie return fdt_setprop_string(blob, offset, "phy-connection-type", 33e8297341SShaohui Xie phy_string_for_interface(phyc)); 34e8297341SShaohui Xie } 35e8297341SShaohui Xie 369f3183d2SMingkai Hu #ifdef CONFIG_MP 379f3183d2SMingkai Hu void ft_fixup_cpu(void *blob) 389f3183d2SMingkai Hu { 399f3183d2SMingkai Hu int off; 409f3183d2SMingkai Hu __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); 419f3183d2SMingkai Hu fdt32_t *reg; 429f3183d2SMingkai Hu int addr_cells; 439f3183d2SMingkai Hu u64 val, core_id; 449f3183d2SMingkai Hu size_t *boot_code_size = &(__secondary_boot_code_size); 452d16a1a6Smacro.wave.z@gmail.com #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ 462d16a1a6Smacro.wave.z@gmail.com defined(CONFIG_FSL_PPA_ARMV8_PSCI) 47032d5bb4SHou Zhiqiang int node; 48032d5bb4SHou Zhiqiang u32 psci_ver; 499f3183d2SMingkai Hu 50032d5bb4SHou Zhiqiang /* Check the psci version to determine if the psci is supported */ 51032d5bb4SHou Zhiqiang psci_ver = sec_firmware_support_psci_version(); 52032d5bb4SHou Zhiqiang if (psci_ver == 0xffffffff) { 53032d5bb4SHou Zhiqiang /* remove psci DT node */ 54032d5bb4SHou Zhiqiang node = fdt_path_offset(blob, "/psci"); 55032d5bb4SHou Zhiqiang if (node >= 0) 56032d5bb4SHou Zhiqiang goto remove_psci_node; 57032d5bb4SHou Zhiqiang 58032d5bb4SHou Zhiqiang node = fdt_node_offset_by_compatible(blob, -1, "arm,psci"); 59032d5bb4SHou Zhiqiang if (node >= 0) 60032d5bb4SHou Zhiqiang goto remove_psci_node; 61032d5bb4SHou Zhiqiang 62032d5bb4SHou Zhiqiang node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2"); 63032d5bb4SHou Zhiqiang if (node >= 0) 64032d5bb4SHou Zhiqiang goto remove_psci_node; 65032d5bb4SHou Zhiqiang 66032d5bb4SHou Zhiqiang node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0"); 67032d5bb4SHou Zhiqiang if (node >= 0) 68032d5bb4SHou Zhiqiang goto remove_psci_node; 69032d5bb4SHou Zhiqiang 70032d5bb4SHou Zhiqiang remove_psci_node: 71032d5bb4SHou Zhiqiang if (node >= 0) 72032d5bb4SHou Zhiqiang fdt_del_node(blob, node); 73032d5bb4SHou Zhiqiang } else { 74032d5bb4SHou Zhiqiang return; 75032d5bb4SHou Zhiqiang } 76032d5bb4SHou Zhiqiang #endif 779f3183d2SMingkai Hu off = fdt_path_offset(blob, "/cpus"); 789f3183d2SMingkai Hu if (off < 0) { 799f3183d2SMingkai Hu puts("couldn't find /cpus node\n"); 809f3183d2SMingkai Hu return; 819f3183d2SMingkai Hu } 829f3183d2SMingkai Hu of_bus_default_count_cells(blob, off, &addr_cells, NULL); 839f3183d2SMingkai Hu 849f3183d2SMingkai Hu off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 859f3183d2SMingkai Hu while (off != -FDT_ERR_NOTFOUND) { 869f3183d2SMingkai Hu reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); 879f3183d2SMingkai Hu if (reg) { 889f3183d2SMingkai Hu core_id = of_read_number(reg, addr_cells); 899f3183d2SMingkai Hu if (core_id == 0 || (is_core_online(core_id))) { 909f3183d2SMingkai Hu val = spin_tbl_addr; 919f3183d2SMingkai Hu val += id_to_core(core_id) * 929f3183d2SMingkai Hu SPIN_TABLE_ELEM_SIZE; 939f3183d2SMingkai Hu val = cpu_to_fdt64(val); 949f3183d2SMingkai Hu fdt_setprop_string(blob, off, "enable-method", 959f3183d2SMingkai Hu "spin-table"); 969f3183d2SMingkai Hu fdt_setprop(blob, off, "cpu-release-addr", 979f3183d2SMingkai Hu &val, sizeof(val)); 989f3183d2SMingkai Hu } else { 999f3183d2SMingkai Hu debug("skipping offline core\n"); 1009f3183d2SMingkai Hu } 1019f3183d2SMingkai Hu } else { 1029f3183d2SMingkai Hu puts("Warning: found cpu node without reg property\n"); 1039f3183d2SMingkai Hu } 1049f3183d2SMingkai Hu off = fdt_node_offset_by_prop_value(blob, off, "device_type", 1059f3183d2SMingkai Hu "cpu", 4); 1069f3183d2SMingkai Hu } 1079f3183d2SMingkai Hu 1089f3183d2SMingkai Hu fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, 1099f3183d2SMingkai Hu *boot_code_size); 1105a37a2f0SAlexander Graf #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) 1115a37a2f0SAlexander Graf efi_add_memory_map((uintptr_t)&secondary_boot_code, 1125a37a2f0SAlexander Graf ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, 1135a37a2f0SAlexander Graf EFI_RESERVED_MEMORY_TYPE, false); 1145a37a2f0SAlexander Graf #endif 1159f3183d2SMingkai Hu } 1169f3183d2SMingkai Hu #endif 1179f3183d2SMingkai Hu 118c93db4f7SSriram Dash void fsl_fdt_disable_usb(void *blob) 119c93db4f7SSriram Dash { 120c93db4f7SSriram Dash int off; 121c93db4f7SSriram Dash /* 122c93db4f7SSriram Dash * SYSCLK is used as a reference clock for USB. When the USB 123c93db4f7SSriram Dash * controller is used, SYSCLK must meet the additional requirement 124c93db4f7SSriram Dash * of 100 MHz. 125c93db4f7SSriram Dash */ 126c93db4f7SSriram Dash if (CONFIG_SYS_CLK_FREQ != 100000000) { 127c93db4f7SSriram Dash off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); 128c93db4f7SSriram Dash while (off != -FDT_ERR_NOTFOUND) { 129c93db4f7SSriram Dash fdt_status_disabled(blob, off); 130c93db4f7SSriram Dash off = fdt_node_offset_by_compatible(blob, off, 131c93db4f7SSriram Dash "snps,dwc3"); 132c93db4f7SSriram Dash } 133c93db4f7SSriram Dash } 134c93db4f7SSriram Dash } 135c93db4f7SSriram Dash 136*fa18ed76SWenbin Song #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 137*fa18ed76SWenbin Song static void fdt_fixup_gic(void *blob) 138*fa18ed76SWenbin Song { 139*fa18ed76SWenbin Song int offset, err; 140*fa18ed76SWenbin Song u64 reg[8]; 141*fa18ed76SWenbin Song struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 142*fa18ed76SWenbin Song unsigned int val; 143*fa18ed76SWenbin Song struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 144*fa18ed76SWenbin Song int align_64k = 0; 145*fa18ed76SWenbin Song 146*fa18ed76SWenbin Song val = gur_in32(&gur->svr); 147*fa18ed76SWenbin Song 148*fa18ed76SWenbin Song if (SVR_SOC_VER(val) != SVR_LS1043A) { 149*fa18ed76SWenbin Song align_64k = 1; 150*fa18ed76SWenbin Song } else if (SVR_REV(val) != REV1_0) { 151*fa18ed76SWenbin Song val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); 152*fa18ed76SWenbin Song if (!val) 153*fa18ed76SWenbin Song align_64k = 1; 154*fa18ed76SWenbin Song } 155*fa18ed76SWenbin Song 156*fa18ed76SWenbin Song offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); 157*fa18ed76SWenbin Song if (offset < 0) { 158*fa18ed76SWenbin Song printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", 159*fa18ed76SWenbin Song "interrupt-controller@1400000", fdt_strerror(offset)); 160*fa18ed76SWenbin Song return; 161*fa18ed76SWenbin Song } 162*fa18ed76SWenbin Song 163*fa18ed76SWenbin Song /* Fixup gic node align with 64K */ 164*fa18ed76SWenbin Song if (align_64k) { 165*fa18ed76SWenbin Song reg[0] = cpu_to_fdt64(GICD_BASE_64K); 166*fa18ed76SWenbin Song reg[1] = cpu_to_fdt64(GICD_SIZE_64K); 167*fa18ed76SWenbin Song reg[2] = cpu_to_fdt64(GICC_BASE_64K); 168*fa18ed76SWenbin Song reg[3] = cpu_to_fdt64(GICC_SIZE_64K); 169*fa18ed76SWenbin Song reg[4] = cpu_to_fdt64(GICH_BASE_64K); 170*fa18ed76SWenbin Song reg[5] = cpu_to_fdt64(GICH_SIZE_64K); 171*fa18ed76SWenbin Song reg[6] = cpu_to_fdt64(GICV_BASE_64K); 172*fa18ed76SWenbin Song reg[7] = cpu_to_fdt64(GICV_SIZE_64K); 173*fa18ed76SWenbin Song } else { 174*fa18ed76SWenbin Song /* Fixup gic node align with default */ 175*fa18ed76SWenbin Song reg[0] = cpu_to_fdt64(GICD_BASE); 176*fa18ed76SWenbin Song reg[1] = cpu_to_fdt64(GICD_SIZE); 177*fa18ed76SWenbin Song reg[2] = cpu_to_fdt64(GICC_BASE); 178*fa18ed76SWenbin Song reg[3] = cpu_to_fdt64(GICC_SIZE); 179*fa18ed76SWenbin Song reg[4] = cpu_to_fdt64(GICH_BASE); 180*fa18ed76SWenbin Song reg[5] = cpu_to_fdt64(GICH_SIZE); 181*fa18ed76SWenbin Song reg[6] = cpu_to_fdt64(GICV_BASE); 182*fa18ed76SWenbin Song reg[7] = cpu_to_fdt64(GICV_SIZE); 183*fa18ed76SWenbin Song } 184*fa18ed76SWenbin Song 185*fa18ed76SWenbin Song err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); 186*fa18ed76SWenbin Song if (err < 0) { 187*fa18ed76SWenbin Song printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", 188*fa18ed76SWenbin Song "reg", "interrupt-controller@1400000", 189*fa18ed76SWenbin Song fdt_strerror(err)); 190*fa18ed76SWenbin Song return; 191*fa18ed76SWenbin Song } 192*fa18ed76SWenbin Song 193*fa18ed76SWenbin Song return; 194*fa18ed76SWenbin Song } 195*fa18ed76SWenbin Song #endif 196*fa18ed76SWenbin Song 1979f3183d2SMingkai Hu void ft_cpu_setup(void *blob, bd_t *bd) 1989f3183d2SMingkai Hu { 199f13c99c2SAlex Porosanu #ifdef CONFIG_FSL_LSCH2 200f13c99c2SAlex Porosanu struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 201f13c99c2SAlex Porosanu unsigned int svr = in_be32(&gur->svr); 202f13c99c2SAlex Porosanu 203f13c99c2SAlex Porosanu /* delete crypto node if not on an E-processor */ 204f13c99c2SAlex Porosanu if (!IS_E_PROCESSOR(svr)) 205f13c99c2SAlex Porosanu fdt_fixup_crypto_node(blob, 0); 206f13c99c2SAlex Porosanu #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 207f13c99c2SAlex Porosanu else { 208f13c99c2SAlex Porosanu ccsr_sec_t __iomem *sec; 209f13c99c2SAlex Porosanu 210f13c99c2SAlex Porosanu sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 211f13c99c2SAlex Porosanu fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); 212f13c99c2SAlex Porosanu } 213f13c99c2SAlex Porosanu #endif 214f13c99c2SAlex Porosanu #endif 215f13c99c2SAlex Porosanu 2169f3183d2SMingkai Hu #ifdef CONFIG_MP 2179f3183d2SMingkai Hu ft_fixup_cpu(blob); 2189f3183d2SMingkai Hu #endif 2199f3183d2SMingkai Hu 2209f3183d2SMingkai Hu #ifdef CONFIG_SYS_NS16550 2219f3183d2SMingkai Hu do_fixup_by_compat_u32(blob, "fsl,ns16550", 2229f3183d2SMingkai Hu "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 2239f3183d2SMingkai Hu #endif 2249f3183d2SMingkai Hu 2256f14e257SPrabhakar Kushwaha do_fixup_by_compat_u32(blob, "fixed-clock", 2266f14e257SPrabhakar Kushwaha "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 2276f14e257SPrabhakar Kushwaha 2289f3183d2SMingkai Hu #ifdef CONFIG_PCI 2299f3183d2SMingkai Hu ft_pci_setup(blob, bd); 2309f3183d2SMingkai Hu #endif 2319f3183d2SMingkai Hu 2329f3183d2SMingkai Hu #ifdef CONFIG_FSL_ESDHC 2339f3183d2SMingkai Hu fdt_fixup_esdhc(blob, bd); 2349f3183d2SMingkai Hu #endif 2359f3183d2SMingkai Hu 2360e52b6feSQianyu Gong #ifdef CONFIG_SYS_DPAA_FMAN 2370e52b6feSQianyu Gong fdt_fixup_fman_firmware(blob); 2380e52b6feSQianyu Gong #endif 239c93db4f7SSriram Dash fsl_fdt_disable_usb(blob); 240c93db4f7SSriram Dash 241*fa18ed76SWenbin Song #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 242*fa18ed76SWenbin Song fdt_fixup_gic(blob); 243*fa18ed76SWenbin Song #endif 2449f3183d2SMingkai Hu } 245