1 /* 2 * (C) Copyright 2013 3 * Andre Przywara, Linaro <andre.przywara@linaro.org> 4 * 5 * Routines to transition ARMv7 processors from secure into non-secure state 6 * and from non-secure SVC into HYP mode 7 * needed to enable ARMv7 virtualization for current hypervisors 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/armv7.h> 14 #include <asm/gic.h> 15 #include <asm/io.h> 16 #include <asm/secure.h> 17 18 unsigned long gic_dist_addr; 19 20 static unsigned int read_id_pfr1(void) 21 { 22 unsigned int reg; 23 24 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); 25 return reg; 26 } 27 28 static unsigned long get_gicd_base_address(void) 29 { 30 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS 31 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; 32 #else 33 unsigned midr; 34 unsigned periphbase; 35 36 /* check whether we are an Cortex-A15 or A7. 37 * The actual HYP switch should work with all CPUs supporting 38 * the virtualization extension, but we need the GIC address, 39 * which we know only for sure for those two CPUs. 40 */ 41 asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); 42 switch (midr & MIDR_PRIMARY_PART_MASK) { 43 case MIDR_CORTEX_A9_R0P1: 44 case MIDR_CORTEX_A15_R0P0: 45 case MIDR_CORTEX_A7_R0P0: 46 break; 47 default: 48 printf("nonsec: could not determine GIC address.\n"); 49 return -1; 50 } 51 52 /* get the GIC base address from the CBAR register */ 53 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); 54 55 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to 56 * encode this). Bail out here since we cannot access this without 57 * enabling paging. 58 */ 59 if ((periphbase & 0xff) != 0) { 60 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); 61 return -1; 62 } 63 64 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; 65 #endif 66 } 67 68 static void relocate_secure_section(void) 69 { 70 #ifdef CONFIG_ARMV7_SECURE_BASE 71 size_t sz = __secure_end - __secure_start; 72 73 memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); 74 flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, 75 CONFIG_ARMV7_SECURE_BASE + sz + 1); 76 invalidate_icache_all(); 77 #endif 78 } 79 80 static void kick_secondary_cpus_gic(unsigned long gicdaddr) 81 { 82 /* kick all CPUs (except this one) by writing to GICD_SGIR */ 83 writel(1U << 24, gicdaddr + GICD_SGIR); 84 } 85 86 void __weak smp_kick_all_cpus(void) 87 { 88 kick_secondary_cpus_gic(gic_dist_addr); 89 } 90 91 int armv7_init_nonsec(void) 92 { 93 unsigned int reg; 94 unsigned itlinesnr, i; 95 96 /* check whether the CPU supports the security extensions */ 97 reg = read_id_pfr1(); 98 if ((reg & 0xF0) == 0) { 99 printf("nonsec: Security extensions not implemented.\n"); 100 return -1; 101 } 102 103 /* the SCR register will be set directly in the monitor mode handler, 104 * according to the spec one should not tinker with it in secure state 105 * in SVC mode. Do not try to read it once in non-secure state, 106 * any access to it will trap. 107 */ 108 109 gic_dist_addr = get_gicd_base_address(); 110 if (gic_dist_addr == -1) 111 return -1; 112 113 /* enable the GIC distributor */ 114 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, 115 gic_dist_addr + GICD_CTLR); 116 117 /* TYPER[4:0] contains an encoded number of available interrupts */ 118 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; 119 120 /* set all bits in the GIC group registers to one to allow access 121 * from non-secure state. The first 32 interrupts are private per 122 * CPU and will be set later when enabling the GIC for each core 123 */ 124 for (i = 1; i <= itlinesnr; i++) 125 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); 126 127 #ifndef CONFIG_ARMV7_PSCI 128 smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); 129 smp_kick_all_cpus(); 130 #endif 131 132 /* call the non-sec switching code on this CPU also */ 133 relocate_secure_section(); 134 secure_ram_addr(_nonsec_init)(); 135 return 0; 136 } 137