1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35 36.globl _start 37_start: b reset 38 ldr pc, _undefined_instruction 39 ldr pc, _software_interrupt 40 ldr pc, _prefetch_abort 41 ldr pc, _data_abort 42 ldr pc, _not_used 43 ldr pc, _irq 44 ldr pc, _fiq 45 46_undefined_instruction: .word undefined_instruction 47_software_interrupt: .word software_interrupt 48_prefetch_abort: .word prefetch_abort 49_data_abort: .word data_abort 50_not_used: .word not_used 51_irq: .word irq 52_fiq: .word fiq 53_pad: .word 0x12345678 /* now 16*4=64 */ 54.global _end_vect 55_end_vect: 56 57 .balignl 16,0xdeadbeef 58/************************************************************************* 59 * 60 * Startup Code (reset vector) 61 * 62 * do important init only if we don't start from memory! 63 * setup Memory and board specific bits prior to relocation. 64 * relocate armboot to ram 65 * setup stack 66 * 67 *************************************************************************/ 68 69.globl _TEXT_BASE 70_TEXT_BASE: 71 .word CONFIG_SYS_TEXT_BASE 72 73/* 74 * These are defined in the board-specific linker script. 75 */ 76.globl _bss_start_ofs 77_bss_start_ofs: 78 .word __bss_start - _start 79 80.globl _bss_end_ofs 81_bss_end_ofs: 82 .word _end - _start 83 84#ifdef CONFIG_USE_IRQ 85/* IRQ stack memory (calculated at run-time) */ 86.globl IRQ_STACK_START 87IRQ_STACK_START: 88 .word 0x0badc0de 89 90/* IRQ stack memory (calculated at run-time) */ 91.globl FIQ_STACK_START 92FIQ_STACK_START: 93 .word 0x0badc0de 94#endif 95 96/* IRQ stack memory (calculated at run-time) + 8 bytes */ 97.globl IRQ_STACK_START_IN 98IRQ_STACK_START_IN: 99 .word 0x0badc0de 100 101.globl _datarel_start_ofs 102_datarel_start_ofs: 103 .word __datarel_start - _start 104 105.globl _datarelrolocal_start_ofs 106_datarelrolocal_start_ofs: 107 .word __datarelrolocal_start - _start 108 109.globl _datarellocal_start_ofs 110_datarellocal_start_ofs: 111 .word __datarellocal_start - _start 112 113.globl _datarelro_start_ofs 114_datarelro_start_ofs: 115 .word __datarelro_start - _start 116 117.globl _got_start_ofs 118_got_start_ofs: 119 .word __got_start - _start 120 121.globl _got_end_Ofs 122_got_end_ofs: 123 .word __got_end - _start 124 125/* 126 * the actual reset code 127 */ 128 129reset: 130 /* 131 * set the cpu to SVC32 mode 132 */ 133 mrs r0, cpsr 134 bic r0, r0, #0x1f 135 orr r0, r0, #0xd3 136 msr cpsr,r0 137 138#if (CONFIG_OMAP34XX) 139 /* Copy vectors to mask ROM indirect addr */ 140 adr r0, _start @ r0 <- current position of code 141 add r0, r0, #4 @ skip reset vector 142 mov r2, #64 @ r2 <- size to copy 143 add r2, r0, r2 @ r2 <- source end address 144 mov r1, #SRAM_OFFSET0 @ build vect addr 145 mov r3, #SRAM_OFFSET1 146 add r1, r1, r3 147 mov r3, #SRAM_OFFSET2 148 add r1, r1, r3 149next: 150 ldmia r0!, {r3 - r10} @ copy from source address [r0] 151 stmia r1!, {r3 - r10} @ copy to target address [r1] 152 cmp r0, r2 @ until source end address [r2] 153 bne next @ loop until equal */ 154#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 155 /* No need to copy/exec the clock code - DPLL adjust already done 156 * in NAND/oneNAND Boot. 157 */ 158 bl cpy_clk_code @ put dpll adjust code behind vectors 159#endif /* NAND Boot */ 160#endif 161 /* the mask ROM code should have PLL and others stable */ 162#ifndef CONFIG_SKIP_LOWLEVEL_INIT 163 bl cpu_init_crit 164#endif 165 166/* Set stackpointer in internal RAM to call board_init_f */ 167call_board_init_f: 168 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 169 ldr r0,=0x00000000 170 bl board_init_f 171 172/*------------------------------------------------------------------------------*/ 173 174/* 175 * void relocate_code (addr_sp, gd, addr_moni) 176 * 177 * This "function" does not return, instead it continues in RAM 178 * after relocating the monitor code. 179 * 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 mov r7, r2 /* save addr of destination */ 187 188 /* Set up the stack */ 189stack_setup: 190 mov sp, r4 191 192 adr r0, _start 193 ldr r2, _TEXT_BASE 194 ldr r3, _bss_start_ofs 195 add r2, r0, r3 /* r2 <- source end address */ 196 cmp r0, r6 197#ifndef CONFIG_PRELOADER 198 beq jump_2_ram 199#endif 200 201copy_loop: 202 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 203 stmia r6!, {r9-r10} /* copy to target address [r1] */ 204 cmp r0, r2 /* until source end address [r2] */ 205 blo copy_loop 206 207#ifndef CONFIG_PRELOADER 208 /* 209 * fix .rel.dyn relocations 210 */ 211 ldr r0, _TEXT_BASE /* r0 <- Text base */ 212 sub r9, r7, r0 /* r9 <- relocation offset */ 213 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 214 add r10, r10, r0 /* r10 <- sym table in FLASH */ 215 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 216 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 217 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 218 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 219fixloop: 220 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 221 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 222 ldr r1, [r2, #4] 223 and r8, r1, #0xff 224 cmp r8, #23 /* relative fixup? */ 225 beq fixrel 226 cmp r8, #2 /* absolute fixup? */ 227 beq fixabs 228 /* ignore unknown type of fixup */ 229 b fixnext 230fixabs: 231 /* absolute fix: set location to (offset) symbol value */ 232 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 233 add r1, r10, r1 /* r1 <- address of symbol in table */ 234 ldr r1, [r1, #4] /* r1 <- symbol value */ 235 add r1, r9 /* r1 <- relocated sym addr */ 236 b fixnext 237fixrel: 238 /* relative fix: increase location by offset */ 239 ldr r1, [r0] 240 add r1, r1, r9 241fixnext: 242 str r1, [r0] 243 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 244 cmp r2, r3 245 blo fixloop 246 247clear_bss: 248 ldr r0, _bss_start_ofs 249 ldr r1, _bss_end_ofs 250 ldr r3, _TEXT_BASE /* Text base */ 251 mov r4, r7 /* reloc addr */ 252 add r0, r0, r4 253 add r1, r1, r4 254 mov r2, #0x00000000 /* clear */ 255 256clbss_l:str r2, [r0] /* clear loop... */ 257 add r0, r0, #4 258 cmp r0, r1 259 bne clbss_l 260#endif /* #ifndef CONFIG_PRELOADER */ 261 262/* 263 * We are done. Do not return, instead branch to second part of board 264 * initialization, now running from RAM. 265 */ 266jump_2_ram: 267 ldr r0, _board_init_r_ofs 268 adr r1, _start 269 add lr, r0, r1 270 add lr, lr, r9 271 /* setup parameters for board_init_r */ 272 mov r0, r5 /* gd_t */ 273 mov r1, r7 /* dest_addr */ 274 /* jump to it ... */ 275 mov pc, lr 276 277_board_init_r_ofs: 278 .word board_init_r - _start 279 280_rel_dyn_start_ofs: 281 .word __rel_dyn_start - _start 282_rel_dyn_end_ofs: 283 .word __rel_dyn_end - _start 284_dynsym_start_ofs: 285 .word __dynsym_start - _start 286 287/************************************************************************* 288 * 289 * CPU_init_critical registers 290 * 291 * setup important registers 292 * setup memory timing 293 * 294 *************************************************************************/ 295cpu_init_crit: 296 /* 297 * Invalidate L1 I/D 298 */ 299 mov r0, #0 @ set up for MCR 300 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 301 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 302 303 /* 304 * disable MMU stuff and caches 305 */ 306 mrc p15, 0, r0, c1, c0, 0 307 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 308 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 309 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 310 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB 311 mcr p15, 0, r0, c1, c0, 0 312 313 /* 314 * Jump to board specific initialization... 315 * The Mask ROM will have already initialized 316 * basic memory. Go here to bump up clock rate and handle 317 * wake up conditions. 318 */ 319 mov ip, lr @ persevere link reg across call 320 bl lowlevel_init @ go setup pll,mux,memory 321 mov lr, ip @ restore link 322 mov pc, lr @ back to my caller 323/* 324 ************************************************************************* 325 * 326 * Interrupt handling 327 * 328 ************************************************************************* 329 */ 330@ 331@ IRQ stack frame. 332@ 333#define S_FRAME_SIZE 72 334 335#define S_OLD_R0 68 336#define S_PSR 64 337#define S_PC 60 338#define S_LR 56 339#define S_SP 52 340 341#define S_IP 48 342#define S_FP 44 343#define S_R10 40 344#define S_R9 36 345#define S_R8 32 346#define S_R7 28 347#define S_R6 24 348#define S_R5 20 349#define S_R4 16 350#define S_R3 12 351#define S_R2 8 352#define S_R1 4 353#define S_R0 0 354 355#define MODE_SVC 0x13 356#define I_BIT 0x80 357 358/* 359 * use bad_save_user_regs for abort/prefetch/undef/swi ... 360 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 361 */ 362 363 .macro bad_save_user_regs 364 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 365 @ user stack 366 stmia sp, {r0 - r12} @ Save user registers (now in 367 @ svc mode) r0-r12 368 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 369 @ stack 370 ldmia r2, {r2 - r3} @ get values for "aborted" pc 371 @ and cpsr (into parm regs) 372 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 373 374 add r5, sp, #S_SP 375 mov r1, lr 376 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 377 mov r0, sp @ save current stack into r0 378 @ (param register) 379 .endm 380 381 .macro irq_save_user_regs 382 sub sp, sp, #S_FRAME_SIZE 383 stmia sp, {r0 - r12} @ Calling r0-r12 384 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 385 @ a reserved stack spot would 386 @ be good. 387 stmdb r8, {sp, lr}^ @ Calling SP, LR 388 str lr, [r8, #0] @ Save calling PC 389 mrs r6, spsr 390 str r6, [r8, #4] @ Save CPSR 391 str r0, [r8, #8] @ Save OLD_R0 392 mov r0, sp 393 .endm 394 395 .macro irq_restore_user_regs 396 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 397 mov r0, r0 398 ldr lr, [sp, #S_PC] @ Get PC 399 add sp, sp, #S_FRAME_SIZE 400 subs pc, lr, #4 @ return & move spsr_svc into 401 @ cpsr 402 .endm 403 404 .macro get_bad_stack 405 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 406 @ in banked mode) 407 408 str lr, [r13] @ save caller lr in position 0 409 @ of saved stack 410 mrs lr, spsr @ get the spsr 411 str lr, [r13, #4] @ save spsr in position 1 of 412 @ saved stack 413 414 mov r13, #MODE_SVC @ prepare SVC-Mode 415 @ msr spsr_c, r13 416 msr spsr, r13 @ switch modes, make sure 417 @ moves will execute 418 mov lr, pc @ capture return pc 419 movs pc, lr @ jump to next instruction & 420 @ switch modes. 421 .endm 422 423 .macro get_bad_stack_swi 424 sub r13, r13, #4 @ space on current stack for 425 @ scratch reg. 426 str r0, [r13] @ save R0's value. 427 ldr r0, IRQ_STACK_START_IN @ get data regions start 428 @ spots for abort stack 429 str lr, [r0] @ save caller lr in position 0 430 @ of saved stack 431 mrs r0, spsr @ get the spsr 432 str lr, [r0, #4] @ save spsr in position 1 of 433 @ saved stack 434 ldr r0, [r13] @ restore r0 435 add r13, r13, #4 @ pop stack entry 436 .endm 437 438 .macro get_irq_stack @ setup IRQ stack 439 ldr sp, IRQ_STACK_START 440 .endm 441 442 .macro get_fiq_stack @ setup FIQ stack 443 ldr sp, FIQ_STACK_START 444 .endm 445 446/* 447 * exception handlers 448 */ 449 .align 5 450undefined_instruction: 451 get_bad_stack 452 bad_save_user_regs 453 bl do_undefined_instruction 454 455 .align 5 456software_interrupt: 457 get_bad_stack_swi 458 bad_save_user_regs 459 bl do_software_interrupt 460 461 .align 5 462prefetch_abort: 463 get_bad_stack 464 bad_save_user_regs 465 bl do_prefetch_abort 466 467 .align 5 468data_abort: 469 get_bad_stack 470 bad_save_user_regs 471 bl do_data_abort 472 473 .align 5 474not_used: 475 get_bad_stack 476 bad_save_user_regs 477 bl do_not_used 478 479#ifdef CONFIG_USE_IRQ 480 481 .align 5 482irq: 483 get_irq_stack 484 irq_save_user_regs 485 bl do_irq 486 irq_restore_user_regs 487 488 .align 5 489fiq: 490 get_fiq_stack 491 /* someone ought to write a more effective fiq_save_user_regs */ 492 irq_save_user_regs 493 bl do_fiq 494 irq_restore_user_regs 495 496#else 497 498 .align 5 499irq: 500 get_bad_stack 501 bad_save_user_regs 502 bl do_irq 503 504 .align 5 505fiq: 506 get_bad_stack 507 bad_save_user_regs 508 bl do_fiq 509 510#endif 511