1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35 36.globl _start 37_start: b reset 38 ldr pc, _undefined_instruction 39 ldr pc, _software_interrupt 40 ldr pc, _prefetch_abort 41 ldr pc, _data_abort 42 ldr pc, _not_used 43 ldr pc, _irq 44 ldr pc, _fiq 45 46_undefined_instruction: .word undefined_instruction 47_software_interrupt: .word software_interrupt 48_prefetch_abort: .word prefetch_abort 49_data_abort: .word data_abort 50_not_used: .word not_used 51_irq: .word irq 52_fiq: .word fiq 53_pad: .word 0x12345678 /* now 16*4=64 */ 54.global _end_vect 55_end_vect: 56 57 .balignl 16,0xdeadbeef 58/************************************************************************* 59 * 60 * Startup Code (reset vector) 61 * 62 * do important init only if we don't start from memory! 63 * setup Memory and board specific bits prior to relocation. 64 * relocate armboot to ram 65 * setup stack 66 * 67 *************************************************************************/ 68 69.globl _TEXT_BASE 70_TEXT_BASE: 71 .word CONFIG_SYS_TEXT_BASE 72 73/* 74 * These are defined in the board-specific linker script. 75 */ 76.globl _bss_start_ofs 77_bss_start_ofs: 78 .word __bss_start - _start 79 80.globl _bss_end_ofs 81_bss_end_ofs: 82 .word _end - _start 83 84#ifdef CONFIG_USE_IRQ 85/* IRQ stack memory (calculated at run-time) */ 86.globl IRQ_STACK_START 87IRQ_STACK_START: 88 .word 0x0badc0de 89 90/* IRQ stack memory (calculated at run-time) */ 91.globl FIQ_STACK_START 92FIQ_STACK_START: 93 .word 0x0badc0de 94#endif 95 96/* IRQ stack memory (calculated at run-time) + 8 bytes */ 97.globl IRQ_STACK_START_IN 98IRQ_STACK_START_IN: 99 .word 0x0badc0de 100 101/* 102 * the actual reset code 103 */ 104 105reset: 106 /* 107 * set the cpu to SVC32 mode 108 */ 109 mrs r0, cpsr 110 bic r0, r0, #0x1f 111 orr r0, r0, #0xd3 112 msr cpsr,r0 113 114#if (CONFIG_OMAP34XX) 115 /* Copy vectors to mask ROM indirect addr */ 116 adr r0, _start @ r0 <- current position of code 117 add r0, r0, #4 @ skip reset vector 118 mov r2, #64 @ r2 <- size to copy 119 add r2, r0, r2 @ r2 <- source end address 120 mov r1, #SRAM_OFFSET0 @ build vect addr 121 mov r3, #SRAM_OFFSET1 122 add r1, r1, r3 123 mov r3, #SRAM_OFFSET2 124 add r1, r1, r3 125next: 126 ldmia r0!, {r3 - r10} @ copy from source address [r0] 127 stmia r1!, {r3 - r10} @ copy to target address [r1] 128 cmp r0, r2 @ until source end address [r2] 129 bne next @ loop until equal */ 130#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 131 /* No need to copy/exec the clock code - DPLL adjust already done 132 * in NAND/oneNAND Boot. 133 */ 134 bl cpy_clk_code @ put dpll adjust code behind vectors 135#endif /* NAND Boot */ 136#endif 137 /* the mask ROM code should have PLL and others stable */ 138#ifndef CONFIG_SKIP_LOWLEVEL_INIT 139 bl cpu_init_crit 140#endif 141 142/* Set stackpointer in internal RAM to call board_init_f */ 143call_board_init_f: 144 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 145 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 146 ldr r0,=0x00000000 147 bl board_init_f 148 149/*------------------------------------------------------------------------------*/ 150 151/* 152 * void relocate_code (addr_sp, gd, addr_moni) 153 * 154 * This "function" does not return, instead it continues in RAM 155 * after relocating the monitor code. 156 * 157 */ 158 .globl relocate_code 159relocate_code: 160 mov r4, r0 /* save addr_sp */ 161 mov r5, r1 /* save addr of gd */ 162 mov r6, r2 /* save addr of destination */ 163 164 /* Set up the stack */ 165stack_setup: 166 mov sp, r4 167 168 adr r0, _start 169#ifndef CONFIG_PRELOADER 170 cmp r0, r6 171 beq clear_bss /* skip relocation */ 172#endif 173 mov r1, r6 /* r1 <- scratch for copy_loop */ 174 ldr r2, _TEXT_BASE 175 ldr r3, _bss_start_ofs 176 add r2, r0, r3 /* r2 <- source end address */ 177 178copy_loop: 179 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 180 stmia r1!, {r9-r10} /* copy to target address [r1] */ 181 cmp r0, r2 /* until source end address [r2] */ 182 blo copy_loop 183 184#ifndef CONFIG_PRELOADER 185 /* 186 * fix .rel.dyn relocations 187 */ 188 ldr r0, _TEXT_BASE /* r0 <- Text base */ 189 sub r9, r6, r0 /* r9 <- relocation offset */ 190 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 191 add r10, r10, r0 /* r10 <- sym table in FLASH */ 192 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 193 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 194 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 195 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 196fixloop: 197 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 198 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 199 ldr r1, [r2, #4] 200 and r7, r1, #0xff 201 cmp r7, #23 /* relative fixup? */ 202 beq fixrel 203 cmp r7, #2 /* absolute fixup? */ 204 beq fixabs 205 /* ignore unknown type of fixup */ 206 b fixnext 207fixabs: 208 /* absolute fix: set location to (offset) symbol value */ 209 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 210 add r1, r10, r1 /* r1 <- address of symbol in table */ 211 ldr r1, [r1, #4] /* r1 <- symbol value */ 212 add r1, r1, r9 /* r1 <- relocated sym addr */ 213 b fixnext 214fixrel: 215 /* relative fix: increase location by offset */ 216 ldr r1, [r0] 217 add r1, r1, r9 218fixnext: 219 str r1, [r0] 220 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 221 cmp r2, r3 222 blo fixloop 223 224clear_bss: 225 ldr r0, _bss_start_ofs 226 ldr r1, _bss_end_ofs 227 ldr r3, _TEXT_BASE /* Text base */ 228 mov r4, r6 /* reloc addr */ 229 add r0, r0, r4 230 add r1, r1, r4 231 mov r2, #0x00000000 /* clear */ 232 233clbss_l:str r2, [r0] /* clear loop... */ 234 add r0, r0, #4 235 cmp r0, r1 236 bne clbss_l 237#endif /* #ifndef CONFIG_PRELOADER */ 238 239/* 240 * We are done. Do not return, instead branch to second part of board 241 * initialization, now running from RAM. 242 */ 243jump_2_ram: 244 ldr r0, _board_init_r_ofs 245 adr r1, _start 246 add lr, r0, r1 247 add lr, lr, r9 248 /* setup parameters for board_init_r */ 249 mov r0, r5 /* gd_t */ 250 mov r1, r6 /* dest_addr */ 251 /* jump to it ... */ 252 mov pc, lr 253 254_board_init_r_ofs: 255 .word board_init_r - _start 256 257_rel_dyn_start_ofs: 258 .word __rel_dyn_start - _start 259_rel_dyn_end_ofs: 260 .word __rel_dyn_end - _start 261_dynsym_start_ofs: 262 .word __dynsym_start - _start 263 264/************************************************************************* 265 * 266 * CPU_init_critical registers 267 * 268 * setup important registers 269 * setup memory timing 270 * 271 *************************************************************************/ 272cpu_init_crit: 273 /* 274 * Invalidate L1 I/D 275 */ 276 mov r0, #0 @ set up for MCR 277 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 278 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 279 280 /* 281 * disable MMU stuff and caches 282 */ 283 mrc p15, 0, r0, c1, c0, 0 284 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 285 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 286 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 287 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB 288 mcr p15, 0, r0, c1, c0, 0 289 290 /* 291 * Jump to board specific initialization... 292 * The Mask ROM will have already initialized 293 * basic memory. Go here to bump up clock rate and handle 294 * wake up conditions. 295 */ 296 mov ip, lr @ persevere link reg across call 297 bl lowlevel_init @ go setup pll,mux,memory 298 mov lr, ip @ restore link 299 mov pc, lr @ back to my caller 300/* 301 ************************************************************************* 302 * 303 * Interrupt handling 304 * 305 ************************************************************************* 306 */ 307@ 308@ IRQ stack frame. 309@ 310#define S_FRAME_SIZE 72 311 312#define S_OLD_R0 68 313#define S_PSR 64 314#define S_PC 60 315#define S_LR 56 316#define S_SP 52 317 318#define S_IP 48 319#define S_FP 44 320#define S_R10 40 321#define S_R9 36 322#define S_R8 32 323#define S_R7 28 324#define S_R6 24 325#define S_R5 20 326#define S_R4 16 327#define S_R3 12 328#define S_R2 8 329#define S_R1 4 330#define S_R0 0 331 332#define MODE_SVC 0x13 333#define I_BIT 0x80 334 335/* 336 * use bad_save_user_regs for abort/prefetch/undef/swi ... 337 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 338 */ 339 340 .macro bad_save_user_regs 341 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 342 @ user stack 343 stmia sp, {r0 - r12} @ Save user registers (now in 344 @ svc mode) r0-r12 345 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 346 @ stack 347 ldmia r2, {r2 - r3} @ get values for "aborted" pc 348 @ and cpsr (into parm regs) 349 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 350 351 add r5, sp, #S_SP 352 mov r1, lr 353 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 354 mov r0, sp @ save current stack into r0 355 @ (param register) 356 .endm 357 358 .macro irq_save_user_regs 359 sub sp, sp, #S_FRAME_SIZE 360 stmia sp, {r0 - r12} @ Calling r0-r12 361 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 362 @ a reserved stack spot would 363 @ be good. 364 stmdb r8, {sp, lr}^ @ Calling SP, LR 365 str lr, [r8, #0] @ Save calling PC 366 mrs r6, spsr 367 str r6, [r8, #4] @ Save CPSR 368 str r0, [r8, #8] @ Save OLD_R0 369 mov r0, sp 370 .endm 371 372 .macro irq_restore_user_regs 373 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 374 mov r0, r0 375 ldr lr, [sp, #S_PC] @ Get PC 376 add sp, sp, #S_FRAME_SIZE 377 subs pc, lr, #4 @ return & move spsr_svc into 378 @ cpsr 379 .endm 380 381 .macro get_bad_stack 382 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 383 @ in banked mode) 384 385 str lr, [r13] @ save caller lr in position 0 386 @ of saved stack 387 mrs lr, spsr @ get the spsr 388 str lr, [r13, #4] @ save spsr in position 1 of 389 @ saved stack 390 391 mov r13, #MODE_SVC @ prepare SVC-Mode 392 @ msr spsr_c, r13 393 msr spsr, r13 @ switch modes, make sure 394 @ moves will execute 395 mov lr, pc @ capture return pc 396 movs pc, lr @ jump to next instruction & 397 @ switch modes. 398 .endm 399 400 .macro get_bad_stack_swi 401 sub r13, r13, #4 @ space on current stack for 402 @ scratch reg. 403 str r0, [r13] @ save R0's value. 404 ldr r0, IRQ_STACK_START_IN @ get data regions start 405 @ spots for abort stack 406 str lr, [r0] @ save caller lr in position 0 407 @ of saved stack 408 mrs r0, spsr @ get the spsr 409 str lr, [r0, #4] @ save spsr in position 1 of 410 @ saved stack 411 ldr r0, [r13] @ restore r0 412 add r13, r13, #4 @ pop stack entry 413 .endm 414 415 .macro get_irq_stack @ setup IRQ stack 416 ldr sp, IRQ_STACK_START 417 .endm 418 419 .macro get_fiq_stack @ setup FIQ stack 420 ldr sp, FIQ_STACK_START 421 .endm 422 423/* 424 * exception handlers 425 */ 426 .align 5 427undefined_instruction: 428 get_bad_stack 429 bad_save_user_regs 430 bl do_undefined_instruction 431 432 .align 5 433software_interrupt: 434 get_bad_stack_swi 435 bad_save_user_regs 436 bl do_software_interrupt 437 438 .align 5 439prefetch_abort: 440 get_bad_stack 441 bad_save_user_regs 442 bl do_prefetch_abort 443 444 .align 5 445data_abort: 446 get_bad_stack 447 bad_save_user_regs 448 bl do_data_abort 449 450 .align 5 451not_used: 452 get_bad_stack 453 bad_save_user_regs 454 bl do_not_used 455 456#ifdef CONFIG_USE_IRQ 457 458 .align 5 459irq: 460 get_irq_stack 461 irq_save_user_regs 462 bl do_irq 463 irq_restore_user_regs 464 465 .align 5 466fiq: 467 get_fiq_stack 468 /* someone ought to write a more effective fiq_save_user_regs */ 469 irq_save_user_regs 470 bl do_fiq 471 irq_restore_user_regs 472 473#else 474 475 .align 5 476irq: 477 get_bad_stack 478 bad_save_user_regs 479 bl do_irq 480 481 .align 5 482fiq: 483 get_bad_stack 484 bad_save_user_regs 485 bl do_fiq 486 487#endif 488