1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c616a0dfSNishanth Menon /*
3c616a0dfSNishanth Menon * (C) Copyright 2015 Texas Insturments
4c616a0dfSNishanth Menon */
5c616a0dfSNishanth Menon
6c616a0dfSNishanth Menon /*
7c616a0dfSNishanth Menon * CP15 specific code
8c616a0dfSNishanth Menon */
9c616a0dfSNishanth Menon
10c616a0dfSNishanth Menon #include <common.h>
11c616a0dfSNishanth Menon #include <command.h>
12c616a0dfSNishanth Menon #include <asm/system.h>
13c616a0dfSNishanth Menon #include <asm/cache.h>
14c616a0dfSNishanth Menon #include <asm/armv7.h>
15c616a0dfSNishanth Menon #include <linux/compiler.h>
16c616a0dfSNishanth Menon
v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)17c616a0dfSNishanth Menon void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
18c616a0dfSNishanth Menon u32 cpu_rev_comb, u32 cpu_variant,
19c616a0dfSNishanth Menon u32 cpu_rev)
20c616a0dfSNishanth Menon {
21c616a0dfSNishanth Menon asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
22c616a0dfSNishanth Menon }
23b45c48a7SNishanth Menon
v7_arch_cp15_set_acr(u32 acr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)24b45c48a7SNishanth Menon void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
25b45c48a7SNishanth Menon u32 cpu_variant, u32 cpu_rev)
26b45c48a7SNishanth Menon {
27b45c48a7SNishanth Menon asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
28b45c48a7SNishanth Menon }
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