xref: /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c (revision 989ce049997daefc25c15e1d5bf5307cdca25abb)
1*989ce049SDarwin Rambo /*
2*989ce049SDarwin Rambo  * Copyright 2013 Broadcom Corporation.
3*989ce049SDarwin Rambo  *
4*989ce049SDarwin Rambo  * SPDX-License-Identifier:      GPL-2.0+
5*989ce049SDarwin Rambo  */
6*989ce049SDarwin Rambo 
7*989ce049SDarwin Rambo #include <common.h>
8*989ce049SDarwin Rambo #include <asm/io.h>
9*989ce049SDarwin Rambo #include <asm/errno.h>
10*989ce049SDarwin Rambo #include <asm/arch/sysmap.h>
11*989ce049SDarwin Rambo #include <asm/kona-common/clk.h>
12*989ce049SDarwin Rambo #include "clk-core.h"
13*989ce049SDarwin Rambo 
14*989ce049SDarwin Rambo /* Enable appropriate clocks for a BSC/I2C port */
15*989ce049SDarwin Rambo int clk_bsc_enable(void *base)
16*989ce049SDarwin Rambo {
17*989ce049SDarwin Rambo 	int ret;
18*989ce049SDarwin Rambo 	char *bscstr, *apbstr;
19*989ce049SDarwin Rambo 
20*989ce049SDarwin Rambo 	switch ((u32) base) {
21*989ce049SDarwin Rambo 	case PMU_BSC_BASE_ADDR:
22*989ce049SDarwin Rambo 		/* PMU clock is always enabled */
23*989ce049SDarwin Rambo 		return 0;
24*989ce049SDarwin Rambo 	case BSC1_BASE_ADDR:
25*989ce049SDarwin Rambo 		bscstr = "bsc1_clk";
26*989ce049SDarwin Rambo 		apbstr = "bsc1_apb_clk";
27*989ce049SDarwin Rambo 		break;
28*989ce049SDarwin Rambo 	case BSC2_BASE_ADDR:
29*989ce049SDarwin Rambo 		bscstr = "bsc2_clk";
30*989ce049SDarwin Rambo 		apbstr = "bsc2_apb_clk";
31*989ce049SDarwin Rambo 		break;
32*989ce049SDarwin Rambo 	case BSC3_BASE_ADDR:
33*989ce049SDarwin Rambo 		bscstr = "bsc3_clk";
34*989ce049SDarwin Rambo 		apbstr = "bsc3_apb_clk";
35*989ce049SDarwin Rambo 		break;
36*989ce049SDarwin Rambo 	default:
37*989ce049SDarwin Rambo 		printf("%s: base 0x%p not found\n", __func__, base);
38*989ce049SDarwin Rambo 		return -EINVAL;
39*989ce049SDarwin Rambo 	}
40*989ce049SDarwin Rambo 
41*989ce049SDarwin Rambo 	/* Note that the bus clock must be enabled first */
42*989ce049SDarwin Rambo 
43*989ce049SDarwin Rambo 	ret = clk_get_and_enable(apbstr);
44*989ce049SDarwin Rambo 	if (ret)
45*989ce049SDarwin Rambo 		return ret;
46*989ce049SDarwin Rambo 
47*989ce049SDarwin Rambo 	ret = clk_get_and_enable(bscstr);
48*989ce049SDarwin Rambo 	if (ret)
49*989ce049SDarwin Rambo 		return ret;
50*989ce049SDarwin Rambo 
51*989ce049SDarwin Rambo 	return 0;
52*989ce049SDarwin Rambo }
53