1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <version.h> 37 38/* 39 ************************************************************************* 40 * 41 * Jump vector table as in table 3.1 in [1] 42 * 43 ************************************************************************* 44 */ 45 46 47.globl _start 48_start: 49 b reset 50 ldr pc, _undefined_instruction 51 ldr pc, _software_interrupt 52 ldr pc, _prefetch_abort 53 ldr pc, _data_abort 54 ldr pc, _not_used 55 ldr pc, _irq 56 ldr pc, _fiq 57 58_undefined_instruction: 59 .word undefined_instruction 60_software_interrupt: 61 .word software_interrupt 62_prefetch_abort: 63 .word prefetch_abort 64_data_abort: 65 .word data_abort 66_not_used: 67 .word not_used 68_irq: 69 .word irq 70_fiq: 71 .word fiq 72 73 .balignl 16,0xdeadbeef 74 75_vectors_end: 76 77/* 78 ************************************************************************* 79 * 80 * Startup Code (reset vector) 81 * 82 * do important init only if we don't start from memory! 83 * setup Memory and board specific bits prior to relocation. 84 * relocate armboot to ram 85 * setup stack 86 * 87 ************************************************************************* 88 */ 89 90.globl _TEXT_BASE 91_TEXT_BASE: 92#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 93 .word CONFIG_SPL_TEXT_BASE 94#else 95 .word CONFIG_SYS_TEXT_BASE 96#endif 97 98/* 99 * These are defined in the board-specific linker script. 100 * Subtracting _start from them lets the linker put their 101 * relative position in the executable instead of leaving 102 * them null. 103 */ 104.globl _bss_start_ofs 105_bss_start_ofs: 106 .word __bss_start - _start 107 108.globl _bss_end_ofs 109_bss_end_ofs: 110 .word __bss_end - _start 111 112.globl _end_ofs 113_end_ofs: 114 .word _end - _start 115 116#ifdef CONFIG_USE_IRQ 117/* IRQ stack memory (calculated at run-time) */ 118.globl IRQ_STACK_START 119IRQ_STACK_START: 120 .word 0x0badc0de 121 122/* IRQ stack memory (calculated at run-time) */ 123.globl FIQ_STACK_START 124FIQ_STACK_START: 125 .word 0x0badc0de 126#endif 127 128/* IRQ stack memory (calculated at run-time) + 8 bytes */ 129.globl IRQ_STACK_START_IN 130IRQ_STACK_START_IN: 131 .word 0x0badc0de 132 133/* 134 * the actual reset code 135 */ 136 137reset: 138 /* 139 * set the cpu to SVC32 mode 140 */ 141 mrs r0,cpsr 142 bic r0,r0,#0x1f 143 orr r0,r0,#0xd3 144 msr cpsr,r0 145 146 /* 147 * we do sys-critical inits only at reboot, 148 * not when booting from ram! 149 */ 150#ifndef CONFIG_SKIP_LOWLEVEL_INIT 151 bl cpu_init_crit 152#endif 153 154 bl _main 155 156/*------------------------------------------------------------------------------*/ 157 158/* 159 * void relocate_code (addr_sp, gd, addr_moni) 160 * 161 * This "function" does not return, instead it continues in RAM 162 * after relocating the monitor code. 163 * 164 */ 165 .globl relocate_code 166relocate_code: 167 mov r4, r0 /* save addr_sp */ 168 mov r5, r1 /* save addr of gd */ 169 mov r6, r2 /* save addr of destination */ 170 171 adr r0, _start 172 cmp r0, r6 173 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 174 beq relocate_done /* skip relocation */ 175 mov r1, r6 /* r1 <- scratch for copy_loop */ 176 ldr r3, _bss_start_ofs 177 add r2, r0, r3 /* r2 <- source end address */ 178 179copy_loop: 180 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 181 stmia r1!, {r9-r10} /* copy to target address [r1] */ 182 cmp r0, r2 /* until source end address [r2] */ 183 blo copy_loop 184 185#ifndef CONFIG_SPL_BUILD 186 /* 187 * fix .rel.dyn relocations 188 */ 189 ldr r0, _TEXT_BASE /* r0 <- Text base */ 190 sub r9, r6, r0 /* r9 <- relocation offset */ 191 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 192 add r10, r10, r0 /* r10 <- sym table in FLASH */ 193 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 194 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 195 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 196 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 197fixloop: 198 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 199 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 200 ldr r1, [r2, #4] 201 and r7, r1, #0xff 202 cmp r7, #23 /* relative fixup? */ 203 beq fixrel 204 cmp r7, #2 /* absolute fixup? */ 205 beq fixabs 206 /* ignore unknown type of fixup */ 207 b fixnext 208fixabs: 209 /* absolute fix: set location to (offset) symbol value */ 210 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 211 add r1, r10, r1 /* r1 <- address of symbol in table */ 212 ldr r1, [r1, #4] /* r1 <- symbol value */ 213 add r1, r1, r9 /* r1 <- relocated sym addr */ 214 b fixnext 215fixrel: 216 /* relative fix: increase location by offset */ 217 ldr r1, [r0] 218 add r1, r1, r9 219fixnext: 220 str r1, [r0] 221 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 222 cmp r2, r3 223 blo fixloop 224#endif 225 226relocate_done: 227 228 mov pc, lr 229 230_rel_dyn_start_ofs: 231 .word __rel_dyn_start - _start 232_rel_dyn_end_ofs: 233 .word __rel_dyn_end - _start 234_dynsym_start_ofs: 235 .word __dynsym_start - _start 236 237 .globl c_runtime_cpu_setup 238c_runtime_cpu_setup: 239 240 mov pc, lr 241 242/* 243 ************************************************************************* 244 * 245 * CPU_init_critical registers 246 * 247 * setup important registers 248 * setup memory timing 249 * 250 ************************************************************************* 251 */ 252 253 254#ifndef CONFIG_SKIP_LOWLEVEL_INIT 255cpu_init_crit: 256 /* 257 * flush v4 I/D caches 258 */ 259 mov r0, #0 260 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ 261 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ 262 263 /* 264 * disable MMU stuff and caches 265 */ 266 mrc p15, 0, r0, c1, c0, 0 267 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 268 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 269 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 270 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 271 mcr p15, 0, r0, c1, c0, 0 272 273 /* 274 * Go setup Memory and board specific bits prior to relocation. 275 */ 276 mov ip, lr /* perserve link reg across call */ 277 bl lowlevel_init /* go setup memory */ 278 mov lr, ip /* restore link */ 279 mov pc, lr /* back to my caller */ 280#endif 281/* 282 ************************************************************************* 283 * 284 * Interrupt handling 285 * 286 ************************************************************************* 287 */ 288 289@ 290@ IRQ stack frame. 291@ 292#define S_FRAME_SIZE 72 293 294#define S_OLD_R0 68 295#define S_PSR 64 296#define S_PC 60 297#define S_LR 56 298#define S_SP 52 299 300#define S_IP 48 301#define S_FP 44 302#define S_R10 40 303#define S_R9 36 304#define S_R8 32 305#define S_R7 28 306#define S_R6 24 307#define S_R5 20 308#define S_R4 16 309#define S_R3 12 310#define S_R2 8 311#define S_R1 4 312#define S_R0 0 313 314#define MODE_SVC 0x13 315#define I_BIT 0x80 316 317/* 318 * use bad_save_user_regs for abort/prefetch/undef/swi ... 319 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 320 */ 321 322 .macro bad_save_user_regs 323 @ carve out a frame on current user stack 324 sub sp, sp, #S_FRAME_SIZE 325 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 326 327 ldr r2, IRQ_STACK_START_IN 328 @ get values for "aborted" pc and cpsr (into parm regs) 329 ldmia r2, {r2 - r3} 330 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 331 add r5, sp, #S_SP 332 mov r1, lr 333 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 334 mov r0, sp @ save current stack into r0 (param register) 335 .endm 336 337 .macro irq_save_user_regs 338 sub sp, sp, #S_FRAME_SIZE 339 stmia sp, {r0 - r12} @ Calling r0-r12 340 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 341 add r8, sp, #S_PC 342 stmdb r8, {sp, lr}^ @ Calling SP, LR 343 str lr, [r8, #0] @ Save calling PC 344 mrs r6, spsr 345 str r6, [r8, #4] @ Save CPSR 346 str r0, [r8, #8] @ Save OLD_R0 347 mov r0, sp 348 .endm 349 350 .macro irq_restore_user_regs 351 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 352 mov r0, r0 353 ldr lr, [sp, #S_PC] @ Get PC 354 add sp, sp, #S_FRAME_SIZE 355 subs pc, lr, #4 @ return & move spsr_svc into cpsr 356 .endm 357 358 .macro get_bad_stack 359 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 360 361 str lr, [r13] @ save caller lr in position 0 of saved stack 362 mrs lr, spsr @ get the spsr 363 str lr, [r13, #4] @ save spsr in position 1 of saved stack 364 mov r13, #MODE_SVC @ prepare SVC-Mode 365 @ msr spsr_c, r13 366 msr spsr, r13 @ switch modes, make sure moves will execute 367 mov lr, pc @ capture return pc 368 movs pc, lr @ jump to next instruction & switch modes. 369 .endm 370 371 .macro get_irq_stack @ setup IRQ stack 372 ldr sp, IRQ_STACK_START 373 .endm 374 375 .macro get_fiq_stack @ setup FIQ stack 376 ldr sp, FIQ_STACK_START 377 .endm 378 379/* 380 * exception handlers 381 */ 382 .align 5 383undefined_instruction: 384 get_bad_stack 385 bad_save_user_regs 386 bl do_undefined_instruction 387 388 .align 5 389software_interrupt: 390 get_bad_stack 391 bad_save_user_regs 392 bl do_software_interrupt 393 394 .align 5 395prefetch_abort: 396 get_bad_stack 397 bad_save_user_regs 398 bl do_prefetch_abort 399 400 .align 5 401data_abort: 402 get_bad_stack 403 bad_save_user_regs 404 bl do_data_abort 405 406 .align 5 407not_used: 408 get_bad_stack 409 bad_save_user_regs 410 bl do_not_used 411 412#ifdef CONFIG_USE_IRQ 413 414 .align 5 415irq: 416 get_irq_stack 417 irq_save_user_regs 418 bl do_irq 419 irq_restore_user_regs 420 421 .align 5 422fiq: 423 get_fiq_stack 424 /* someone ought to write a more effiction fiq_save_user_regs */ 425 irq_save_user_regs 426 bl do_fiq 427 irq_restore_user_regs 428 429#else 430 431 .align 5 432irq: 433 get_bad_stack 434 bad_save_user_regs 435 bl do_irq 436 437 .align 5 438fiq: 439 get_bad_stack 440 bad_save_user_regs 441 bl do_fiq 442 443#endif 444 445# ifdef CONFIG_INTEGRATOR 446 447 /* Satisfied by general board level routine */ 448 449#else 450 451 .align 5 452.globl reset_cpu 453reset_cpu: 454 455 ldr r1, rstctl1 /* get clkm1 reset ctl */ 456 mov r3, #0x0 457 strh r3, [r1] /* clear it */ 458 mov r3, #0x8 459 strh r3, [r1] /* force dsp+arm reset */ 460_loop_forever: 461 b _loop_forever 462 463rstctl1: 464 .word 0xfffece10 465 466#endif /* #ifdef CONFIG_INTEGRATOR */ 467