1/* 2 * armboot - Startup Code for ARM920 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#include <asm-offsets.h> 28#include <common.h> 29#include <config.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b start_code 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50_undefined_instruction: .word undefined_instruction 51_software_interrupt: .word software_interrupt 52_prefetch_abort: .word prefetch_abort 53_data_abort: .word data_abort 54_not_used: .word not_used 55_irq: .word irq 56_fiq: .word fiq 57 58 .balignl 16,0xdeadbeef 59 60 61/* 62 ************************************************************************* 63 * 64 * Startup Code (called from the ARM reset exception vector) 65 * 66 * do important init only if we don't start from memory! 67 * relocate armboot to ram 68 * setup stack 69 * jump to second stage 70 * 71 ************************************************************************* 72 */ 73 74.globl _TEXT_BASE 75_TEXT_BASE: 76 .word CONFIG_SYS_TEXT_BASE 77 78/* 79 * These are defined in the board-specific linker script. 80 * Subtracting _start from them lets the linker put their 81 * relative position in the executable instead of leaving 82 * them null. 83 */ 84.globl _bss_start_ofs 85_bss_start_ofs: 86 .word __bss_start - _start 87 88.globl _bss_end_ofs 89_bss_end_ofs: 90 .word __bss_end__ - _start 91 92#ifdef CONFIG_USE_IRQ 93/* IRQ stack memory (calculated at run-time) */ 94.globl IRQ_STACK_START 95IRQ_STACK_START: 96 .word 0x0badc0de 97 98/* IRQ stack memory (calculated at run-time) */ 99.globl FIQ_STACK_START 100FIQ_STACK_START: 101 .word 0x0badc0de 102#endif 103 104/* IRQ stack memory (calculated at run-time) + 8 bytes */ 105.globl IRQ_STACK_START_IN 106IRQ_STACK_START_IN: 107 .word 0x0badc0de 108 109/* 110 * the actual start code 111 */ 112 113start_code: 114 /* 115 * set the cpu to SVC32 mode 116 */ 117 mrs r0, cpsr 118 bic r0, r0, #0x1f 119 orr r0, r0, #0xd3 120 msr cpsr, r0 121 122#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) 123 /* 124 * relocate exception table 125 */ 126 ldr r0, =_start 127 ldr r1, =0x0 128 mov r2, #16 129copyex: 130 subs r2, r2, #1 131 ldr r3, [r0], #4 132 str r3, [r1], #4 133 bne copyex 134#endif 135 136#ifdef CONFIG_S3C24X0 137 /* turn off the watchdog */ 138 139# if defined(CONFIG_S3C2400) 140# define pWTCON 0x15300000 141# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ 142# define CLKDIVN 0x14800014 /* clock divisor register */ 143#else 144# define pWTCON 0x53000000 145# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ 146# define INTSUBMSK 0x4A00001C 147# define CLKDIVN 0x4C000014 /* clock divisor register */ 148# endif 149 150 ldr r0, =pWTCON 151 mov r1, #0x0 152 str r1, [r0] 153 154 /* 155 * mask all IRQs by setting all bits in the INTMR - default 156 */ 157 mov r1, #0xffffffff 158 ldr r0, =INTMSK 159 str r1, [r0] 160# if defined(CONFIG_S3C2410) 161 ldr r1, =0x3ff 162 ldr r0, =INTSUBMSK 163 str r1, [r0] 164# endif 165 166 /* FCLK:HCLK:PCLK = 1:2:4 */ 167 /* default FCLK is 120 MHz ! */ 168 ldr r0, =CLKDIVN 169 mov r1, #3 170 str r1, [r0] 171#endif /* CONFIG_S3C24X0 */ 172 173 /* 174 * we do sys-critical inits only at reboot, 175 * not when booting from ram! 176 */ 177#ifndef CONFIG_SKIP_LOWLEVEL_INIT 178 bl cpu_init_crit 179#endif 180 181/* Set stackpointer in internal RAM to call board_init_f */ 182call_board_init_f: 183 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 184 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 185 ldr r0,=0x00000000 186 bl board_init_f 187 188/*------------------------------------------------------------------------------*/ 189 190/* 191 * void relocate_code (addr_sp, gd, addr_moni) 192 * 193 * This "function" does not return, instead it continues in RAM 194 * after relocating the monitor code. 195 * 196 */ 197 .globl relocate_code 198relocate_code: 199 mov r4, r0 /* save addr_sp */ 200 mov r5, r1 /* save addr of gd */ 201 mov r6, r2 /* save addr of destination */ 202 203 /* Set up the stack */ 204stack_setup: 205 mov sp, r4 206 207 adr r0, _start 208 cmp r0, r6 209 beq clear_bss /* skip relocation */ 210 mov r1, r6 /* r1 <- scratch for copy_loop */ 211 ldr r3, _bss_start_ofs 212 add r2, r0, r3 /* r2 <- source end address */ 213 214copy_loop: 215 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 216 stmia r1!, {r9-r10} /* copy to target address [r1] */ 217 cmp r0, r2 /* until source end address [r2] */ 218 blo copy_loop 219 220#ifndef CONFIG_PRELOADER 221 /* 222 * fix .rel.dyn relocations 223 */ 224 ldr r0, _TEXT_BASE /* r0 <- Text base */ 225 sub r9, r6, r0 /* r9 <- relocation offset */ 226 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 227 add r10, r10, r0 /* r10 <- sym table in FLASH */ 228 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 229 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 230 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 231 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 232fixloop: 233 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 234 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 235 ldr r1, [r2, #4] 236 and r7, r1, #0xff 237 cmp r7, #23 /* relative fixup? */ 238 beq fixrel 239 cmp r7, #2 /* absolute fixup? */ 240 beq fixabs 241 /* ignore unknown type of fixup */ 242 b fixnext 243fixabs: 244 /* absolute fix: set location to (offset) symbol value */ 245 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 246 add r1, r10, r1 /* r1 <- address of symbol in table */ 247 ldr r1, [r1, #4] /* r1 <- symbol value */ 248 add r1, r1, r9 /* r1 <- relocated sym addr */ 249 b fixnext 250fixrel: 251 /* relative fix: increase location by offset */ 252 ldr r1, [r0] 253 add r1, r1, r9 254fixnext: 255 str r1, [r0] 256 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 257 cmp r2, r3 258 blo fixloop 259#endif 260 261clear_bss: 262#ifndef CONFIG_PRELOADER 263 ldr r0, _bss_start_ofs 264 ldr r1, _bss_end_ofs 265 mov r4, r6 /* reloc addr */ 266 add r0, r0, r4 267 add r1, r1, r4 268 mov r2, #0x00000000 /* clear */ 269 270clbss_l:str r2, [r0] /* clear loop... */ 271 add r0, r0, #4 272 cmp r0, r1 273 bne clbss_l 274 275 bl coloured_LED_init 276 bl red_LED_on 277#endif 278 279/* 280 * We are done. Do not return, instead branch to second part of board 281 * initialization, now running from RAM. 282 */ 283#ifdef CONFIG_NAND_SPL 284 ldr r0, _nand_boot_ofs 285 mov pc, r0 286 287_nand_boot_ofs: 288 .word nand_boot 289#else 290 ldr r0, _board_init_r_ofs 291 adr r1, _start 292 add lr, r0, r1 293 add lr, lr, r9 294 /* setup parameters for board_init_r */ 295 mov r0, r5 /* gd_t */ 296 mov r1, r6 /* dest_addr */ 297 /* jump to it ... */ 298 mov pc, lr 299 300_board_init_r_ofs: 301 .word board_init_r - _start 302#endif 303 304_rel_dyn_start_ofs: 305 .word __rel_dyn_start - _start 306_rel_dyn_end_ofs: 307 .word __rel_dyn_end - _start 308_dynsym_start_ofs: 309 .word __dynsym_start - _start 310 311/* 312 ************************************************************************* 313 * 314 * CPU_init_critical registers 315 * 316 * setup important registers 317 * setup memory timing 318 * 319 ************************************************************************* 320 */ 321 322 323#ifndef CONFIG_SKIP_LOWLEVEL_INIT 324cpu_init_crit: 325 /* 326 * flush v4 I/D caches 327 */ 328 mov r0, #0 329 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 330 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 331 332 /* 333 * disable MMU stuff and caches 334 */ 335 mrc p15, 0, r0, c1, c0, 0 336 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 337 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 338 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 339 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 340 mcr p15, 0, r0, c1, c0, 0 341 342 /* 343 * before relocating, we have to setup RAM timing 344 * because memory timing is board-dependend, you will 345 * find a lowlevel_init.S in your board directory. 346 */ 347 mov ip, lr 348 349 bl lowlevel_init 350 351 mov lr, ip 352 mov pc, lr 353#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 354 355/* 356 ************************************************************************* 357 * 358 * Interrupt handling 359 * 360 ************************************************************************* 361 */ 362 363@ 364@ IRQ stack frame. 365@ 366#define S_FRAME_SIZE 72 367 368#define S_OLD_R0 68 369#define S_PSR 64 370#define S_PC 60 371#define S_LR 56 372#define S_SP 52 373 374#define S_IP 48 375#define S_FP 44 376#define S_R10 40 377#define S_R9 36 378#define S_R8 32 379#define S_R7 28 380#define S_R6 24 381#define S_R5 20 382#define S_R4 16 383#define S_R3 12 384#define S_R2 8 385#define S_R1 4 386#define S_R0 0 387 388#define MODE_SVC 0x13 389#define I_BIT 0x80 390 391/* 392 * use bad_save_user_regs for abort/prefetch/undef/swi ... 393 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 394 */ 395 396 .macro bad_save_user_regs 397 sub sp, sp, #S_FRAME_SIZE 398 stmia sp, {r0 - r12} @ Calling r0-r12 399 ldr r2, IRQ_STACK_START_IN 400 ldmia r2, {r2 - r3} @ get pc, cpsr 401 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 402 403 add r5, sp, #S_SP 404 mov r1, lr 405 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 406 mov r0, sp 407 .endm 408 409 .macro irq_save_user_regs 410 sub sp, sp, #S_FRAME_SIZE 411 stmia sp, {r0 - r12} @ Calling r0-r12 412 add r7, sp, #S_PC 413 stmdb r7, {sp, lr}^ @ Calling SP, LR 414 str lr, [r7, #0] @ Save calling PC 415 mrs r6, spsr 416 str r6, [r7, #4] @ Save CPSR 417 str r0, [r7, #8] @ Save OLD_R0 418 mov r0, sp 419 .endm 420 421 .macro irq_restore_user_regs 422 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 423 mov r0, r0 424 ldr lr, [sp, #S_PC] @ Get PC 425 add sp, sp, #S_FRAME_SIZE 426 /* return & move spsr_svc into cpsr */ 427 subs pc, lr, #4 428 .endm 429 430 .macro get_bad_stack 431 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 432 433 str lr, [r13] @ save caller lr / spsr 434 mrs lr, spsr 435 str lr, [r13, #4] 436 437 mov r13, #MODE_SVC @ prepare SVC-Mode 438 @ msr spsr_c, r13 439 msr spsr, r13 440 mov lr, pc 441 movs pc, lr 442 .endm 443 444 .macro get_irq_stack @ setup IRQ stack 445 ldr sp, IRQ_STACK_START 446 .endm 447 448 .macro get_fiq_stack @ setup FIQ stack 449 ldr sp, FIQ_STACK_START 450 .endm 451 452/* 453 * exception handlers 454 */ 455 .align 5 456undefined_instruction: 457 get_bad_stack 458 bad_save_user_regs 459 bl do_undefined_instruction 460 461 .align 5 462software_interrupt: 463 get_bad_stack 464 bad_save_user_regs 465 bl do_software_interrupt 466 467 .align 5 468prefetch_abort: 469 get_bad_stack 470 bad_save_user_regs 471 bl do_prefetch_abort 472 473 .align 5 474data_abort: 475 get_bad_stack 476 bad_save_user_regs 477 bl do_data_abort 478 479 .align 5 480not_used: 481 get_bad_stack 482 bad_save_user_regs 483 bl do_not_used 484 485#ifdef CONFIG_USE_IRQ 486 487 .align 5 488irq: 489 get_irq_stack 490 irq_save_user_regs 491 bl do_irq 492 irq_restore_user_regs 493 494 .align 5 495fiq: 496 get_fiq_stack 497 /* someone ought to write a more effiction fiq_save_user_regs */ 498 irq_save_user_regs 499 bl do_fiq 500 irq_restore_user_regs 501 502#else 503 504 .align 5 505irq: 506 get_bad_stack 507 bad_save_user_regs 508 bl do_irq 509 510 .align 5 511fiq: 512 get_bad_stack 513 bad_save_user_regs 514 bl do_fiq 515 516#endif 517