xref: /openbmc/u-boot/arch/arm/cpu/arm720t/start.S (revision 38dba0c2ff685e3f8276a236bd70eaa09c84ead5) 
1/*
2 *  armboot - Startup Code for ARM720 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gr�ger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Z�pke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <asm-offsets.h>
27#include <config.h>
28#include <version.h>
29#include <asm/hardware.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start: b	reset
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46#ifdef CONFIG_LPC2292
47	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
48#else
49	ldr	pc, _not_used
50#endif
51	ldr	pc, _irq
52	ldr	pc, _fiq
53
54_undefined_instruction: .word undefined_instruction
55_software_interrupt:	.word software_interrupt
56_prefetch_abort:	.word prefetch_abort
57_data_abort:		.word data_abort
58_not_used:		.word not_used
59_irq:			.word irq
60_fiq:			.word fiq
61
62	.balignl 16,0xdeadbeef
63
64
65/*
66 *************************************************************************
67 *
68 * Startup Code (reset vector)
69 *
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
72 * setup stack
73 * jump to second stage
74 *
75 *************************************************************************
76 */
77
78.globl _TEXT_BASE
79_TEXT_BASE:
80	.word	CONFIG_SYS_TEXT_BASE
81
82/*
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
86 * them null.
87 */
88.globl _bss_start_ofs
89_bss_start_ofs:
90	.word __bss_start - _start
91
92.globl _bss_end_ofs
93_bss_end_ofs:
94	.word _end - _start
95
96#ifdef CONFIG_USE_IRQ
97/* IRQ stack memory (calculated at run-time) */
98.globl IRQ_STACK_START
99IRQ_STACK_START:
100	.word	0x0badc0de
101
102/* IRQ stack memory (calculated at run-time) */
103.globl FIQ_STACK_START
104FIQ_STACK_START:
105	.word 0x0badc0de
106#endif
107
108/* IRQ stack memory (calculated at run-time) + 8 bytes */
109.globl IRQ_STACK_START_IN
110IRQ_STACK_START_IN:
111	.word	0x0badc0de
112
113/*
114 * the actual reset code
115 */
116
117reset:
118	/*
119	 * set the cpu to SVC32 mode
120	 */
121	mrs	r0,cpsr
122	bic	r0,r0,#0x1f
123	orr	r0,r0,#0xd3
124	msr	cpsr,r0
125
126	/*
127	 * we do sys-critical inits only at reboot,
128	 * not when booting from ram!
129	 */
130#ifndef CONFIG_SKIP_LOWLEVEL_INIT
131	bl	cpu_init_crit
132#endif
133
134#ifdef CONFIG_LPC2292
135	bl	lowlevel_init
136#endif
137
138/* Set stackpointer in internal RAM to call board_init_f */
139call_board_init_f:
140	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
141	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
142	ldr	r0,=0x00000000
143	bl	board_init_f
144
145/*------------------------------------------------------------------------------*/
146
147/*
148 * void relocate_code (addr_sp, gd, addr_moni)
149 *
150 * This "function" does not return, instead it continues in RAM
151 * after relocating the monitor code.
152 *
153 */
154	.globl	relocate_code
155relocate_code:
156	mov	r4, r0	/* save addr_sp */
157	mov	r5, r1	/* save addr of gd */
158	mov	r6, r2	/* save addr of destination */
159
160	/* Set up the stack						    */
161stack_setup:
162	mov	sp, r4
163
164	adr	r0, _start
165	cmp	r0, r6
166	beq	clear_bss		/* skip relocation */
167	mov	r1, r6			/* r1 <- scratch for copy_loop */
168	ldr	r2, _TEXT_BASE
169	ldr	r3, _bss_start_ofs
170	add	r2, r0, r3		/* r2 <- source end address	    */
171
172copy_loop:
173	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
174	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
175	cmp	r0, r2			/* until source end address [r2]    */
176	blo	copy_loop
177
178#ifndef CONFIG_PRELOADER
179	/*
180	 * fix .rel.dyn relocations
181	 */
182	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
183	sub	r9, r6, r0		/* r9 <- relocation offset */
184	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
185	add	r10, r10, r0		/* r10 <- sym table in FLASH */
186	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
187	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
188	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
189	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
190fixloop:
191	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
192	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
193	ldr	r1, [r2, #4]
194	and	r7, r1, #0xff
195	cmp	r7, #23			/* relative fixup? */
196	beq	fixrel
197	cmp	r7, #2			/* absolute fixup? */
198	beq	fixabs
199	/* ignore unknown type of fixup */
200	b	fixnext
201fixabs:
202	/* absolute fix: set location to (offset) symbol value */
203	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
204	add	r1, r10, r1		/* r1 <- address of symbol in table */
205	ldr	r1, [r1, #4]		/* r1 <- symbol value */
206	add	r1, r1, r9		/* r1 <- relocated sym addr */
207	b	fixnext
208fixrel:
209	/* relative fix: increase location by offset */
210	ldr	r1, [r0]
211	add	r1, r1, r9
212fixnext:
213	str	r1, [r0]
214	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
215	cmp	r2, r3
216	blo	fixloop
217#endif
218
219clear_bss:
220#ifndef CONFIG_PRELOADER
221	ldr	r0, _bss_start_ofs
222	ldr	r1, _bss_end_ofs
223	ldr	r3, _TEXT_BASE		/* Text base */
224	mov	r4, r6			/* reloc addr */
225	add	r0, r0, r4
226	add	r1, r1, r4
227	mov	r2, #0x00000000		/* clear			    */
228
229clbss_l:str	r2, [r0]		/* clear loop...		    */
230	add	r0, r0, #4
231	cmp	r0, r1
232	bne	clbss_l
233
234	bl coloured_LED_init
235	bl red_LED_on
236#endif
237
238/*
239 * We are done. Do not return, instead branch to second part of board
240 * initialization, now running from RAM.
241 */
242	ldr	r0, _board_init_r_ofs
243	adr	r1, _start
244	add	lr, r0, r1
245	add	lr, lr, r9
246	/* setup parameters for board_init_r */
247	mov	r0, r5		/* gd_t */
248	mov	r1, r6		/* dest_addr */
249	/* jump to it ... */
250	mov	pc, lr
251
252_board_init_r_ofs:
253	.word board_init_r - _start
254
255_rel_dyn_start_ofs:
256	.word __rel_dyn_start - _start
257_rel_dyn_end_ofs:
258	.word __rel_dyn_end - _start
259_dynsym_start_ofs:
260	.word __dynsym_start - _start
261
262/*
263 *************************************************************************
264 *
265 * CPU_init_critical registers
266 *
267 * setup important registers
268 * setup memory timing
269 *
270 *************************************************************************
271 */
272
273#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
274
275/* Interupt-Controller base addresses */
276INTMR1:		.word	0x80000280 @ 32 bit size
277INTMR2:		.word	0x80001280 @ 16 bit size
278INTMR3:		.word	0x80002280 @  8 bit size
279
280/* SYSCONs */
281SYSCON1:	.word	0x80000100
282SYSCON2:	.word	0x80001100
283SYSCON3:	.word	0x80002200
284
285#define CLKCTL	       0x6  /* mask */
286#define CLKCTL_18      0x0  /* 18.432 MHz */
287#define CLKCTL_36      0x2  /* 36.864 MHz */
288#define CLKCTL_49      0x4  /* 49.152 MHz */
289#define CLKCTL_73      0x6  /* 73.728 MHz */
290
291#elif defined(CONFIG_LPC2292)
292PLLCFG_ADR:	.word	PLLCFG
293PLLFEED_ADR:	.word	PLLFEED
294PLLCON_ADR:	.word	PLLCON
295PLLSTAT_ADR:	.word	PLLSTAT
296VPBDIV_ADR:	.word	VPBDIV
297MEMMAP_ADR:	.word	MEMMAP
298
299#endif
300
301cpu_init_crit:
302#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
303
304	/*
305	 * mask all IRQs by clearing all bits in the INTMRs
306	 */
307	mov	r1, #0x00
308	ldr	r0, INTMR1
309	str	r1, [r0]
310	ldr	r0, INTMR2
311	str	r1, [r0]
312	ldr	r0, INTMR3
313	str	r1, [r0]
314
315	/*
316	 * flush v4 I/D caches
317	 */
318	mov	r0, #0
319	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
320	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
321
322	/*
323	 * disable MMU stuff and caches
324	 */
325	mrc	p15,0,r0,c1,c0
326	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
327	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
328	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
329	mcr	p15,0,r0,c1,c0
330#elif defined(CONFIG_NETARM)
331	/*
332	 * prior to software reset : need to set pin PORTC4 to be *HRESET
333	 */
334	ldr	r0, =NETARM_GEN_MODULE_BASE
335	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
336			NETARM_GEN_PORT_DIR(0x10))
337	str	r1, [r0, #+NETARM_GEN_PORTC]
338	/*
339	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
340	 *		    for an explanation of this process
341	 */
342	ldr	r0, =NETARM_GEN_MODULE_BASE
343	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
344	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
345	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
346	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
347	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
348	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
349	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
350	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
351	/*
352	 * setup PLL and System Config
353	 */
354	ldr	r0, =NETARM_GEN_MODULE_BASE
355
356	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
357			NETARM_GEN_SYS_CFG_BUSFULL | \
358			NETARM_GEN_SYS_CFG_USER_EN | \
359			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
360			NETARM_GEN_SYS_CFG_BUSARB_INT | \
361			NETARM_GEN_SYS_CFG_BUSMON_EN )
362
363	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
364
365#ifndef CONFIG_NETARM_PLL_BYPASS
366	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
367			NETARM_GEN_PLL_CTL_POLTST_DEF | \
368			NETARM_GEN_PLL_CTL_INDIV(1) | \
369			NETARM_GEN_PLL_CTL_ICP_DEF | \
370			NETARM_GEN_PLL_CTL_OUTDIV(2) )
371	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
372#endif
373
374	/*
375	 * mask all IRQs by clearing all bits in the INTMRs
376	 */
377	mov	r1, #0
378	ldr	r0, =NETARM_GEN_MODULE_BASE
379	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
380
381#elif defined(CONFIG_S3C4510B)
382
383	/*
384	 * Mask off all IRQ sources
385	 */
386	ldr	r1, =REG_INTMASK
387	ldr	r0, =0x3FFFFF
388	str	r0, [r1]
389
390	/*
391	 * Disable Cache
392	 */
393	ldr r0, =REG_SYSCFG
394	ldr r1, =0x83ffffa0	/* cache-disabled  */
395	str r1, [r0]
396
397#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
398	/* No specific initialisation for IntegratorAP/CM720T as yet */
399#elif defined(CONFIG_LPC2292)
400	/* Set-up PLL */
401	mov	r3, #0xAA
402	mov	r4, #0x55
403	/* First disconnect and disable the PLL */
404	ldr	r0, PLLCON_ADR
405	mov	r1, #0x00
406	str	r1, [r0]
407	ldr	r0, PLLFEED_ADR /* start feed sequence */
408	str	r3, [r0]
409	str	r4, [r0]	/* feed sequence done */
410	/* Set new M and P values */
411	ldr	r0, PLLCFG_ADR
412	mov	r1, #0x23	/* M=4 and P=2 */
413	str	r1, [r0]
414	ldr	r0, PLLFEED_ADR /* start feed sequence */
415	str	r3, [r0]
416	str	r4, [r0]	/* feed sequence done */
417	/* Then enable the PLL */
418	ldr	r0, PLLCON_ADR
419	mov	r1, #0x01	/* PLL enable bit */
420	str	r1, [r0]
421	ldr	r0, PLLFEED_ADR /* start feed sequence */
422	str	r3, [r0]
423	str	r4, [r0]	/* feed sequence done */
424	/* Wait for the lock */
425	ldr	r0, PLLSTAT_ADR
426	mov	r1, #0x400	/* lock bit */
427lock_loop:
428	ldr	r2, [r0]
429	and	r2, r1, r2
430	cmp	r2, #0
431	beq	lock_loop
432	/* And finally connect the PLL */
433	ldr	r0, PLLCON_ADR
434	mov	r1, #0x03	/* PLL enable bit and connect bit */
435	str	r1, [r0]
436	ldr	r0, PLLFEED_ADR /* start feed sequence */
437	str	r3, [r0]
438	str	r4, [r0]	/* feed sequence done */
439	/* Set-up VPBDIV register */
440	ldr	r0, VPBDIV_ADR
441	mov	r1, #0x01	/* VPB clock is same as process clock */
442	str	r1, [r0]
443#else
444#error No cpu_init_crit() defined for current CPU type
445#endif
446
447#ifdef CONFIG_ARM7_REVD
448	/* set clock speed */
449	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
450	/* !!! not doing DRAM refresh properly! */
451	ldr	r0, SYSCON3
452	ldr	r1, [r0]
453	bic	r1, r1, #CLKCTL
454	orr	r1, r1, #CLKCTL_36
455	str	r1, [r0]
456#endif
457
458#ifndef CONFIG_LPC2292
459	mov	ip, lr
460	/*
461	 * before relocating, we have to setup RAM timing
462	 * because memory timing is board-dependent, you will
463	 * find a lowlevel_init.S in your board directory.
464	 */
465	bl	lowlevel_init
466	mov	lr, ip
467#endif
468
469	mov	pc, lr
470
471
472/*
473 *************************************************************************
474 *
475 * Interrupt handling
476 *
477 *************************************************************************
478 */
479
480@
481@ IRQ stack frame.
482@
483#define S_FRAME_SIZE	72
484
485#define S_OLD_R0	68
486#define S_PSR		64
487#define S_PC		60
488#define S_LR		56
489#define S_SP		52
490
491#define S_IP		48
492#define S_FP		44
493#define S_R10		40
494#define S_R9		36
495#define S_R8		32
496#define S_R7		28
497#define S_R6		24
498#define S_R5		20
499#define S_R4		16
500#define S_R3		12
501#define S_R2		8
502#define S_R1		4
503#define S_R0		0
504
505#define MODE_SVC 0x13
506#define I_BIT	 0x80
507
508/*
509 * use bad_save_user_regs for abort/prefetch/undef/swi ...
510 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
511 */
512
513	.macro	bad_save_user_regs
514	sub	sp, sp, #S_FRAME_SIZE
515	stmia	sp, {r0 - r12}			@ Calling r0-r12
516	add	r8, sp, #S_PC
517
518	ldr	r2, IRQ_STACK_START_IN
519	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
520	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
521
522	add	r5, sp, #S_SP
523	mov	r1, lr
524	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
525	mov	r0, sp
526	.endm
527
528	.macro	irq_save_user_regs
529	sub	sp, sp, #S_FRAME_SIZE
530	stmia	sp, {r0 - r12}			@ Calling r0-r12
531	add	r8, sp, #S_PC
532	stmdb	r8, {sp, lr}^			@ Calling SP, LR
533	str	lr, [r8, #0]			@ Save calling PC
534	mrs	r6, spsr
535	str	r6, [r8, #4]			@ Save CPSR
536	str	r0, [r8, #8]			@ Save OLD_R0
537	mov	r0, sp
538	.endm
539
540	.macro	irq_restore_user_regs
541	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
542	mov	r0, r0
543	ldr	lr, [sp, #S_PC]			@ Get PC
544	add	sp, sp, #S_FRAME_SIZE
545	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
546	.endm
547
548	.macro get_bad_stack
549	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
550
551	str	lr, [r13]			@ save caller lr / spsr
552	mrs	lr, spsr
553	str	lr, [r13, #4]
554
555	mov	r13, #MODE_SVC			@ prepare SVC-Mode
556	msr	spsr_c, r13
557	mov	lr, pc
558	movs	pc, lr
559	.endm
560
561	.macro get_irq_stack			@ setup IRQ stack
562	ldr	sp, IRQ_STACK_START
563	.endm
564
565	.macro get_fiq_stack			@ setup FIQ stack
566	ldr	sp, FIQ_STACK_START
567	.endm
568
569/*
570 * exception handlers
571 */
572	.align	5
573undefined_instruction:
574	get_bad_stack
575	bad_save_user_regs
576	bl	do_undefined_instruction
577
578	.align	5
579software_interrupt:
580	get_bad_stack
581	bad_save_user_regs
582	bl	do_software_interrupt
583
584	.align	5
585prefetch_abort:
586	get_bad_stack
587	bad_save_user_regs
588	bl	do_prefetch_abort
589
590	.align	5
591data_abort:
592	get_bad_stack
593	bad_save_user_regs
594	bl	do_data_abort
595
596	.align	5
597not_used:
598	get_bad_stack
599	bad_save_user_regs
600	bl	do_not_used
601
602#ifdef CONFIG_USE_IRQ
603
604	.align	5
605irq:
606	get_irq_stack
607	irq_save_user_regs
608	bl	do_irq
609	irq_restore_user_regs
610
611	.align	5
612fiq:
613	get_fiq_stack
614	/* someone ought to write a more effiction fiq_save_user_regs */
615	irq_save_user_regs
616	bl	do_fiq
617	irq_restore_user_regs
618
619#else
620
621	.align	5
622irq:
623	get_bad_stack
624	bad_save_user_regs
625	bl	do_irq
626
627	.align	5
628fiq:
629	get_bad_stack
630	bad_save_user_regs
631	bl	do_fiq
632
633#endif
634
635#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
636	.align	5
637.globl reset_cpu
638reset_cpu:
639	mov	ip, #0
640	mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
641	mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
642	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
643	bic	ip, ip, #0x000f			@ ............wcam
644	bic	ip, ip, #0x2100			@ ..v....s........
645	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
646	mov	pc, r0
647#elif defined(CONFIG_NETARM)
648	.align	5
649.globl reset_cpu
650reset_cpu:
651	ldr	r1, =NETARM_MEM_MODULE_BASE
652	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
653	ldr	r1, =0xFFFFF000
654	and	r0, r1, r0
655	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
656	add	r0, r1, r0
657	ldr	r4, =NETARM_GEN_MODULE_BASE
658	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
659	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
660	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
661	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
662	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
663	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
664	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
665	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
666	mov	pc, r0
667#elif defined(CONFIG_S3C4510B)
668/* Nothing done here as reseting the CPU is board specific, depending
669 * on external peripherals such as watchdog timers, etc. */
670#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
671	/* No specific reset actions for IntegratorAP/CM720T as yet */
672#elif defined(CONFIG_LPC2292)
673	.align	5
674.globl reset_cpu
675reset_cpu:
676	mov	pc, r0
677#else
678#error No reset_cpu() defined for current CPU type
679#endif
680