1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36#ifdef CONFIG_ENABLE_MMU 37#include <asm/proc/domain.h> 38#endif 39 40#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 41#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 42#endif 43 44/* 45 ************************************************************************* 46 * 47 * Jump vector table as in table 3.1 in [1] 48 * 49 ************************************************************************* 50 */ 51 52.globl _start 53_start: b reset 54#ifndef CONFIG_NAND_SPL 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: 64 .word undefined_instruction 65_software_interrupt: 66 .word software_interrupt 67_prefetch_abort: 68 .word prefetch_abort 69_data_abort: 70 .word data_abort 71_not_used: 72 .word not_used 73_irq: 74 .word irq 75_fiq: 76 .word fiq 77_pad: 78 .word 0x12345678 /* now 16*4=64 */ 79#else 80 . = _start + 64 81#endif 82 83.global _end_vect 84_end_vect: 85 .balignl 16,0xdeadbeef 86/* 87 ************************************************************************* 88 * 89 * Startup Code (reset vector) 90 * 91 * do important init only if we don't start from memory! 92 * setup Memory and board specific bits prior to relocation. 93 * relocate armboot to ram 94 * setup stack 95 * 96 ************************************************************************* 97 */ 98 99.globl _TEXT_BASE 100_TEXT_BASE: 101 .word CONFIG_SYS_TEXT_BASE 102 103/* 104 * Below variable is very important because we use MMU in U-Boot. 105 * Without it, we cannot run code correctly before MMU is ON. 106 * by scsuh. 107 */ 108_TEXT_PHY_BASE: 109 .word CONFIG_SYS_PHY_UBOOT_BASE 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117 118.globl _bss_start_ofs 119_bss_start_ofs: 120 .word __bss_start - _start 121 122.globl _bss_end_ofs 123_bss_end_ofs: 124 .word _end - _start 125 126.globl _datarel_start_ofs 127_datarel_start_ofs: 128 .word __datarel_start - _start 129 130.globl _datarelrolocal_start_ofs 131_datarelrolocal_start_ofs: 132 .word __datarelrolocal_start - _start 133 134.globl _datarellocal_start_ofs 135_datarellocal_start_ofs: 136 .word __datarellocal_start - _start 137 138.globl _datarelro_start_ofs 139_datarelro_start_ofs: 140 .word __datarelro_start - _start 141 142.globl _rel_dyn_start_ofs 143_rel_dyn_start_ofs: 144 .word __rel_dyn_start - _start 145 146.globl _rel_dyn_end_ofs 147_rel_dyn_end_ofs: 148 .word __rel_dyn_end - _start 149 150.globl _dynsym_start_ofs 151_dynsym_start_ofs: 152 .word __dynsym_start - _start 153 154/* IRQ stack memory (calculated at run-time) + 8 bytes */ 155.globl IRQ_STACK_START_IN 156IRQ_STACK_START_IN: 157 .word 0x0badc0de 158 159/* 160 * the actual reset code 161 */ 162 163reset: 164 /* 165 * set the cpu to SVC32 mode 166 */ 167 mrs r0, cpsr 168 bic r0, r0, #0x3f 169 orr r0, r0, #0xd3 170 msr cpsr, r0 171 172/* 173 ************************************************************************* 174 * 175 * CPU_init_critical registers 176 * 177 * setup important registers 178 * setup memory timing 179 * 180 ************************************************************************* 181 */ 182 /* 183 * we do sys-critical inits only at reboot, 184 * not when booting from ram! 185 */ 186cpu_init_crit: 187 /* 188 * When booting from NAND - it has definitely been a reset, so, no need 189 * to flush caches and disable the MMU 190 */ 191#ifndef CONFIG_NAND_SPL 192 /* 193 * flush v4 I/D caches 194 */ 195 mov r0, #0 196 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 197 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 198 199 /* 200 * disable MMU stuff and caches 201 */ 202 mrc p15, 0, r0, c1, c0, 0 203 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 204 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 205 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 206 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 207 208 /* Prepare to disable the MMU */ 209 adr r2, mmu_disable_phys 210 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 211 b mmu_disable 212 213 .align 5 214 /* Run in a single cache-line */ 215mmu_disable: 216 mcr p15, 0, r0, c1, c0, 0 217 nop 218 nop 219 mov pc, r2 220mmu_disable_phys: 221 222#ifdef CONFIG_DISABLE_TCM 223 /* 224 * Disable the TCMs 225 */ 226 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 227 cmp r0, #0 228 beq skip_tcmdisable 229 mov r1, #0 230 mov r2, #1 231 tst r0, r2 232 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 233 tst r0, r2, LSL #16 234 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 235skip_tcmdisable: 236#endif 237#endif 238 239#ifdef CONFIG_PERIPORT_REMAP 240 /* Peri port setup */ 241 ldr r0, =CONFIG_PERIPORT_BASE 242 orr r0, r0, #CONFIG_PERIPORT_SIZE 243 mcr p15,0,r0,c15,c2,4 244#endif 245 246 /* 247 * Go setup Memory and board specific bits prior to relocation. 248 */ 249 bl lowlevel_init /* go setup pll,mux,memory */ 250 251/* Set stackpointer in internal RAM to call board_init_f */ 252call_board_init_f: 253 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 254 ldr r0,=0x00000000 255 bl board_init_f 256 257/*------------------------------------------------------------------------------*/ 258 259/* 260 * void relocate_code (addr_sp, gd, addr_moni) 261 * 262 * This "function" does not return, instead it continues in RAM 263 * after relocating the monitor code. 264 * 265 */ 266 .globl relocate_code 267relocate_code: 268 mov r4, r0 /* save addr_sp */ 269 mov r5, r1 /* save addr of gd */ 270 mov r6, r2 /* save addr of destination */ 271 mov r7, r2 /* save addr of destination */ 272 273 /* Set up the stack */ 274stack_setup: 275 mov sp, r4 276 277 adr r0, _start 278 ldr r2, _TEXT_BASE 279 ldr r3, _bss_start_ofs 280 add r2, r0, r3 /* r2 <- source end address */ 281 cmp r0, r6 282 beq clear_bss 283 284copy_loop: 285 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 286 stmia r6!, {r9-r10} /* copy to target address [r1] */ 287 cmp r0, r2 /* until source end address [r2] */ 288 blo copy_loop 289 290#ifndef CONFIG_PRELOADER 291 /* 292 * fix .rel.dyn relocations 293 */ 294 ldr r0, _TEXT_BASE /* r0 <- Text base */ 295 sub r9, r7, r0 /* r9 <- relocation offset */ 296 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 297 add r10, r10, r0 /* r10 <- sym table in FLASH */ 298 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 299 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 300 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 301 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 302fixloop: 303 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 304 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 305 ldr r1, [r2, #4] 306 and r8, r1, #0xff 307 cmp r8, #23 /* relative fixup? */ 308 beq fixrel 309 cmp r8, #2 /* absolute fixup? */ 310 beq fixabs 311 /* ignore unknown type of fixup */ 312 b fixnext 313fixabs: 314 /* absolute fix: set location to (offset) symbol value */ 315 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 316 add r1, r10, r1 /* r1 <- address of symbol in table */ 317 ldr r1, [r1, #4] /* r1 <- symbol value */ 318 add r1, r1, r9 /* r1 <- relocated sym addr */ 319 b fixnext 320fixrel: 321 /* relative fix: increase location by offset */ 322 ldr r1, [r0] 323 add r1, r1, r9 324fixnext: 325 str r1, [r0] 326 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 327 cmp r2, r3 328 blo fixloop 329#endif 330 331#ifdef CONFIG_ENABLE_MMU 332enable_mmu: 333 /* enable domain access */ 334 ldr r5, =0x0000ffff 335 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 336 337 /* Set the TTB register */ 338 ldr r0, _mmu_table_base 339 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 340 ldr r2, =0xfff00000 341 bic r0, r0, r2 342 orr r1, r0, r1 343 mcr p15, 0, r1, c2, c0, 0 344 345 /* Enable the MMU */ 346 mrc p15, 0, r0, c1, c0, 0 347 orr r0, r0, #1 /* Set CR_M to enable MMU */ 348 349 /* Prepare to enable the MMU */ 350 adr r1, skip_hw_init 351 and r1, r1, #0x3fc 352 ldr r2, _TEXT_BASE 353 ldr r3, =0xfff00000 354 and r2, r2, r3 355 orr r2, r2, r1 356 b mmu_enable 357 358 .align 5 359 /* Run in a single cache-line */ 360mmu_enable: 361 362 mcr p15, 0, r0, c1, c0, 0 363 nop 364 nop 365 mov pc, r2 366skip_hw_init: 367#endif 368 369clear_bss: 370#ifndef CONFIG_PRELOADER 371 ldr r0, _bss_start_ofs 372 ldr r1, _bss_end_ofs 373 ldr r3, _TEXT_BASE /* Text base */ 374 mov r4, r7 /* reloc addr */ 375 add r0, r0, r4 376 add r1, r1, r4 377 mov r2, #0x00000000 /* clear */ 378 379clbss_l:str r2, [r0] /* clear loop... */ 380 add r0, r0, #4 381 cmp r0, r1 382 bne clbss_l 383 384 bl coloured_LED_init 385 bl red_LED_on 386#endif 387 388/* 389 * We are done. Do not return, instead branch to second part of board 390 * initialization, now running from RAM. 391 */ 392#ifdef CONFIG_NAND_SPL 393 ldr pc, _nand_boot 394 395_nand_boot: .word nand_boot 396#else 397 ldr r0, _board_init_r_ofs 398 adr r1, _start 399 add lr, r0, r1 400 add lr, lr, r9 401 /* setup parameters for board_init_r */ 402 mov r0, r5 /* gd_t */ 403 mov r1, r7 /* dest_addr */ 404 /* jump to it ... */ 405 mov pc, lr 406 407_board_init_r_ofs: 408 .word board_init_r - _start 409#endif 410 411#ifdef CONFIG_ENABLE_MMU 412_mmu_table_base: 413 .word mmu_table 414#endif 415 416#ifndef CONFIG_NAND_SPL 417/* 418 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 419 * actually, we don't need to do anything about cache if not use d-cache in 420 * U-Boot. So, in this function we clean only MMU. by scsuh 421 * 422 * void theLastJump(void *kernel, int arch_num, uint boot_params); 423 */ 424#ifdef CONFIG_ENABLE_MMU 425 .globl theLastJump 426theLastJump: 427 mov r9, r0 428 ldr r3, =0xfff00000 429 ldr r4, _TEXT_PHY_BASE 430 adr r5, phy_last_jump 431 bic r5, r5, r3 432 orr r5, r5, r4 433 mov pc, r5 434phy_last_jump: 435 /* 436 * disable MMU stuff 437 */ 438 mrc p15, 0, r0, c1, c0, 0 439 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 440 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 441 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 442 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 443 mcr p15, 0, r0, c1, c0, 0 444 445 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 446 447 mov r0, #0 448 mov pc, r9 449#endif 450 451 452/* 453 ************************************************************************* 454 * 455 * Interrupt handling 456 * 457 ************************************************************************* 458 */ 459@ 460@ IRQ stack frame. 461@ 462#define S_FRAME_SIZE 72 463 464#define S_OLD_R0 68 465#define S_PSR 64 466#define S_PC 60 467#define S_LR 56 468#define S_SP 52 469 470#define S_IP 48 471#define S_FP 44 472#define S_R10 40 473#define S_R9 36 474#define S_R8 32 475#define S_R7 28 476#define S_R6 24 477#define S_R5 20 478#define S_R4 16 479#define S_R3 12 480#define S_R2 8 481#define S_R1 4 482#define S_R0 0 483 484#define MODE_SVC 0x13 485#define I_BIT 0x80 486 487/* 488 * use bad_save_user_regs for abort/prefetch/undef/swi ... 489 */ 490 491 .macro bad_save_user_regs 492 /* carve out a frame on current user stack */ 493 sub sp, sp, #S_FRAME_SIZE 494 /* Save user registers (now in svc mode) r0-r12 */ 495 stmia sp, {r0 - r12} 496 497 ldr r2, IRQ_STACK_START_IN 498 /* get values for "aborted" pc and cpsr (into parm regs) */ 499 ldmia r2, {r2 - r3} 500 /* grab pointer to old stack */ 501 add r0, sp, #S_FRAME_SIZE 502 503 add r5, sp, #S_SP 504 mov r1, lr 505 /* save sp_SVC, lr_SVC, pc, cpsr */ 506 stmia r5, {r0 - r3} 507 /* save current stack into r0 (param register) */ 508 mov r0, sp 509 .endm 510 511 .macro get_bad_stack 512 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 513 514 /* save caller lr in position 0 of saved stack */ 515 str lr, [r13] 516 /* get the spsr */ 517 mrs lr, spsr 518 /* save spsr in position 1 of saved stack */ 519 str lr, [r13, #4] 520 521 /* prepare SVC-Mode */ 522 mov r13, #MODE_SVC 523 @ msr spsr_c, r13 524 /* switch modes, make sure moves will execute */ 525 msr spsr, r13 526 /* capture return pc */ 527 mov lr, pc 528 /* jump to next instruction & switch modes. */ 529 movs pc, lr 530 .endm 531 532 .macro get_bad_stack_swi 533 /* space on current stack for scratch reg. */ 534 sub r13, r13, #4 535 /* save R0's value. */ 536 str r0, [r13] 537 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 538 /* save caller lr in position 0 of saved stack */ 539 str lr, [r0] 540 /* get the spsr */ 541 mrs r0, spsr 542 /* save spsr in position 1 of saved stack */ 543 str lr, [r0, #4] 544 /* restore r0 */ 545 ldr r0, [r13] 546 /* pop stack entry */ 547 add r13, r13, #4 548 .endm 549 550/* 551 * exception handlers 552 */ 553 .align 5 554undefined_instruction: 555 get_bad_stack 556 bad_save_user_regs 557 bl do_undefined_instruction 558 559 .align 5 560software_interrupt: 561 get_bad_stack_swi 562 bad_save_user_regs 563 bl do_software_interrupt 564 565 .align 5 566prefetch_abort: 567 get_bad_stack 568 bad_save_user_regs 569 bl do_prefetch_abort 570 571 .align 5 572data_abort: 573 get_bad_stack 574 bad_save_user_regs 575 bl do_data_abort 576 577 .align 5 578not_used: 579 get_bad_stack 580 bad_save_user_regs 581 bl do_not_used 582 583 .align 5 584irq: 585 get_bad_stack 586 bad_save_user_regs 587 bl do_irq 588 589 .align 5 590fiq: 591 get_bad_stack 592 bad_save_user_regs 593 bl do_fiq 594#endif /* CONFIG_NAND_SPL */ 595