1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_PRELOADER 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_PRELOADER */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word _end - _start 106 107.globl _datarel_start_ofs 108_datarel_start_ofs: 109 .word __datarel_start - _start 110 111.globl _datarelrolocal_start_ofs 112_datarelrolocal_start_ofs: 113 .word __datarelrolocal_start - _start 114 115.globl _datarellocal_start_ofs 116_datarellocal_start_ofs: 117 .word __datarellocal_start - _start 118 119.globl _datarelro_start_ofs 120_datarelro_start_ofs: 121 .word __datarelro_start - _start 122 123#ifdef CONFIG_USE_IRQ 124/* IRQ stack memory (calculated at run-time) */ 125.globl IRQ_STACK_START 126IRQ_STACK_START: 127 .word 0x0badc0de 128 129/* IRQ stack memory (calculated at run-time) */ 130.globl FIQ_STACK_START 131FIQ_STACK_START: 132 .word 0x0badc0de 133#endif 134 135/* IRQ stack memory (calculated at run-time) + 8 bytes */ 136.globl IRQ_STACK_START_IN 137IRQ_STACK_START_IN: 138 .word 0x0badc0de 139 140/* 141 * the actual reset code 142 */ 143 144reset: 145 /* 146 * set the cpu to SVC32 mode 147 */ 148 mrs r0,cpsr 149 bic r0,r0,#0x1f 150 orr r0,r0,#0xd3 151 msr cpsr,r0 152 153#ifdef CONFIG_OMAP2420H4 154 /* Copy vectors to mask ROM indirect addr */ 155 adr r0, _start /* r0 <- current position of code */ 156 add r0, r0, #4 /* skip reset vector */ 157 mov r2, #64 /* r2 <- size to copy */ 158 add r2, r0, r2 /* r2 <- source end address */ 159 mov r1, #SRAM_OFFSET0 /* build vect addr */ 160 mov r3, #SRAM_OFFSET1 161 add r1, r1, r3 162 mov r3, #SRAM_OFFSET2 163 add r1, r1, r3 164next: 165 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 166 stmia r1!, {r3-r10} /* copy to target address [r1] */ 167 cmp r0, r2 /* until source end address [r2] */ 168 bne next /* loop until equal */ 169 bl cpy_clk_code /* put dpll adjust code behind vectors */ 170#endif 171 /* the mask ROM code should have PLL and others stable */ 172#ifndef CONFIG_SKIP_LOWLEVEL_INIT 173 bl cpu_init_crit 174#endif 175 176/* Set stackpointer in internal RAM to call board_init_f */ 177call_board_init_f: 178 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 179 ldr r0,=0x00000000 180 181#ifdef CONFIG_NAND_SPL 182 bl nand_boot 183#else 184#ifdef CONFIG_ONENAND_IPL 185 bl start_oneboot 186#else 187 bl board_init_f 188#endif /* CONFIG_ONENAND_IPL */ 189#endif /* CONFIG_NAND_SPL */ 190 191/*------------------------------------------------------------------------------*/ 192 193/* 194 * void relocate_code (addr_sp, gd, addr_moni) 195 * 196 * This "function" does not return, instead it continues in RAM 197 * after relocating the monitor code. 198 * 199 */ 200 .globl relocate_code 201relocate_code: 202 mov r4, r0 /* save addr_sp */ 203 mov r5, r1 /* save addr of gd */ 204 mov r6, r2 /* save addr of destination */ 205 mov r7, r2 /* save addr of destination */ 206 207 /* Set up the stack */ 208stack_setup: 209 mov sp, r4 210 211 adr r0, _start 212 ldr r2, _TEXT_BASE 213 ldr r3, _bss_start_ofs 214 add r2, r0, r3 /* r2 <- source end address */ 215 cmp r0, r6 216 beq clear_bss 217 218copy_loop: 219 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 220 stmia r6!, {r9-r10} /* copy to target address [r1] */ 221 cmp r0, r2 /* until source end address [r2] */ 222 blo copy_loop 223 224#ifndef CONFIG_PRELOADER 225 /* 226 * fix .rel.dyn relocations 227 */ 228 ldr r0, _TEXT_BASE /* r0 <- Text base */ 229 sub r9, r7, r0 /* r9 <- relocation offset */ 230 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 231 add r10, r10, r0 /* r10 <- sym table in FLASH */ 232 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 233 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 234 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 235 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 236fixloop: 237 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 238 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 239 ldr r1, [r2, #4] 240 and r8, r1, #0xff 241 cmp r8, #23 /* relative fixup? */ 242 beq fixrel 243 cmp r8, #2 /* absolute fixup? */ 244 beq fixabs 245 /* ignore unknown type of fixup */ 246 b fixnext 247fixabs: 248 /* absolute fix: set location to (offset) symbol value */ 249 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 250 add r1, r10, r1 /* r1 <- address of symbol in table */ 251 ldr r1, [r1, #4] /* r1 <- symbol value */ 252 add r1, r9 /* r1 <- relocated sym addr */ 253 b fixnext 254fixrel: 255 /* relative fix: increase location by offset */ 256 ldr r1, [r0] 257 add r1, r1, r9 258fixnext: 259 str r1, [r0] 260 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 261 cmp r2, r3 262 blo fixloop 263#endif 264 265clear_bss: 266#ifndef CONFIG_PRELOADER 267 ldr r0, _bss_start_ofs 268 ldr r1, _bss_end_ofs 269 ldr r3, _TEXT_BASE /* Text base */ 270 mov r4, r7 /* reloc addr */ 271 add r0, r0, r4 272 add r1, r1, r4 273 mov r2, #0x00000000 /* clear */ 274 275clbss_l:str r2, [r0] /* clear loop... */ 276 add r0, r0, #4 277 cmp r0, r1 278 bne clbss_l 279#endif /* #ifndef CONFIG_PRELOADER */ 280 281/* 282 * We are done. Do not return, instead branch to second part of board 283 * initialization, now running from RAM. 284 */ 285#ifdef CONFIG_NAND_SPL 286 ldr r0, _nand_boot_ofs 287 adr r1, _start 288 add pc, r0, r1 289_nand_boot_ofs 290 : .word nand_boot - _start 291#else 292jump_2_ram: 293 ldr r0, _board_init_r_ofs 294 adr r1, _start 295 add lr, r0, r1 296 add lr, lr, r9 297 /* setup parameters for board_init_r */ 298 mov r0, r5 /* gd_t */ 299 mov r1, r7 /* dest_addr */ 300 /* jump to it ... */ 301 mov pc, lr 302 303_board_init_r_ofs: 304 .word board_init_r - _start 305#endif 306 307_rel_dyn_start_ofs: 308 .word __rel_dyn_start - _start 309_rel_dyn_end_ofs: 310 .word __rel_dyn_end - _start 311_dynsym_start_ofs: 312 .word __dynsym_start - _start 313 314/* 315 ************************************************************************* 316 * 317 * CPU_init_critical registers 318 * 319 * setup important registers 320 * setup memory timing 321 * 322 ************************************************************************* 323 */ 324#ifndef CONFIG_SKIP_LOWLEVEL_INIT 325cpu_init_crit: 326 /* 327 * flush v4 I/D caches 328 */ 329 mov r0, #0 330 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 331 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 332 333 /* 334 * disable MMU stuff and caches 335 */ 336 mrc p15, 0, r0, c1, c0, 0 337 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 338 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 339 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 340 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 341 mcr p15, 0, r0, c1, c0, 0 342 343 /* 344 * Jump to board specific initialization... The Mask ROM will have already initialized 345 * basic memory. Go here to bump up clock rate and handle wake up conditions. 346 */ 347 mov ip, lr /* persevere link reg across call */ 348 bl lowlevel_init /* go setup pll,mux,memory */ 349 mov lr, ip /* restore link */ 350 mov pc, lr /* back to my caller */ 351#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 352 353#ifndef CONFIG_PRELOADER 354/* 355 ************************************************************************* 356 * 357 * Interrupt handling 358 * 359 ************************************************************************* 360 */ 361@ 362@ IRQ stack frame. 363@ 364#define S_FRAME_SIZE 72 365 366#define S_OLD_R0 68 367#define S_PSR 64 368#define S_PC 60 369#define S_LR 56 370#define S_SP 52 371 372#define S_IP 48 373#define S_FP 44 374#define S_R10 40 375#define S_R9 36 376#define S_R8 32 377#define S_R7 28 378#define S_R6 24 379#define S_R5 20 380#define S_R4 16 381#define S_R3 12 382#define S_R2 8 383#define S_R1 4 384#define S_R0 0 385 386#define MODE_SVC 0x13 387#define I_BIT 0x80 388 389/* 390 * use bad_save_user_regs for abort/prefetch/undef/swi ... 391 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 392 */ 393 394 .macro bad_save_user_regs 395 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 396 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 397 398 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 399 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 400 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 401 402 add r5, sp, #S_SP 403 mov r1, lr 404 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 405 mov r0, sp @ save current stack into r0 (param register) 406 .endm 407 408 .macro irq_save_user_regs 409 sub sp, sp, #S_FRAME_SIZE 410 stmia sp, {r0 - r12} @ Calling r0-r12 411 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 412 stmdb r8, {sp, lr}^ @ Calling SP, LR 413 str lr, [r8, #0] @ Save calling PC 414 mrs r6, spsr 415 str r6, [r8, #4] @ Save CPSR 416 str r0, [r8, #8] @ Save OLD_R0 417 mov r0, sp 418 .endm 419 420 .macro irq_restore_user_regs 421 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 422 mov r0, r0 423 ldr lr, [sp, #S_PC] @ Get PC 424 add sp, sp, #S_FRAME_SIZE 425 subs pc, lr, #4 @ return & move spsr_svc into cpsr 426 .endm 427 428 .macro get_bad_stack 429 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 430 431 str lr, [r13] @ save caller lr in position 0 of saved stack 432 mrs lr, spsr @ get the spsr 433 str lr, [r13, #4] @ save spsr in position 1 of saved stack 434 435 mov r13, #MODE_SVC @ prepare SVC-Mode 436 @ msr spsr_c, r13 437 msr spsr, r13 @ switch modes, make sure moves will execute 438 mov lr, pc @ capture return pc 439 movs pc, lr @ jump to next instruction & switch modes. 440 .endm 441 442 .macro get_bad_stack_swi 443 sub r13, r13, #4 @ space on current stack for scratch reg. 444 str r0, [r13] @ save R0's value. 445 ldr r0, IRQ_STACK_START_IN @ get data regions start 446 str lr, [r0] @ save caller lr in position 0 of saved stack 447 mrs r0, spsr @ get the spsr 448 str lr, [r0, #4] @ save spsr in position 1 of saved stack 449 ldr r0, [r13] @ restore r0 450 add r13, r13, #4 @ pop stack entry 451 .endm 452 453 .macro get_irq_stack @ setup IRQ stack 454 ldr sp, IRQ_STACK_START 455 .endm 456 457 .macro get_fiq_stack @ setup FIQ stack 458 ldr sp, FIQ_STACK_START 459 .endm 460#endif /* CONFIG_PRELOADER */ 461 462/* 463 * exception handlers 464 */ 465#ifdef CONFIG_PRELOADER 466 .align 5 467do_hang: 468 ldr sp, _TEXT_BASE /* use 32 words about stack */ 469 bl hang /* hang and never return */ 470#else /* !CONFIG_PRELOADER */ 471 .align 5 472undefined_instruction: 473 get_bad_stack 474 bad_save_user_regs 475 bl do_undefined_instruction 476 477 .align 5 478software_interrupt: 479 get_bad_stack_swi 480 bad_save_user_regs 481 bl do_software_interrupt 482 483 .align 5 484prefetch_abort: 485 get_bad_stack 486 bad_save_user_regs 487 bl do_prefetch_abort 488 489 .align 5 490data_abort: 491 get_bad_stack 492 bad_save_user_regs 493 bl do_data_abort 494 495 .align 5 496not_used: 497 get_bad_stack 498 bad_save_user_regs 499 bl do_not_used 500 501#ifdef CONFIG_USE_IRQ 502 503 .align 5 504irq: 505 get_irq_stack 506 irq_save_user_regs 507 bl do_irq 508 irq_restore_user_regs 509 510 .align 5 511fiq: 512 get_fiq_stack 513 /* someone ought to write a more effiction fiq_save_user_regs */ 514 irq_save_user_regs 515 bl do_fiq 516 irq_restore_user_regs 517 518#else 519 520 .align 5 521irq: 522 get_bad_stack 523 bad_save_user_regs 524 bl do_irq 525 526 .align 5 527fiq: 528 get_bad_stack 529 bad_save_user_regs 530 bl do_fiq 531 532#endif 533 .align 5 534.global arm1136_cache_flush 535arm1136_cache_flush: 536#if !defined(CONFIG_SYS_NO_ICACHE) 537 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 538#endif 539#if !defined(CONFIG_SYS_NO_DCACHE) 540 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 541#endif 542 mov pc, lr @ back to caller 543#endif /* CONFIG_PRELOADER */ 544