1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_PRELOADER 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_PRELOADER */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word __bss_end__ - _start 106 107#ifdef CONFIG_USE_IRQ 108/* IRQ stack memory (calculated at run-time) */ 109.globl IRQ_STACK_START 110IRQ_STACK_START: 111 .word 0x0badc0de 112 113/* IRQ stack memory (calculated at run-time) */ 114.globl FIQ_STACK_START 115FIQ_STACK_START: 116 .word 0x0badc0de 117#endif 118 119/* IRQ stack memory (calculated at run-time) + 8 bytes */ 120.globl IRQ_STACK_START_IN 121IRQ_STACK_START_IN: 122 .word 0x0badc0de 123 124/* 125 * the actual reset code 126 */ 127 128reset: 129 /* 130 * set the cpu to SVC32 mode 131 */ 132 mrs r0,cpsr 133 bic r0,r0,#0x1f 134 orr r0,r0,#0xd3 135 msr cpsr,r0 136 137#ifdef CONFIG_OMAP2420H4 138 /* Copy vectors to mask ROM indirect addr */ 139 adr r0, _start /* r0 <- current position of code */ 140 add r0, r0, #4 /* skip reset vector */ 141 mov r2, #64 /* r2 <- size to copy */ 142 add r2, r0, r2 /* r2 <- source end address */ 143 mov r1, #SRAM_OFFSET0 /* build vect addr */ 144 mov r3, #SRAM_OFFSET1 145 add r1, r1, r3 146 mov r3, #SRAM_OFFSET2 147 add r1, r1, r3 148next: 149 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 150 stmia r1!, {r3-r10} /* copy to target address [r1] */ 151 cmp r0, r2 /* until source end address [r2] */ 152 bne next /* loop until equal */ 153 bl cpy_clk_code /* put dpll adjust code behind vectors */ 154#endif 155 /* the mask ROM code should have PLL and others stable */ 156#ifndef CONFIG_SKIP_LOWLEVEL_INIT 157 bl cpu_init_crit 158#endif 159 160/* Set stackpointer in internal RAM to call board_init_f */ 161call_board_init_f: 162 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 163 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 164 ldr r0,=0x00000000 165 166 bl board_init_f 167 168/*------------------------------------------------------------------------------*/ 169 170/* 171 * void relocate_code (addr_sp, gd, addr_moni) 172 * 173 * This "function" does not return, instead it continues in RAM 174 * after relocating the monitor code. 175 * 176 */ 177 .globl relocate_code 178relocate_code: 179 mov r4, r0 /* save addr_sp */ 180 mov r5, r1 /* save addr of gd */ 181 mov r6, r2 /* save addr of destination */ 182 183 /* Set up the stack */ 184stack_setup: 185 mov sp, r4 186 187 adr r0, _start 188 cmp r0, r6 189 beq clear_bss /* skip relocation */ 190 mov r1, r6 /* r1 <- scratch for copy_loop */ 191 ldr r3, _bss_start_ofs 192 add r2, r0, r3 /* r2 <- source end address */ 193 194copy_loop: 195 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 196 stmia r1!, {r9-r10} /* copy to target address [r1] */ 197 cmp r0, r2 /* until source end address [r2] */ 198 blo copy_loop 199 200#ifndef CONFIG_PRELOADER 201 /* 202 * fix .rel.dyn relocations 203 */ 204 ldr r0, _TEXT_BASE /* r0 <- Text base */ 205 sub r9, r6, r0 /* r9 <- relocation offset */ 206 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 207 add r10, r10, r0 /* r10 <- sym table in FLASH */ 208 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 209 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 210 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 211 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 212fixloop: 213 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 214 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 215 ldr r1, [r2, #4] 216 and r7, r1, #0xff 217 cmp r7, #23 /* relative fixup? */ 218 beq fixrel 219 cmp r7, #2 /* absolute fixup? */ 220 beq fixabs 221 /* ignore unknown type of fixup */ 222 b fixnext 223fixabs: 224 /* absolute fix: set location to (offset) symbol value */ 225 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 226 add r1, r10, r1 /* r1 <- address of symbol in table */ 227 ldr r1, [r1, #4] /* r1 <- symbol value */ 228 add r1, r1, r9 /* r1 <- relocated sym addr */ 229 b fixnext 230fixrel: 231 /* relative fix: increase location by offset */ 232 ldr r1, [r0] 233 add r1, r1, r9 234fixnext: 235 str r1, [r0] 236 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 237 cmp r2, r3 238 blo fixloop 239#endif 240 241clear_bss: 242#ifndef CONFIG_PRELOADER 243 ldr r0, _bss_start_ofs 244 ldr r1, _bss_end_ofs 245 mov r4, r6 /* reloc addr */ 246 add r0, r0, r4 247 add r1, r1, r4 248 mov r2, #0x00000000 /* clear */ 249 250clbss_l:str r2, [r0] /* clear loop... */ 251 add r0, r0, #4 252 cmp r0, r1 253 bne clbss_l 254#endif /* #ifndef CONFIG_PRELOADER */ 255 256/* 257 * We are done. Do not return, instead branch to second part of board 258 * initialization, now running from RAM. 259 */ 260#ifdef CONFIG_NAND_SPL 261 ldr r0, _nand_boot_ofs 262 mov pc, r0 263 264_nand_boot_ofs: 265 .word nand_boot 266#else 267jump_2_ram: 268 ldr r0, _board_init_r_ofs 269 ldr r1, _TEXT_BASE 270 add lr, r0, r1 271 add lr, lr, r9 272 /* setup parameters for board_init_r */ 273 mov r0, r5 /* gd_t */ 274 mov r1, r6 /* dest_addr */ 275 /* jump to it ... */ 276 mov pc, lr 277 278_board_init_r_ofs: 279 .word board_init_r - _start 280#endif 281 282_rel_dyn_start_ofs: 283 .word __rel_dyn_start - _start 284_rel_dyn_end_ofs: 285 .word __rel_dyn_end - _start 286_dynsym_start_ofs: 287 .word __dynsym_start - _start 288 289/* 290 ************************************************************************* 291 * 292 * CPU_init_critical registers 293 * 294 * setup important registers 295 * setup memory timing 296 * 297 ************************************************************************* 298 */ 299#ifndef CONFIG_SKIP_LOWLEVEL_INIT 300cpu_init_crit: 301 /* 302 * flush v4 I/D caches 303 */ 304 mov r0, #0 305 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 306 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 307 308 /* 309 * disable MMU stuff and caches 310 */ 311 mrc p15, 0, r0, c1, c0, 0 312 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 313 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 314 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 315 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 316 mcr p15, 0, r0, c1, c0, 0 317 318 /* 319 * Jump to board specific initialization... The Mask ROM will have already initialized 320 * basic memory. Go here to bump up clock rate and handle wake up conditions. 321 */ 322 mov ip, lr /* persevere link reg across call */ 323 bl lowlevel_init /* go setup pll,mux,memory */ 324 mov lr, ip /* restore link */ 325 mov pc, lr /* back to my caller */ 326#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 327 328#ifndef CONFIG_PRELOADER 329/* 330 ************************************************************************* 331 * 332 * Interrupt handling 333 * 334 ************************************************************************* 335 */ 336@ 337@ IRQ stack frame. 338@ 339#define S_FRAME_SIZE 72 340 341#define S_OLD_R0 68 342#define S_PSR 64 343#define S_PC 60 344#define S_LR 56 345#define S_SP 52 346 347#define S_IP 48 348#define S_FP 44 349#define S_R10 40 350#define S_R9 36 351#define S_R8 32 352#define S_R7 28 353#define S_R6 24 354#define S_R5 20 355#define S_R4 16 356#define S_R3 12 357#define S_R2 8 358#define S_R1 4 359#define S_R0 0 360 361#define MODE_SVC 0x13 362#define I_BIT 0x80 363 364/* 365 * use bad_save_user_regs for abort/prefetch/undef/swi ... 366 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 367 */ 368 369 .macro bad_save_user_regs 370 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 371 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 372 373 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 374 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 375 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 376 377 add r5, sp, #S_SP 378 mov r1, lr 379 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 380 mov r0, sp @ save current stack into r0 (param register) 381 .endm 382 383 .macro irq_save_user_regs 384 sub sp, sp, #S_FRAME_SIZE 385 stmia sp, {r0 - r12} @ Calling r0-r12 386 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 387 stmdb r8, {sp, lr}^ @ Calling SP, LR 388 str lr, [r8, #0] @ Save calling PC 389 mrs r6, spsr 390 str r6, [r8, #4] @ Save CPSR 391 str r0, [r8, #8] @ Save OLD_R0 392 mov r0, sp 393 .endm 394 395 .macro irq_restore_user_regs 396 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 397 mov r0, r0 398 ldr lr, [sp, #S_PC] @ Get PC 399 add sp, sp, #S_FRAME_SIZE 400 subs pc, lr, #4 @ return & move spsr_svc into cpsr 401 .endm 402 403 .macro get_bad_stack 404 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 405 406 str lr, [r13] @ save caller lr in position 0 of saved stack 407 mrs lr, spsr @ get the spsr 408 str lr, [r13, #4] @ save spsr in position 1 of saved stack 409 410 mov r13, #MODE_SVC @ prepare SVC-Mode 411 @ msr spsr_c, r13 412 msr spsr, r13 @ switch modes, make sure moves will execute 413 mov lr, pc @ capture return pc 414 movs pc, lr @ jump to next instruction & switch modes. 415 .endm 416 417 .macro get_bad_stack_swi 418 sub r13, r13, #4 @ space on current stack for scratch reg. 419 str r0, [r13] @ save R0's value. 420 ldr r0, IRQ_STACK_START_IN @ get data regions start 421 str lr, [r0] @ save caller lr in position 0 of saved stack 422 mrs r0, spsr @ get the spsr 423 str lr, [r0, #4] @ save spsr in position 1 of saved stack 424 ldr r0, [r13] @ restore r0 425 add r13, r13, #4 @ pop stack entry 426 .endm 427 428 .macro get_irq_stack @ setup IRQ stack 429 ldr sp, IRQ_STACK_START 430 .endm 431 432 .macro get_fiq_stack @ setup FIQ stack 433 ldr sp, FIQ_STACK_START 434 .endm 435#endif /* CONFIG_PRELOADER */ 436 437/* 438 * exception handlers 439 */ 440#ifdef CONFIG_PRELOADER 441 .align 5 442do_hang: 443 ldr sp, _TEXT_BASE /* use 32 words about stack */ 444 bl hang /* hang and never return */ 445#else /* !CONFIG_PRELOADER */ 446 .align 5 447undefined_instruction: 448 get_bad_stack 449 bad_save_user_regs 450 bl do_undefined_instruction 451 452 .align 5 453software_interrupt: 454 get_bad_stack_swi 455 bad_save_user_regs 456 bl do_software_interrupt 457 458 .align 5 459prefetch_abort: 460 get_bad_stack 461 bad_save_user_regs 462 bl do_prefetch_abort 463 464 .align 5 465data_abort: 466 get_bad_stack 467 bad_save_user_regs 468 bl do_data_abort 469 470 .align 5 471not_used: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_not_used 475 476#ifdef CONFIG_USE_IRQ 477 478 .align 5 479irq: 480 get_irq_stack 481 irq_save_user_regs 482 bl do_irq 483 irq_restore_user_regs 484 485 .align 5 486fiq: 487 get_fiq_stack 488 /* someone ought to write a more effiction fiq_save_user_regs */ 489 irq_save_user_regs 490 bl do_fiq 491 irq_restore_user_regs 492 493#else 494 495 .align 5 496irq: 497 get_bad_stack 498 bad_save_user_regs 499 bl do_irq 500 501 .align 5 502fiq: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_fiq 506 507#endif 508 .align 5 509.global arm1136_cache_flush 510arm1136_cache_flush: 511#if !defined(CONFIG_SYS_NO_ICACHE) 512 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 513#endif 514#if !defined(CONFIG_SYS_NO_DCACHE) 515 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 516#endif 517 mov pc, lr @ back to caller 518#endif /* CONFIG_PRELOADER */ 519