1*88ae27edSEugeniy Paltsev /* 2*88ae27edSEugeniy Paltsev * ARC Build Configuration Registers, with encoded hardware config 3*88ae27edSEugeniy Paltsev * 4*88ae27edSEugeniy Paltsev * Copyright (C) 2018 Synopsys 5*88ae27edSEugeniy Paltsev * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 6*88ae27edSEugeniy Paltsev * 7*88ae27edSEugeniy Paltsev * This file is licensed under the terms of the GNU General Public 8*88ae27edSEugeniy Paltsev * License version 2. This program is licensed "as is" without any 9*88ae27edSEugeniy Paltsev * warranty of any kind, whether express or implied. 10*88ae27edSEugeniy Paltsev */ 11*88ae27edSEugeniy Paltsev 12*88ae27edSEugeniy Paltsev #ifndef __ARC_BCR_H 13*88ae27edSEugeniy Paltsev #define __ARC_BCR_H 14*88ae27edSEugeniy Paltsev #ifndef __ASSEMBLY__ 15*88ae27edSEugeniy Paltsev 16*88ae27edSEugeniy Paltsev #include <config.h> 17*88ae27edSEugeniy Paltsev 18*88ae27edSEugeniy Paltsev union bcr_di_cache { 19*88ae27edSEugeniy Paltsev struct { 20*88ae27edSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 21*88ae27edSEugeniy Paltsev unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 22*88ae27edSEugeniy Paltsev #else 23*88ae27edSEugeniy Paltsev unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 24*88ae27edSEugeniy Paltsev #endif 25*88ae27edSEugeniy Paltsev } fields; 26*88ae27edSEugeniy Paltsev unsigned int word; 27*88ae27edSEugeniy Paltsev }; 28*88ae27edSEugeniy Paltsev 29*88ae27edSEugeniy Paltsev union bcr_slc_cfg { 30*88ae27edSEugeniy Paltsev struct { 31*88ae27edSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 32*88ae27edSEugeniy Paltsev unsigned int pad:24, way:2, lsz:2, sz:4; 33*88ae27edSEugeniy Paltsev #else 34*88ae27edSEugeniy Paltsev unsigned int sz:4, lsz:2, way:2, pad:24; 35*88ae27edSEugeniy Paltsev #endif 36*88ae27edSEugeniy Paltsev } fields; 37*88ae27edSEugeniy Paltsev unsigned int word; 38*88ae27edSEugeniy Paltsev }; 39*88ae27edSEugeniy Paltsev 40*88ae27edSEugeniy Paltsev union bcr_generic { 41*88ae27edSEugeniy Paltsev struct { 42*88ae27edSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 43*88ae27edSEugeniy Paltsev unsigned int pad:24, ver:8; 44*88ae27edSEugeniy Paltsev #else 45*88ae27edSEugeniy Paltsev unsigned int ver:8, pad:24; 46*88ae27edSEugeniy Paltsev #endif 47*88ae27edSEugeniy Paltsev } fields; 48*88ae27edSEugeniy Paltsev unsigned int word; 49*88ae27edSEugeniy Paltsev }; 50*88ae27edSEugeniy Paltsev 51*88ae27edSEugeniy Paltsev union bcr_clust_cfg { 52*88ae27edSEugeniy Paltsev struct { 53*88ae27edSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 54*88ae27edSEugeniy Paltsev unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; 55*88ae27edSEugeniy Paltsev #else 56*88ae27edSEugeniy Paltsev unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; 57*88ae27edSEugeniy Paltsev #endif 58*88ae27edSEugeniy Paltsev } fields; 59*88ae27edSEugeniy Paltsev unsigned int word; 60*88ae27edSEugeniy Paltsev }; 61*88ae27edSEugeniy Paltsev 62*88ae27edSEugeniy Paltsev union bcr_mmu_4 { 63*88ae27edSEugeniy Paltsev struct { 64*88ae27edSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 65*88ae27edSEugeniy Paltsev unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, 66*88ae27edSEugeniy Paltsev n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; 67*88ae27edSEugeniy Paltsev #else 68*88ae27edSEugeniy Paltsev /* DTLB ITLB JES JE JA */ 69*88ae27edSEugeniy Paltsev unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, 70*88ae27edSEugeniy Paltsev pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; 71*88ae27edSEugeniy Paltsev #endif 72*88ae27edSEugeniy Paltsev } fields; 73*88ae27edSEugeniy Paltsev unsigned int word; 74*88ae27edSEugeniy Paltsev }; 75*88ae27edSEugeniy Paltsev 76*88ae27edSEugeniy Paltsev #endif /* __ASSEMBLY__ */ 77*88ae27edSEugeniy Paltsev #endif /* __ARC_BCR_H */ 78