1*5396e8b1SAlexey Brodkin// SPDX-License-Identifier: GPL-2.0+ 2*5396e8b1SAlexey Brodkin/* 3*5396e8b1SAlexey Brodkin * Copyright (C) 2018 Synopsys, Inc. All rights reserved. 4*5396e8b1SAlexey Brodkin */ 5*5396e8b1SAlexey Brodkin/dts-v1/; 6*5396e8b1SAlexey Brodkin 7*5396e8b1SAlexey Brodkin#include "skeleton.dtsi" 8*5396e8b1SAlexey Brodkin 9*5396e8b1SAlexey Brodkin/ { 10*5396e8b1SAlexey Brodkin #address-cells = <1>; 11*5396e8b1SAlexey Brodkin #size-cells = <1>; 12*5396e8b1SAlexey Brodkin 13*5396e8b1SAlexey Brodkin aliases { 14*5396e8b1SAlexey Brodkin console = &uart0; 15*5396e8b1SAlexey Brodkin }; 16*5396e8b1SAlexey Brodkin 17*5396e8b1SAlexey Brodkin cpu_card { 18*5396e8b1SAlexey Brodkin core_clk: core_clk { 19*5396e8b1SAlexey Brodkin #clock-cells = <0>; 20*5396e8b1SAlexey Brodkin compatible = "fixed-clock"; 21*5396e8b1SAlexey Brodkin clock-frequency = <144000000>; 22*5396e8b1SAlexey Brodkin u-boot,dm-pre-reloc; 23*5396e8b1SAlexey Brodkin }; 24*5396e8b1SAlexey Brodkin }; 25*5396e8b1SAlexey Brodkin 26*5396e8b1SAlexey Brodkin uart0: serial0@80014000 { 27*5396e8b1SAlexey Brodkin compatible = "snps,dw-apb-uart"; 28*5396e8b1SAlexey Brodkin clock-frequency = <16000000>; 29*5396e8b1SAlexey Brodkin reg = <0x80014000 0x1000>; 30*5396e8b1SAlexey Brodkin reg-shift = <2>; 31*5396e8b1SAlexey Brodkin reg-io-width = <4>; 32*5396e8b1SAlexey Brodkin }; 33*5396e8b1SAlexey Brodkin 34*5396e8b1SAlexey Brodkin usb: usb@f0040000 { 35*5396e8b1SAlexey Brodkin compatible = "snps,dwc2"; 36*5396e8b1SAlexey Brodkin reg = <0xf0040000 0x10000>; 37*5396e8b1SAlexey Brodkin phys = <&usbphy>; 38*5396e8b1SAlexey Brodkin phy-names = "usb2-phy"; 39*5396e8b1SAlexey Brodkin }; 40*5396e8b1SAlexey Brodkin 41*5396e8b1SAlexey Brodkin usbphy: phy { 42*5396e8b1SAlexey Brodkin compatible = "nop-phy"; 43*5396e8b1SAlexey Brodkin #phy-cells = <0>; 44*5396e8b1SAlexey Brodkin }; 45*5396e8b1SAlexey Brodkin}; 46