1*adc9b09aSAlexey Brodkin// SPDX-License-Identifier: GPL-2.0+ 2*adc9b09aSAlexey Brodkin/* 3*adc9b09aSAlexey Brodkin * Copyright (C) 2018 Synopsys, Inc. All rights reserved. 4*adc9b09aSAlexey Brodkin */ 5*adc9b09aSAlexey Brodkin/dts-v1/; 6*adc9b09aSAlexey Brodkin 7*adc9b09aSAlexey Brodkin#include "skeleton.dtsi" 8*adc9b09aSAlexey Brodkin 9*adc9b09aSAlexey Brodkin/ { 10*adc9b09aSAlexey Brodkin model = "snps,emsdp"; 11*adc9b09aSAlexey Brodkin 12*adc9b09aSAlexey Brodkin #address-cells = <1>; 13*adc9b09aSAlexey Brodkin #size-cells = <1>; 14*adc9b09aSAlexey Brodkin 15*adc9b09aSAlexey Brodkin aliases { 16*adc9b09aSAlexey Brodkin console = &uart0; 17*adc9b09aSAlexey Brodkin }; 18*adc9b09aSAlexey Brodkin 19*adc9b09aSAlexey Brodkin cpu_card { 20*adc9b09aSAlexey Brodkin core_clk: core_clk { 21*adc9b09aSAlexey Brodkin #clock-cells = <0>; 22*adc9b09aSAlexey Brodkin compatible = "fixed-clock"; 23*adc9b09aSAlexey Brodkin clock-frequency = <40000000>; 24*adc9b09aSAlexey Brodkin u-boot,dm-pre-reloc; 25*adc9b09aSAlexey Brodkin }; 26*adc9b09aSAlexey Brodkin }; 27*adc9b09aSAlexey Brodkin 28*adc9b09aSAlexey Brodkin uart0: serial0@f0004000 { 29*adc9b09aSAlexey Brodkin compatible = "snps,dw-apb-uart"; 30*adc9b09aSAlexey Brodkin clock-frequency = <100000000>; 31*adc9b09aSAlexey Brodkin reg = <0xf0004000 0x1000>; 32*adc9b09aSAlexey Brodkin reg-shift = <2>; 33*adc9b09aSAlexey Brodkin reg-io-width = <4>; 34*adc9b09aSAlexey Brodkin }; 35*adc9b09aSAlexey Brodkin}; 36