xref: /openbmc/qemu/tests/tcg/s390x/precise-smc-softmmu.S (revision 2d8fbcb1eecd8d39171f457e583428758321d69d)
1*c3513ce5SIlya Leoshkevich/*
2*c3513ce5SIlya Leoshkevich * Test s390x-softmmu precise self-modifying code handling.
3*c3513ce5SIlya Leoshkevich *
4*c3513ce5SIlya Leoshkevich * SPDX-License-Identifier: GPL-2.0-or-later
5*c3513ce5SIlya Leoshkevich */
6*c3513ce5SIlya Leoshkevich    .org 0x8e
7*c3513ce5SIlya Leoshkevichprogram_interruption_code:
8*c3513ce5SIlya Leoshkevich    .org 0x150
9*c3513ce5SIlya Leoshkevichprogram_old_psw:
10*c3513ce5SIlya Leoshkevich    .org 0x1D0                         /* program new PSW */
11*c3513ce5SIlya Leoshkevich    .quad 0x180000000,pgm              /* 64-bit mode */
12*c3513ce5SIlya Leoshkevich    .org 0x200                         /* lowcore padding */
13*c3513ce5SIlya Leoshkevich    .globl _start
14*c3513ce5SIlya Leoshkevich_start:
15*c3513ce5SIlya Leoshkevich    lctlg %c0,%c0,c0
16*c3513ce5SIlya Leoshkevich    lghi %r0,15
17*c3513ce5SIlya Leoshkevich
18*c3513ce5SIlya Leoshkevich    /* Test 1: replace sgr with agr. */
19*c3513ce5SIlya Leoshkevich    lghi %r1,21
20*c3513ce5SIlya Leoshkevich    vl %v0,patch1
21*c3513ce5SIlya Leoshkevich    jg 1f                              /* start a new TB */
22*c3513ce5SIlya Leoshkevich0:
23*c3513ce5SIlya Leoshkevich    .org . + 6                         /* pad patched code to 16 bytes */
24*c3513ce5SIlya Leoshkevich1:
25*c3513ce5SIlya Leoshkevich    vstl %v0,%r0,0b                    /* start writing before TB */
26*c3513ce5SIlya Leoshkevich    sgr %r1,%r1                        /* this becomes `agr %r1,%r1` */
27*c3513ce5SIlya Leoshkevich    cgijne %r1,42,failure
28*c3513ce5SIlya Leoshkevich
29*c3513ce5SIlya Leoshkevich    /* Test 2: replace agr with division by zero. */
30*c3513ce5SIlya Leoshkevich    vl %v0,patch2
31*c3513ce5SIlya Leoshkevich    jg 1f                              /* start a new TB */
32*c3513ce5SIlya Leoshkevich0:
33*c3513ce5SIlya Leoshkevich    .org . + 6                         /* pad patched code to 16 bytes */
34*c3513ce5SIlya Leoshkevich1:
35*c3513ce5SIlya Leoshkevich    vstl %v0,%r0,0b                    /* start writing before TB */
36*c3513ce5SIlya Leoshkevich    sgr %r1,%r1                        /* this becomes `d %r0,zero` */
37*c3513ce5SIlya Leoshkevichfailure:
38*c3513ce5SIlya Leoshkevich    lpswe failure_psw
39*c3513ce5SIlya Leoshkevich
40*c3513ce5SIlya Leoshkevichpgm:
41*c3513ce5SIlya Leoshkevich    chhsi program_interruption_code,0x9          /* divide exception? */
42*c3513ce5SIlya Leoshkevich    jne failure
43*c3513ce5SIlya Leoshkevich    clc program_old_psw(16),expected_old_psw2    /* correct old PSW? */
44*c3513ce5SIlya Leoshkevich    jne failure
45*c3513ce5SIlya Leoshkevich    lpswe success_psw
46*c3513ce5SIlya Leoshkevich
47*c3513ce5SIlya Leoshkevichpatch1:
48*c3513ce5SIlya Leoshkevich    .fill 12                           /* replaces padding and stpq */
49*c3513ce5SIlya Leoshkevich    agr %r1,%r1                        /* replaces sgr */
50*c3513ce5SIlya Leoshkevichpatch2:
51*c3513ce5SIlya Leoshkevich    .fill 12                           /* replaces padding and stpq */
52*c3513ce5SIlya Leoshkevich    d %r0,zero                         /* replaces sgr */
53*c3513ce5SIlya Leoshkevichzero:
54*c3513ce5SIlya Leoshkevich    .long 0
55*c3513ce5SIlya Leoshkevichexpected_old_psw2:
56*c3513ce5SIlya Leoshkevich    .quad 0x200180000000,failure       /* cc is from addition */
57*c3513ce5SIlya Leoshkevich    .align 8
58*c3513ce5SIlya Leoshkevichc0:
59*c3513ce5SIlya Leoshkevich    .quad 0x60000                      /* AFP, VX */
60*c3513ce5SIlya Leoshkevichsuccess_psw:
61*c3513ce5SIlya Leoshkevich    .quad 0x2000000000000,0xfff        /* see is_special_wait_psw() */
62*c3513ce5SIlya Leoshkevichfailure_psw:
63*c3513ce5SIlya Leoshkevich    .quad 0x2000000000000,0            /* disabled wait */
64