1*fa8718c7SRichard Henderson .org 0x8d 2*fa8718c7SRichard Hendersonilc: 3*fa8718c7SRichard Henderson .org 0x8e 4*fa8718c7SRichard Hendersonprogram_interruption_code: 5*fa8718c7SRichard Henderson .org 0x96 6*fa8718c7SRichard Hendersonper_code: 7*fa8718c7SRichard Henderson .org 0x98 8*fa8718c7SRichard Hendersonper_address: 9*fa8718c7SRichard Henderson .org 0x150 10*fa8718c7SRichard Hendersonprogram_old_psw: 11*fa8718c7SRichard Henderson .org 0x1d0 12*fa8718c7SRichard Hendersonprogram_new_psw: 13*fa8718c7SRichard Henderson .quad 0, pgm_handler 14*fa8718c7SRichard Henderson 15*fa8718c7SRichard Henderson .org 0x200 /* exit lowcore */ 16*fa8718c7SRichard Henderson 17*fa8718c7SRichard Hendersonper_on_psw: 18*fa8718c7SRichard Henderson .quad 0x4000000000000000, start_per 19*fa8718c7SRichard Hendersonper_on_regs: 20*fa8718c7SRichard Henderson .quad 0x80000000, 0, -1 /* successful-branching everywhere */ 21*fa8718c7SRichard Hendersonper_off_regs: 22*fa8718c7SRichard Henderson .quad 0, 0 ,0 23*fa8718c7SRichard Hendersonsuccess_psw: 24*fa8718c7SRichard Henderson .quad 0x2000000000000, 0xfff /* see is_special_wait_psw() */ 25*fa8718c7SRichard Hendersonfailure_psw: 26*fa8718c7SRichard Henderson .quad 0x2000000000000, 0 /* disabled wait */ 27*fa8718c7SRichard Henderson 28*fa8718c7SRichard Henderson .org 0x2000 /* exit lowcore pages */ 29*fa8718c7SRichard Henderson 30*fa8718c7SRichard Henderson .globl _start 31*fa8718c7SRichard Henderson_start: 32*fa8718c7SRichard Henderson lpswe per_on_psw 33*fa8718c7SRichard Hendersonstart_per: 34*fa8718c7SRichard Henderson lctlg %c9, %c11, per_on_regs 35*fa8718c7SRichard Henderson 36*fa8718c7SRichard Henderson/* Test unconditional relative branch. */ 37*fa8718c7SRichard Henderson larl %r0, j1 38*fa8718c7SRichard Henderson larl %r1, d1 39*fa8718c7SRichard Henderson lhi %r2, 0 40*fa8718c7SRichard Hendersonj1: j d1 41*fa8718c7SRichard Henderson lpswe failure_psw 42*fa8718c7SRichard Hendersond1: 43*fa8718c7SRichard Henderson 44*fa8718c7SRichard Henderson/* Test unconditional indirect branch. */ 45*fa8718c7SRichard Henderson larl %r0, j2 46*fa8718c7SRichard Henderson larl %r1, d2 47*fa8718c7SRichard Hendersonj2: br %r1 48*fa8718c7SRichard Henderson lpswe failure_psw 49*fa8718c7SRichard Hendersond2: 50*fa8718c7SRichard Henderson 51*fa8718c7SRichard Henderson/* Test conditional relative branch. */ 52*fa8718c7SRichard Henderson larl %r0, j3 53*fa8718c7SRichard Henderson larl %r1, d3 54*fa8718c7SRichard Henderson clr %r1, %r2 /* d3 != 0 */ 55*fa8718c7SRichard Hendersonj3: jne d3 56*fa8718c7SRichard Henderson lpswe failure_psw 57*fa8718c7SRichard Hendersond3: 58*fa8718c7SRichard Henderson 59*fa8718c7SRichard Henderson/* Test conditional register branch. */ 60*fa8718c7SRichard Henderson larl %r0, j4 61*fa8718c7SRichard Henderson larl %r1, d4 62*fa8718c7SRichard Henderson clr %r1, %r2 /* d4 != 0 */ 63*fa8718c7SRichard Hendersonj4: bner %r1 64*fa8718c7SRichard Henderson lpswe failure_psw 65*fa8718c7SRichard Hendersond4: 66*fa8718c7SRichard Henderson 67*fa8718c7SRichard Henderson/* Success! */ 68*fa8718c7SRichard Henderson nop 69*fa8718c7SRichard Henderson lpswe success_psw 70*fa8718c7SRichard Henderson 71*fa8718c7SRichard Hendersonpgm_handler: 72*fa8718c7SRichard Henderson chhsi program_interruption_code, 0x80 /* PER event? */ 73*fa8718c7SRichard Henderson jne fail 74*fa8718c7SRichard Henderson cli per_code, 0x80 /* successful-branching event? */ 75*fa8718c7SRichard Henderson jne fail 76*fa8718c7SRichard Henderson clg %r0, per_address /* per_address == jump insn? */ 77*fa8718c7SRichard Henderson jne fail 78*fa8718c7SRichard Henderson clg %r1, program_old_psw+8 /* psw.addr updated to dest? */ 79*fa8718c7SRichard Henderson jne fail 80*fa8718c7SRichard Henderson lpswe program_old_psw 81*fa8718c7SRichard Hendersonfail: 82*fa8718c7SRichard Henderson lpswe failure_psw 83