14d2cd2d8SGlenn Miles /* 24d2cd2d8SGlenn Miles * PowerNV XSCOM Bus 34d2cd2d8SGlenn Miles * 44d2cd2d8SGlenn Miles * Copyright (c) 2024, IBM Corporation. 54d2cd2d8SGlenn Miles * 64d2cd2d8SGlenn Miles * SPDX-License-Identifier: GPL-2.0-or-later 74d2cd2d8SGlenn Miles */ 84d2cd2d8SGlenn Miles 94d2cd2d8SGlenn Miles #ifndef PNV_XSCOM_H 104d2cd2d8SGlenn Miles #define PNV_XSCOM_H 114d2cd2d8SGlenn Miles 124d2cd2d8SGlenn Miles #define SMT 4 /* some tests will break if less than 4 */ 134d2cd2d8SGlenn Miles 144d2cd2d8SGlenn Miles typedef enum PnvChipType { 154d2cd2d8SGlenn Miles PNV_CHIP_POWER8E, /* AKA Murano (default) */ 164d2cd2d8SGlenn Miles PNV_CHIP_POWER8, /* AKA Venice */ 174d2cd2d8SGlenn Miles PNV_CHIP_POWER8NVL, /* AKA Naples */ 184d2cd2d8SGlenn Miles PNV_CHIP_POWER9, /* AKA Nimbus */ 194d2cd2d8SGlenn Miles PNV_CHIP_POWER10, 204d2cd2d8SGlenn Miles } PnvChipType; 214d2cd2d8SGlenn Miles 224d2cd2d8SGlenn Miles typedef struct PnvChip { 234d2cd2d8SGlenn Miles PnvChipType chip_type; 244d2cd2d8SGlenn Miles const char *cpu_model; 254d2cd2d8SGlenn Miles uint64_t xscom_base; 264d2cd2d8SGlenn Miles uint64_t cfam_id; 274d2cd2d8SGlenn Miles uint32_t first_core; 284d2cd2d8SGlenn Miles uint32_t num_i2c; 294d2cd2d8SGlenn Miles } PnvChip; 304d2cd2d8SGlenn Miles 314d2cd2d8SGlenn Miles static const PnvChip pnv_chips[] = { 324d2cd2d8SGlenn Miles { 334d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER8, 344d2cd2d8SGlenn Miles .cpu_model = "POWER8", 354d2cd2d8SGlenn Miles .xscom_base = 0x0003fc0000000000ull, 364d2cd2d8SGlenn Miles .cfam_id = 0x220ea04980000000ull, 374d2cd2d8SGlenn Miles .first_core = 0x1, 384d2cd2d8SGlenn Miles .num_i2c = 0, 394d2cd2d8SGlenn Miles }, { 404d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER8NVL, 414d2cd2d8SGlenn Miles .cpu_model = "POWER8NVL", 424d2cd2d8SGlenn Miles .xscom_base = 0x0003fc0000000000ull, 434d2cd2d8SGlenn Miles .cfam_id = 0x120d304980000000ull, 444d2cd2d8SGlenn Miles .first_core = 0x1, 454d2cd2d8SGlenn Miles .num_i2c = 0, 464d2cd2d8SGlenn Miles }, 474d2cd2d8SGlenn Miles { 484d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER9, 494d2cd2d8SGlenn Miles .cpu_model = "POWER9", 504d2cd2d8SGlenn Miles .xscom_base = 0x000603fc00000000ull, 514d2cd2d8SGlenn Miles .cfam_id = 0x220d104900008000ull, 524d2cd2d8SGlenn Miles .first_core = 0x0, 534d2cd2d8SGlenn Miles .num_i2c = 4, 544d2cd2d8SGlenn Miles }, 554d2cd2d8SGlenn Miles { 564d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER10, 574d2cd2d8SGlenn Miles .cpu_model = "POWER10", 584d2cd2d8SGlenn Miles .xscom_base = 0x000603fc00000000ull, 59*977e789cSAditya Gupta .cfam_id = 0x220da04980000000ull, 604d2cd2d8SGlenn Miles .first_core = 0x0, 614d2cd2d8SGlenn Miles .num_i2c = 4, 624d2cd2d8SGlenn Miles }, 634d2cd2d8SGlenn Miles }; 644d2cd2d8SGlenn Miles 654d2cd2d8SGlenn Miles static inline uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba) 664d2cd2d8SGlenn Miles { 674d2cd2d8SGlenn Miles uint64_t addr = chip->xscom_base; 684d2cd2d8SGlenn Miles 694d2cd2d8SGlenn Miles if (chip->chip_type == PNV_CHIP_POWER10) { 704d2cd2d8SGlenn Miles addr |= ((uint64_t) pcba << 3); 714d2cd2d8SGlenn Miles } else if (chip->chip_type == PNV_CHIP_POWER9) { 724d2cd2d8SGlenn Miles addr |= ((uint64_t) pcba << 3); 734d2cd2d8SGlenn Miles } else { 744d2cd2d8SGlenn Miles addr |= (((uint64_t) pcba << 4) & ~0xffull) | 754d2cd2d8SGlenn Miles (((uint64_t) pcba << 3) & 0x78); 764d2cd2d8SGlenn Miles } 774d2cd2d8SGlenn Miles return addr; 784d2cd2d8SGlenn Miles } 794d2cd2d8SGlenn Miles 804d2cd2d8SGlenn Miles #endif /* PNV_XSCOM_H */ 81