1*4d2cd2d8SGlenn Miles /* 2*4d2cd2d8SGlenn Miles * PowerNV XSCOM Bus 3*4d2cd2d8SGlenn Miles * 4*4d2cd2d8SGlenn Miles * Copyright (c) 2024, IBM Corporation. 5*4d2cd2d8SGlenn Miles * 6*4d2cd2d8SGlenn Miles * SPDX-License-Identifier: GPL-2.0-or-later 7*4d2cd2d8SGlenn Miles */ 8*4d2cd2d8SGlenn Miles 9*4d2cd2d8SGlenn Miles #ifndef PNV_XSCOM_H 10*4d2cd2d8SGlenn Miles #define PNV_XSCOM_H 11*4d2cd2d8SGlenn Miles 12*4d2cd2d8SGlenn Miles #define SMT 4 /* some tests will break if less than 4 */ 13*4d2cd2d8SGlenn Miles 14*4d2cd2d8SGlenn Miles typedef enum PnvChipType { 15*4d2cd2d8SGlenn Miles PNV_CHIP_POWER8E, /* AKA Murano (default) */ 16*4d2cd2d8SGlenn Miles PNV_CHIP_POWER8, /* AKA Venice */ 17*4d2cd2d8SGlenn Miles PNV_CHIP_POWER8NVL, /* AKA Naples */ 18*4d2cd2d8SGlenn Miles PNV_CHIP_POWER9, /* AKA Nimbus */ 19*4d2cd2d8SGlenn Miles PNV_CHIP_POWER10, 20*4d2cd2d8SGlenn Miles } PnvChipType; 21*4d2cd2d8SGlenn Miles 22*4d2cd2d8SGlenn Miles typedef struct PnvChip { 23*4d2cd2d8SGlenn Miles PnvChipType chip_type; 24*4d2cd2d8SGlenn Miles const char *cpu_model; 25*4d2cd2d8SGlenn Miles uint64_t xscom_base; 26*4d2cd2d8SGlenn Miles uint64_t cfam_id; 27*4d2cd2d8SGlenn Miles uint32_t first_core; 28*4d2cd2d8SGlenn Miles uint32_t num_i2c; 29*4d2cd2d8SGlenn Miles } PnvChip; 30*4d2cd2d8SGlenn Miles 31*4d2cd2d8SGlenn Miles static const PnvChip pnv_chips[] = { 32*4d2cd2d8SGlenn Miles { 33*4d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER8, 34*4d2cd2d8SGlenn Miles .cpu_model = "POWER8", 35*4d2cd2d8SGlenn Miles .xscom_base = 0x0003fc0000000000ull, 36*4d2cd2d8SGlenn Miles .cfam_id = 0x220ea04980000000ull, 37*4d2cd2d8SGlenn Miles .first_core = 0x1, 38*4d2cd2d8SGlenn Miles .num_i2c = 0, 39*4d2cd2d8SGlenn Miles }, { 40*4d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER8NVL, 41*4d2cd2d8SGlenn Miles .cpu_model = "POWER8NVL", 42*4d2cd2d8SGlenn Miles .xscom_base = 0x0003fc0000000000ull, 43*4d2cd2d8SGlenn Miles .cfam_id = 0x120d304980000000ull, 44*4d2cd2d8SGlenn Miles .first_core = 0x1, 45*4d2cd2d8SGlenn Miles .num_i2c = 0, 46*4d2cd2d8SGlenn Miles }, 47*4d2cd2d8SGlenn Miles { 48*4d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER9, 49*4d2cd2d8SGlenn Miles .cpu_model = "POWER9", 50*4d2cd2d8SGlenn Miles .xscom_base = 0x000603fc00000000ull, 51*4d2cd2d8SGlenn Miles .cfam_id = 0x220d104900008000ull, 52*4d2cd2d8SGlenn Miles .first_core = 0x0, 53*4d2cd2d8SGlenn Miles .num_i2c = 4, 54*4d2cd2d8SGlenn Miles }, 55*4d2cd2d8SGlenn Miles { 56*4d2cd2d8SGlenn Miles .chip_type = PNV_CHIP_POWER10, 57*4d2cd2d8SGlenn Miles .cpu_model = "POWER10", 58*4d2cd2d8SGlenn Miles .xscom_base = 0x000603fc00000000ull, 59*4d2cd2d8SGlenn Miles .cfam_id = 0x120da04900008000ull, 60*4d2cd2d8SGlenn Miles .first_core = 0x0, 61*4d2cd2d8SGlenn Miles .num_i2c = 4, 62*4d2cd2d8SGlenn Miles }, 63*4d2cd2d8SGlenn Miles }; 64*4d2cd2d8SGlenn Miles 65*4d2cd2d8SGlenn Miles static inline uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba) 66*4d2cd2d8SGlenn Miles { 67*4d2cd2d8SGlenn Miles uint64_t addr = chip->xscom_base; 68*4d2cd2d8SGlenn Miles 69*4d2cd2d8SGlenn Miles if (chip->chip_type == PNV_CHIP_POWER10) { 70*4d2cd2d8SGlenn Miles addr |= ((uint64_t) pcba << 3); 71*4d2cd2d8SGlenn Miles } else if (chip->chip_type == PNV_CHIP_POWER9) { 72*4d2cd2d8SGlenn Miles addr |= ((uint64_t) pcba << 3); 73*4d2cd2d8SGlenn Miles } else { 74*4d2cd2d8SGlenn Miles addr |= (((uint64_t) pcba << 4) & ~0xffull) | 75*4d2cd2d8SGlenn Miles (((uint64_t) pcba << 3) & 0x78); 76*4d2cd2d8SGlenn Miles } 77*4d2cd2d8SGlenn Miles return addr; 78*4d2cd2d8SGlenn Miles } 79*4d2cd2d8SGlenn Miles 80*4d2cd2d8SGlenn Miles #endif /* PNV_XSCOM_H */ 81