1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* We only support generating code for 64-bit mode. */ 26#ifndef __arch64__ 27#error "unsupported code generation mode" 28#endif 29 30#include "../tcg-ldst.c.inc" 31#include "../tcg-pool.c.inc" 32 33#ifdef CONFIG_DEBUG_TCG 34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 35 "%g0", 36 "%g1", 37 "%g2", 38 "%g3", 39 "%g4", 40 "%g5", 41 "%g6", 42 "%g7", 43 "%o0", 44 "%o1", 45 "%o2", 46 "%o3", 47 "%o4", 48 "%o5", 49 "%o6", 50 "%o7", 51 "%l0", 52 "%l1", 53 "%l2", 54 "%l3", 55 "%l4", 56 "%l5", 57 "%l6", 58 "%l7", 59 "%i0", 60 "%i1", 61 "%i2", 62 "%i3", 63 "%i4", 64 "%i5", 65 "%i6", 66 "%i7", 67}; 68#endif 69 70#define TCG_CT_CONST_S11 0x100 71#define TCG_CT_CONST_S13 0x200 72#define TCG_CT_CONST_ZERO 0x400 73 74#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 75 76/* Define some temporary registers. T3 is used for constant generation. */ 77#define TCG_REG_T1 TCG_REG_G1 78#define TCG_REG_T2 TCG_REG_G2 79#define TCG_REG_T3 TCG_REG_O7 80 81#ifndef CONFIG_SOFTMMU 82# define TCG_GUEST_BASE_REG TCG_REG_I5 83#endif 84 85#define TCG_REG_TB TCG_REG_I1 86 87static const int tcg_target_reg_alloc_order[] = { 88 TCG_REG_L0, 89 TCG_REG_L1, 90 TCG_REG_L2, 91 TCG_REG_L3, 92 TCG_REG_L4, 93 TCG_REG_L5, 94 TCG_REG_L6, 95 TCG_REG_L7, 96 97 TCG_REG_I0, 98 TCG_REG_I1, 99 TCG_REG_I2, 100 TCG_REG_I3, 101 TCG_REG_I4, 102 TCG_REG_I5, 103 104 TCG_REG_G3, 105 TCG_REG_G4, 106 TCG_REG_G5, 107 108 TCG_REG_O0, 109 TCG_REG_O1, 110 TCG_REG_O2, 111 TCG_REG_O3, 112 TCG_REG_O4, 113 TCG_REG_O5, 114}; 115 116static const int tcg_target_call_iarg_regs[6] = { 117 TCG_REG_O0, 118 TCG_REG_O1, 119 TCG_REG_O2, 120 TCG_REG_O3, 121 TCG_REG_O4, 122 TCG_REG_O5, 123}; 124 125static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 126{ 127 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 128 tcg_debug_assert(slot >= 0 && slot <= 3); 129 return TCG_REG_O0 + slot; 130} 131 132#define INSN_OP(x) ((x) << 30) 133#define INSN_OP2(x) ((x) << 22) 134#define INSN_OP3(x) ((x) << 19) 135#define INSN_OPF(x) ((x) << 5) 136#define INSN_RD(x) ((x) << 25) 137#define INSN_RS1(x) ((x) << 14) 138#define INSN_RS2(x) (x) 139#define INSN_ASI(x) ((x) << 5) 140 141#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) 142#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) 143#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) 144#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) 145#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) 146#define INSN_COND(x) ((x) << 25) 147 148#define COND_N 0x0 149#define COND_E 0x1 150#define COND_LE 0x2 151#define COND_L 0x3 152#define COND_LEU 0x4 153#define COND_CS 0x5 154#define COND_NEG 0x6 155#define COND_VS 0x7 156#define COND_A 0x8 157#define COND_NE 0x9 158#define COND_G 0xa 159#define COND_GE 0xb 160#define COND_GU 0xc 161#define COND_CC 0xd 162#define COND_POS 0xe 163#define COND_VC 0xf 164#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) 165 166#define RCOND_Z 1 167#define RCOND_LEZ 2 168#define RCOND_LZ 3 169#define RCOND_NZ 5 170#define RCOND_GZ 6 171#define RCOND_GEZ 7 172 173#define MOVCC_ICC (1 << 18) 174#define MOVCC_XCC (1 << 18 | 1 << 12) 175 176#define BPCC_ICC 0 177#define BPCC_XCC (2 << 20) 178#define BPCC_PT (1 << 19) 179#define BPCC_PN 0 180#define BPCC_A (1 << 29) 181 182#define BPR_PT BPCC_PT 183 184#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) 185#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) 186#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) 187#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) 188#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) 189#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) 190#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) 191#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) 192#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) 193#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) 194#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) 195#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) 196#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) 197#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) 198#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) 199#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) 200#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) 201#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) 202#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) 203#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) 204#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) 205#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) 206 207#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) 208#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) 209 210#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) 211#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) 212#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) 213 214#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) 215#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) 216#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) 217 218#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) 219#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) 220#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) 221#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) 222#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) 223#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) 224#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) 225#define CALL INSN_OP(1) 226#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) 227#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) 228#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) 229#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) 230#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) 231#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) 232#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) 233#define STB (INSN_OP(3) | INSN_OP3(0x05)) 234#define STH (INSN_OP(3) | INSN_OP3(0x06)) 235#define STW (INSN_OP(3) | INSN_OP3(0x04)) 236#define STX (INSN_OP(3) | INSN_OP3(0x0e)) 237#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) 238#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) 239#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) 240#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) 241#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) 242#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) 243#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) 244#define STBA (INSN_OP(3) | INSN_OP3(0x15)) 245#define STHA (INSN_OP(3) | INSN_OP3(0x16)) 246#define STWA (INSN_OP(3) | INSN_OP3(0x14)) 247#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) 248 249#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) 250 251#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) 252 253#ifndef ASI_PRIMARY_LITTLE 254#define ASI_PRIMARY_LITTLE 0x88 255#endif 256 257#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 258#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 259#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 260#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 261#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 262 263#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 264#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 265#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 266 267#ifndef use_vis3_instructions 268bool use_vis3_instructions; 269#endif 270 271static bool check_fit_i64(int64_t val, unsigned int bits) 272{ 273 return val == sextract64(val, 0, bits); 274} 275 276static bool check_fit_i32(int32_t val, unsigned int bits) 277{ 278 return val == sextract32(val, 0, bits); 279} 280 281#define check_fit_tl check_fit_i64 282#define check_fit_ptr check_fit_i64 283 284static bool patch_reloc(tcg_insn_unit *src_rw, int type, 285 intptr_t value, intptr_t addend) 286{ 287 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 288 uint32_t insn = *src_rw; 289 intptr_t pcrel; 290 291 value += addend; 292 pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); 293 294 switch (type) { 295 case R_SPARC_WDISP16: 296 if (!check_fit_ptr(pcrel >> 2, 16)) { 297 return false; 298 } 299 insn &= ~INSN_OFF16(-1); 300 insn |= INSN_OFF16(pcrel); 301 break; 302 case R_SPARC_WDISP19: 303 if (!check_fit_ptr(pcrel >> 2, 19)) { 304 return false; 305 } 306 insn &= ~INSN_OFF19(-1); 307 insn |= INSN_OFF19(pcrel); 308 break; 309 case R_SPARC_13: 310 if (!check_fit_ptr(value, 13)) { 311 return false; 312 } 313 insn &= ~INSN_IMM13(-1); 314 insn |= INSN_IMM13(value); 315 break; 316 default: 317 g_assert_not_reached(); 318 } 319 320 *src_rw = insn; 321 return true; 322} 323 324/* test if a constant matches the constraint */ 325static bool tcg_target_const_match(int64_t val, int ct, 326 TCGType type, TCGCond cond, int vece) 327{ 328 if (ct & TCG_CT_CONST) { 329 return 1; 330 } 331 332 if (type == TCG_TYPE_I32) { 333 val = (int32_t)val; 334 } 335 336 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 337 return 1; 338 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { 339 return 1; 340 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { 341 return 1; 342 } else { 343 return 0; 344 } 345} 346 347static void tcg_out_nop(TCGContext *s) 348{ 349 tcg_out32(s, NOP); 350} 351 352static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, 353 TCGReg rs2, int op) 354{ 355 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); 356} 357 358static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, 359 int32_t offset, int op) 360{ 361 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); 362} 363 364static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, 365 int32_t val2, int val2const, int op) 366{ 367 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) 368 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); 369} 370 371static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 372{ 373 if (ret != arg) { 374 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 375 } 376 return true; 377} 378 379static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) 380{ 381 if (ret != arg) { 382 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 383 } else { 384 tcg_out_nop(s); 385 } 386} 387 388static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) 389{ 390 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); 391} 392 393/* A 13-bit constant sign-extended to 64 bits. */ 394static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) 395{ 396 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); 397} 398 399/* A 32-bit constant sign-extended to 64 bits. */ 400static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) 401{ 402 tcg_out_sethi(s, ret, ~arg); 403 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); 404} 405 406/* A 32-bit constant zero-extended to 64 bits. */ 407static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) 408{ 409 tcg_out_sethi(s, ret, arg); 410 if (arg & 0x3ff) { 411 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); 412 } 413} 414 415static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 416 tcg_target_long arg, bool in_prologue, 417 TCGReg scratch) 418{ 419 tcg_target_long hi, lo = (int32_t)arg; 420 tcg_target_long test, lsb; 421 422 /* A 13-bit constant sign-extended to 64-bits. */ 423 if (check_fit_tl(arg, 13)) { 424 tcg_out_movi_s13(s, ret, arg); 425 return; 426 } 427 428 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ 429 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { 430 tcg_out_movi_u32(s, ret, arg); 431 return; 432 } 433 434 /* A 13-bit constant relative to the TB. */ 435 if (!in_prologue) { 436 test = tcg_tbrel_diff(s, (void *)arg); 437 if (check_fit_ptr(test, 13)) { 438 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); 439 return; 440 } 441 } 442 443 /* A 32-bit constant sign-extended to 64-bits. */ 444 if (arg == lo) { 445 tcg_out_movi_s32(s, ret, arg); 446 return; 447 } 448 449 /* A 32-bit constant, shifted. */ 450 lsb = ctz64(arg); 451 test = (tcg_target_long)arg >> lsb; 452 if (lsb > 10 && test == extract64(test, 0, 21)) { 453 tcg_out_sethi(s, ret, test << 10); 454 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); 455 return; 456 } else if (test == (uint32_t)test || test == (int32_t)test) { 457 tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); 458 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); 459 return; 460 } 461 462 /* Use the constant pool, if possible. */ 463 if (!in_prologue) { 464 new_pool_label(s, arg, R_SPARC_13, s->code_ptr, 465 tcg_tbrel_diff(s, NULL)); 466 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); 467 return; 468 } 469 470 /* A 64-bit constant decomposed into 2 32-bit pieces. */ 471 if (check_fit_i32(lo, 13)) { 472 hi = (arg - lo) >> 32; 473 tcg_out_movi_u32(s, ret, hi); 474 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 475 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); 476 } else { 477 hi = arg >> 32; 478 tcg_out_movi_u32(s, ret, hi); 479 tcg_out_movi_u32(s, scratch, lo); 480 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 481 tcg_out_arith(s, ret, ret, scratch, ARITH_OR); 482 } 483} 484 485static void tcg_out_movi(TCGContext *s, TCGType type, 486 TCGReg ret, tcg_target_long arg) 487{ 488 tcg_debug_assert(ret != TCG_REG_T3); 489 tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); 490} 491 492static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 493{ 494 g_assert_not_reached(); 495} 496 497static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 498{ 499 g_assert_not_reached(); 500} 501 502static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 503{ 504 tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); 505} 506 507static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 508{ 509 tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); 510 tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); 511} 512 513static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 514{ 515 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); 516} 517 518static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) 519{ 520 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); 521} 522 523static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 524{ 525 tcg_out_ext32s(s, rd, rs); 526} 527 528static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 529{ 530 tcg_out_ext32u(s, rd, rs); 531} 532 533static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 534{ 535 tcg_out_ext32u(s, rd, rs); 536} 537 538static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 539{ 540 return false; 541} 542 543static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 544 tcg_target_long imm) 545{ 546 /* This function is only used for passing structs by reference. */ 547 g_assert_not_reached(); 548} 549 550static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, 551 TCGReg a2, int op) 552{ 553 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); 554} 555 556static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, 557 intptr_t offset, int op) 558{ 559 if (check_fit_ptr(offset, 13)) { 560 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | 561 INSN_IMM13(offset)); 562 } else { 563 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); 564 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); 565 } 566} 567 568static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 569 TCGReg arg1, intptr_t arg2) 570{ 571 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); 572} 573 574static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 575 TCGReg arg1, intptr_t arg2) 576{ 577 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); 578} 579 580static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 581 TCGReg base, intptr_t ofs) 582{ 583 if (val == 0) { 584 tcg_out_st(s, type, TCG_REG_G0, base, ofs); 585 return true; 586 } 587 return false; 588} 589 590static void tcg_out_sety(TCGContext *s, TCGReg rs) 591{ 592 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); 593} 594 595static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, 596 int32_t val2, int val2const, int uns) 597{ 598 /* Load Y with the sign/zero extension of RS1 to 64-bits. */ 599 if (uns) { 600 tcg_out_sety(s, TCG_REG_G0); 601 } else { 602 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); 603 tcg_out_sety(s, TCG_REG_T1); 604 } 605 606 tcg_out_arithc(s, rd, rs1, val2, val2const, 607 uns ? ARITH_UDIV : ARITH_SDIV); 608} 609 610static const uint8_t tcg_cond_to_bcond[] = { 611 [TCG_COND_EQ] = COND_E, 612 [TCG_COND_NE] = COND_NE, 613 [TCG_COND_LT] = COND_L, 614 [TCG_COND_GE] = COND_GE, 615 [TCG_COND_LE] = COND_LE, 616 [TCG_COND_GT] = COND_G, 617 [TCG_COND_LTU] = COND_CS, 618 [TCG_COND_GEU] = COND_CC, 619 [TCG_COND_LEU] = COND_LEU, 620 [TCG_COND_GTU] = COND_GU, 621}; 622 623static const uint8_t tcg_cond_to_rcond[] = { 624 [TCG_COND_EQ] = RCOND_Z, 625 [TCG_COND_NE] = RCOND_NZ, 626 [TCG_COND_LT] = RCOND_LZ, 627 [TCG_COND_GT] = RCOND_GZ, 628 [TCG_COND_LE] = RCOND_LEZ, 629 [TCG_COND_GE] = RCOND_GEZ 630}; 631 632static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) 633{ 634 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); 635} 636 637static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) 638{ 639 int off19 = 0; 640 641 if (l->has_value) { 642 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); 643 } else { 644 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); 645 } 646 tcg_out_bpcc0(s, scond, flags, off19); 647} 648 649static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) 650{ 651 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); 652} 653 654static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, 655 int32_t arg2, int const_arg2, TCGLabel *l) 656{ 657 tcg_out_cmp(s, arg1, arg2, const_arg2); 658 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); 659 tcg_out_nop(s); 660} 661 662static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, 663 int32_t v1, int v1const) 664{ 665 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) 666 | INSN_RS1(tcg_cond_to_bcond[cond]) 667 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); 668} 669 670static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 671 TCGReg c1, int32_t c2, int c2const, 672 int32_t v1, int v1const) 673{ 674 tcg_out_cmp(s, c1, c2, c2const); 675 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); 676} 677 678static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, 679 int32_t arg2, int const_arg2, TCGLabel *l) 680{ 681 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ 682 if (arg2 == 0 && !is_unsigned_cond(cond)) { 683 int off16 = 0; 684 685 if (l->has_value) { 686 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); 687 } else { 688 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); 689 } 690 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) 691 | INSN_COND(tcg_cond_to_rcond[cond]) | off16); 692 } else { 693 tcg_out_cmp(s, arg1, arg2, const_arg2); 694 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); 695 } 696 tcg_out_nop(s); 697} 698 699static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, 700 int32_t v1, int v1const) 701{ 702 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) 703 | (tcg_cond_to_rcond[cond] << 10) 704 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); 705} 706 707static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 708 TCGReg c1, int32_t c2, int c2const, 709 int32_t v1, int v1const) 710{ 711 /* For 64-bit signed comparisons vs zero, we can avoid the compare. 712 Note that the immediate range is one bit smaller, so we must check 713 for that as well. */ 714 if (c2 == 0 && !is_unsigned_cond(cond) 715 && (!v1const || check_fit_i32(v1, 10))) { 716 tcg_out_movr(s, cond, ret, c1, v1, v1const); 717 } else { 718 tcg_out_cmp(s, c1, c2, c2const); 719 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); 720 } 721} 722 723static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 724 TCGReg c1, int32_t c2, int c2const, bool neg) 725{ 726 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ 727 switch (cond) { 728 case TCG_COND_LTU: 729 case TCG_COND_GEU: 730 /* The result of the comparison is in the carry bit. */ 731 break; 732 733 case TCG_COND_EQ: 734 case TCG_COND_NE: 735 /* For equality, we can transform to inequality vs zero. */ 736 if (c2 != 0) { 737 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); 738 c2 = TCG_REG_T1; 739 } else { 740 c2 = c1; 741 } 742 c1 = TCG_REG_G0, c2const = 0; 743 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); 744 break; 745 746 case TCG_COND_GTU: 747 case TCG_COND_LEU: 748 /* If we don't need to load a constant into a register, we can 749 swap the operands on GTU/LEU. There's no benefit to loading 750 the constant into a temporary register. */ 751 if (!c2const || c2 == 0) { 752 TCGReg t = c1; 753 c1 = c2; 754 c2 = t; 755 c2const = 0; 756 cond = tcg_swap_cond(cond); 757 break; 758 } 759 /* FALLTHRU */ 760 761 default: 762 tcg_out_cmp(s, c1, c2, c2const); 763 tcg_out_movi_s13(s, ret, 0); 764 tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); 765 return; 766 } 767 768 tcg_out_cmp(s, c1, c2, c2const); 769 if (cond == TCG_COND_LTU) { 770 if (neg) { 771 /* 0 - 0 - C = -C = (C ? -1 : 0) */ 772 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); 773 } else { 774 /* 0 + 0 + C = C = (C ? 1 : 0) */ 775 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); 776 } 777 } else { 778 if (neg) { 779 /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */ 780 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); 781 } else { 782 /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */ 783 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); 784 } 785 } 786} 787 788static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 789 TCGReg c1, int32_t c2, int c2const, bool neg) 790{ 791 if (use_vis3_instructions && !neg) { 792 switch (cond) { 793 case TCG_COND_NE: 794 if (c2 != 0) { 795 break; 796 } 797 c2 = c1, c2const = 0, c1 = TCG_REG_G0; 798 /* FALLTHRU */ 799 case TCG_COND_LTU: 800 tcg_out_cmp(s, c1, c2, c2const); 801 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); 802 return; 803 default: 804 break; 805 } 806 } 807 808 /* For 64-bit signed comparisons vs zero, we can avoid the compare 809 if the input does not overlap the output. */ 810 if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { 811 tcg_out_movi_s13(s, ret, 0); 812 tcg_out_movr(s, cond, ret, c1, neg ? -1 : 1, 1); 813 } else { 814 tcg_out_cmp(s, c1, c2, c2const); 815 tcg_out_movi_s13(s, ret, 0); 816 tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); 817 } 818} 819 820static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, 821 TCGReg al, TCGReg ah, int32_t bl, int blconst, 822 int32_t bh, int bhconst, int opl, int oph) 823{ 824 TCGReg tmp = TCG_REG_T1; 825 826 /* Note that the low parts are fully consumed before tmp is set. */ 827 if (rl != ah && (bhconst || rl != bh)) { 828 tmp = rl; 829 } 830 831 tcg_out_arithc(s, tmp, al, bl, blconst, opl); 832 tcg_out_arithc(s, rh, ah, bh, bhconst, oph); 833 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); 834} 835 836static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, 837 TCGReg al, TCGReg ah, int32_t bl, int blconst, 838 int32_t bh, int bhconst, bool is_sub) 839{ 840 TCGReg tmp = TCG_REG_T1; 841 842 /* Note that the low parts are fully consumed before tmp is set. */ 843 if (rl != ah && (bhconst || rl != bh)) { 844 tmp = rl; 845 } 846 847 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); 848 849 if (use_vis3_instructions && !is_sub) { 850 /* Note that ADDXC doesn't accept immediates. */ 851 if (bhconst && bh != 0) { 852 tcg_out_movi_s13(s, TCG_REG_T2, bh); 853 bh = TCG_REG_T2; 854 } 855 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); 856 } else if (bh == TCG_REG_G0) { 857 /* If we have a zero, we can perform the operation in two insns, 858 with the arithmetic first, and a conditional move into place. */ 859 if (rh == ah) { 860 tcg_out_arithi(s, TCG_REG_T2, ah, 1, 861 is_sub ? ARITH_SUB : ARITH_ADD); 862 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); 863 } else { 864 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); 865 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); 866 } 867 } else { 868 /* 869 * Otherwise adjust BH as if there is carry into T2. 870 * Note that constant BH is constrained to 11 bits for the MOVCC, 871 * so the adjustment fits 12 bits. 872 */ 873 if (bhconst) { 874 tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); 875 } else { 876 tcg_out_arithi(s, TCG_REG_T2, bh, 1, 877 is_sub ? ARITH_SUB : ARITH_ADD); 878 } 879 /* ... smoosh T2 back to original BH if carry is clear ... */ 880 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); 881 /* ... and finally perform the arithmetic with the new operand. */ 882 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); 883 } 884 885 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); 886} 887 888static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, 889 bool in_prologue, bool tail_call) 890{ 891 uintptr_t desti = (uintptr_t)dest; 892 893 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, 894 desti & ~0xfff, in_prologue, TCG_REG_T2); 895 tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, 896 TCG_REG_T1, desti & 0xfff, JMPL); 897} 898 899static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, 900 bool in_prologue) 901{ 902 ptrdiff_t disp = tcg_pcrel_diff(s, dest); 903 904 if (disp == (int32_t)disp) { 905 tcg_out32(s, CALL | (uint32_t)disp >> 2); 906 } else { 907 tcg_out_jmpl_const(s, dest, in_prologue, false); 908 } 909} 910 911static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 912 const TCGHelperInfo *info) 913{ 914 tcg_out_call_nodelay(s, dest, false); 915 tcg_out_nop(s); 916} 917 918static void tcg_out_mb(TCGContext *s, TCGArg a0) 919{ 920 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ 921 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); 922} 923 924/* Generate global QEMU prologue and epilogue code */ 925static void tcg_target_qemu_prologue(TCGContext *s) 926{ 927 int tmp_buf_size, frame_size; 928 929 /* 930 * The TCG temp buffer is at the top of the frame, immediately 931 * below the frame pointer. Use the logical (aligned) offset here; 932 * the stack bias is applied in temp_allocate_frame(). 933 */ 934 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); 935 tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); 936 937 /* 938 * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is 939 * otherwise the minimal frame usable by callees. 940 */ 941 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; 942 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; 943 frame_size += TCG_TARGET_STACK_ALIGN - 1; 944 frame_size &= -TCG_TARGET_STACK_ALIGN; 945 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | 946 INSN_IMM13(-frame_size)); 947 948#ifndef CONFIG_SOFTMMU 949 if (guest_base != 0) { 950 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, 951 guest_base, true, TCG_REG_T1); 952 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 953 } 954#endif 955 956 /* We choose TCG_REG_TB such that no move is required. */ 957 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); 958 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); 959 960 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); 961 /* delay slot */ 962 tcg_out_nop(s); 963 964 /* Epilogue for goto_ptr. */ 965 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 966 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 967 /* delay slot */ 968 tcg_out_movi_s13(s, TCG_REG_O0, 0); 969} 970 971static void tcg_out_tb_start(TCGContext *s) 972{ 973 /* nothing to do */ 974} 975 976static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 977{ 978 int i; 979 for (i = 0; i < count; ++i) { 980 p[i] = NOP; 981 } 982} 983 984static const TCGLdstHelperParam ldst_helper_param = { 985 .ntmp = 1, .tmp = { TCG_REG_T1 } 986}; 987 988static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 989{ 990 MemOp opc = get_memop(lb->oi); 991 MemOp sgn; 992 993 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 994 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 995 return false; 996 } 997 998 /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ 999 sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; 1000 1001 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1002 tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); 1003 tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); 1004 1005 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1006 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1007 (intptr_t)lb->raddr, 0); 1008} 1009 1010static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1011{ 1012 MemOp opc = get_memop(lb->oi); 1013 1014 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1015 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1016 return false; 1017 } 1018 1019 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1020 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); 1021 1022 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1023 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1024 (intptr_t)lb->raddr, 0); 1025} 1026 1027typedef struct { 1028 TCGReg base; 1029 TCGReg index; 1030 TCGAtomAlign aa; 1031} HostAddress; 1032 1033bool tcg_target_has_memory_bswap(MemOp memop) 1034{ 1035 return true; 1036} 1037 1038/* We expect to use a 13-bit negative offset from ENV. */ 1039#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) 1040 1041/* 1042 * For system-mode, perform the TLB load and compare. 1043 * For user-mode, perform any required alignment tests. 1044 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1045 * is required and fill in @h with the host address for the fast path. 1046 */ 1047static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1048 TCGReg addr_reg, MemOpIdx oi, 1049 bool is_ld) 1050{ 1051 TCGType addr_type = s->addr_type; 1052 TCGLabelQemuLdst *ldst = NULL; 1053 MemOp opc = get_memop(oi); 1054 MemOp s_bits = opc & MO_SIZE; 1055 unsigned a_mask; 1056 1057 /* We don't support unaligned accesses. */ 1058 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1059 h->aa.align = MAX(h->aa.align, s_bits); 1060 a_mask = (1u << h->aa.align) - 1; 1061 1062#ifdef CONFIG_SOFTMMU 1063 int mem_index = get_mmuidx(oi); 1064 int fast_off = tlb_mask_table_ofs(s, mem_index); 1065 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1066 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1067 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1068 : offsetof(CPUTLBEntry, addr_write); 1069 int add_off = offsetof(CPUTLBEntry, addend); 1070 int compare_mask; 1071 int cc; 1072 1073 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1074 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); 1075 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); 1076 1077 /* Extract the page index, shifted into place for tlb index. */ 1078 tcg_out_arithi(s, TCG_REG_T1, addr_reg, 1079 s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); 1080 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); 1081 1082 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ 1083 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); 1084 1085 /* 1086 * Load the tlb comparator and the addend. 1087 * Always load the entire 64-bit comparator for simplicity. 1088 * We will ignore the high bits via BPCC_ICC below. 1089 */ 1090 tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); 1091 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); 1092 h->base = TCG_REG_T1; 1093 1094 /* Mask out the page offset, except for the required alignment. */ 1095 compare_mask = s->page_mask | a_mask; 1096 if (check_fit_tl(compare_mask, 13)) { 1097 tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); 1098 } else { 1099 tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); 1100 tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); 1101 } 1102 tcg_out_cmp(s, TCG_REG_T2, TCG_REG_T3, 0); 1103 1104 ldst = new_ldst_label(s); 1105 ldst->is_ld = is_ld; 1106 ldst->oi = oi; 1107 ldst->addrlo_reg = addr_reg; 1108 ldst->label_ptr[0] = s->code_ptr; 1109 1110 /* bne,pn %[xi]cc, label0 */ 1111 cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; 1112 tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); 1113#else 1114 /* 1115 * If the size equals the required alignment, we can skip the test 1116 * and allow host SIGBUS to deliver SIGBUS to the guest. 1117 * Otherwise, test for at least natural alignment and defer 1118 * everything else to the helper functions. 1119 */ 1120 if (s_bits != get_alignment_bits(opc)) { 1121 tcg_debug_assert(check_fit_tl(a_mask, 13)); 1122 tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); 1123 1124 ldst = new_ldst_label(s); 1125 ldst->is_ld = is_ld; 1126 ldst->oi = oi; 1127 ldst->addrlo_reg = addr_reg; 1128 ldst->label_ptr[0] = s->code_ptr; 1129 1130 /* bne,pn %icc, label0 */ 1131 tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); 1132 } 1133 h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; 1134#endif 1135 1136 /* If the guest address must be zero-extended, do in the delay slot. */ 1137 if (addr_type == TCG_TYPE_I32) { 1138 tcg_out_ext32u(s, TCG_REG_T2, addr_reg); 1139 h->index = TCG_REG_T2; 1140 } else { 1141 if (ldst) { 1142 tcg_out_nop(s); 1143 } 1144 h->index = addr_reg; 1145 } 1146 return ldst; 1147} 1148 1149static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, 1150 MemOpIdx oi, TCGType data_type) 1151{ 1152 static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { 1153 [MO_UB] = LDUB, 1154 [MO_SB] = LDSB, 1155 [MO_UB | MO_LE] = LDUB, 1156 [MO_SB | MO_LE] = LDSB, 1157 1158 [MO_BEUW] = LDUH, 1159 [MO_BESW] = LDSH, 1160 [MO_BEUL] = LDUW, 1161 [MO_BESL] = LDSW, 1162 [MO_BEUQ] = LDX, 1163 [MO_BESQ] = LDX, 1164 1165 [MO_LEUW] = LDUH_LE, 1166 [MO_LESW] = LDSH_LE, 1167 [MO_LEUL] = LDUW_LE, 1168 [MO_LESL] = LDSW_LE, 1169 [MO_LEUQ] = LDX_LE, 1170 [MO_LESQ] = LDX_LE, 1171 }; 1172 1173 TCGLabelQemuLdst *ldst; 1174 HostAddress h; 1175 1176 ldst = prepare_host_addr(s, &h, addr, oi, true); 1177 1178 tcg_out_ldst_rr(s, data, h.base, h.index, 1179 ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); 1180 1181 if (ldst) { 1182 ldst->type = data_type; 1183 ldst->datalo_reg = data; 1184 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1185 } 1186} 1187 1188static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, 1189 MemOpIdx oi, TCGType data_type) 1190{ 1191 static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { 1192 [MO_UB] = STB, 1193 1194 [MO_BEUW] = STH, 1195 [MO_BEUL] = STW, 1196 [MO_BEUQ] = STX, 1197 1198 [MO_LEUW] = STH_LE, 1199 [MO_LEUL] = STW_LE, 1200 [MO_LEUQ] = STX_LE, 1201 }; 1202 1203 TCGLabelQemuLdst *ldst; 1204 HostAddress h; 1205 1206 ldst = prepare_host_addr(s, &h, addr, oi, false); 1207 1208 tcg_out_ldst_rr(s, data, h.base, h.index, 1209 st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); 1210 1211 if (ldst) { 1212 ldst->type = data_type; 1213 ldst->datalo_reg = data; 1214 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1215 } 1216} 1217 1218static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1219{ 1220 if (check_fit_ptr(a0, 13)) { 1221 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1222 tcg_out_movi_s13(s, TCG_REG_O0, a0); 1223 return; 1224 } else { 1225 intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); 1226 if (check_fit_ptr(tb_diff, 13)) { 1227 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1228 /* Note that TCG_REG_TB has been unwound to O1. */ 1229 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); 1230 return; 1231 } 1232 } 1233 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); 1234 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1235 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); 1236} 1237 1238static void tcg_out_goto_tb(TCGContext *s, int which) 1239{ 1240 ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); 1241 1242 /* Load link and indirect branch. */ 1243 set_jmp_insn_offset(s, which); 1244 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); 1245 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); 1246 /* delay slot */ 1247 tcg_out_nop(s); 1248 set_jmp_reset_offset(s, which); 1249 1250 /* 1251 * For the unlinked path of goto_tb, we need to reset TCG_REG_TB 1252 * to the beginning of this TB. 1253 */ 1254 off = -tcg_current_code_size(s); 1255 if (check_fit_i32(off, 13)) { 1256 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); 1257 } else { 1258 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); 1259 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); 1260 } 1261} 1262 1263void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1264 uintptr_t jmp_rx, uintptr_t jmp_rw) 1265{ 1266} 1267 1268static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1269 const TCGArg args[TCG_MAX_OP_ARGS], 1270 const int const_args[TCG_MAX_OP_ARGS]) 1271{ 1272 TCGArg a0, a1, a2; 1273 int c, c2; 1274 1275 /* Hoist the loads of the most common arguments. */ 1276 a0 = args[0]; 1277 a1 = args[1]; 1278 a2 = args[2]; 1279 c2 = const_args[2]; 1280 1281 switch (opc) { 1282 case INDEX_op_goto_ptr: 1283 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); 1284 tcg_out_mov_delay(s, TCG_REG_TB, a0); 1285 break; 1286 case INDEX_op_br: 1287 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); 1288 tcg_out_nop(s); 1289 break; 1290 1291#define OP_32_64(x) \ 1292 glue(glue(case INDEX_op_, x), _i32): \ 1293 glue(glue(case INDEX_op_, x), _i64) 1294 1295 OP_32_64(ld8u): 1296 tcg_out_ldst(s, a0, a1, a2, LDUB); 1297 break; 1298 OP_32_64(ld8s): 1299 tcg_out_ldst(s, a0, a1, a2, LDSB); 1300 break; 1301 OP_32_64(ld16u): 1302 tcg_out_ldst(s, a0, a1, a2, LDUH); 1303 break; 1304 OP_32_64(ld16s): 1305 tcg_out_ldst(s, a0, a1, a2, LDSH); 1306 break; 1307 case INDEX_op_ld_i32: 1308 case INDEX_op_ld32u_i64: 1309 tcg_out_ldst(s, a0, a1, a2, LDUW); 1310 break; 1311 OP_32_64(st8): 1312 tcg_out_ldst(s, a0, a1, a2, STB); 1313 break; 1314 OP_32_64(st16): 1315 tcg_out_ldst(s, a0, a1, a2, STH); 1316 break; 1317 case INDEX_op_st_i32: 1318 case INDEX_op_st32_i64: 1319 tcg_out_ldst(s, a0, a1, a2, STW); 1320 break; 1321 OP_32_64(add): 1322 c = ARITH_ADD; 1323 goto gen_arith; 1324 OP_32_64(sub): 1325 c = ARITH_SUB; 1326 goto gen_arith; 1327 OP_32_64(and): 1328 c = ARITH_AND; 1329 goto gen_arith; 1330 OP_32_64(andc): 1331 c = ARITH_ANDN; 1332 goto gen_arith; 1333 OP_32_64(or): 1334 c = ARITH_OR; 1335 goto gen_arith; 1336 OP_32_64(orc): 1337 c = ARITH_ORN; 1338 goto gen_arith; 1339 OP_32_64(xor): 1340 c = ARITH_XOR; 1341 goto gen_arith; 1342 case INDEX_op_shl_i32: 1343 c = SHIFT_SLL; 1344 do_shift32: 1345 /* Limit immediate shift count lest we create an illegal insn. */ 1346 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); 1347 break; 1348 case INDEX_op_shr_i32: 1349 c = SHIFT_SRL; 1350 goto do_shift32; 1351 case INDEX_op_sar_i32: 1352 c = SHIFT_SRA; 1353 goto do_shift32; 1354 case INDEX_op_mul_i32: 1355 c = ARITH_UMUL; 1356 goto gen_arith; 1357 1358 OP_32_64(neg): 1359 c = ARITH_SUB; 1360 goto gen_arith1; 1361 OP_32_64(not): 1362 c = ARITH_ORN; 1363 goto gen_arith1; 1364 1365 case INDEX_op_div_i32: 1366 tcg_out_div32(s, a0, a1, a2, c2, 0); 1367 break; 1368 case INDEX_op_divu_i32: 1369 tcg_out_div32(s, a0, a1, a2, c2, 1); 1370 break; 1371 1372 case INDEX_op_brcond_i32: 1373 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1374 break; 1375 case INDEX_op_setcond_i32: 1376 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false); 1377 break; 1378 case INDEX_op_negsetcond_i32: 1379 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true); 1380 break; 1381 case INDEX_op_movcond_i32: 1382 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1383 break; 1384 1385 case INDEX_op_add2_i32: 1386 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1387 args[4], const_args[4], args[5], const_args[5], 1388 ARITH_ADDCC, ARITH_ADDC); 1389 break; 1390 case INDEX_op_sub2_i32: 1391 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1392 args[4], const_args[4], args[5], const_args[5], 1393 ARITH_SUBCC, ARITH_SUBC); 1394 break; 1395 case INDEX_op_mulu2_i32: 1396 c = ARITH_UMUL; 1397 goto do_mul2; 1398 case INDEX_op_muls2_i32: 1399 c = ARITH_SMUL; 1400 do_mul2: 1401 /* The 32-bit multiply insns produce a full 64-bit result. */ 1402 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); 1403 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); 1404 break; 1405 1406 case INDEX_op_qemu_ld_a32_i32: 1407 case INDEX_op_qemu_ld_a64_i32: 1408 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1409 break; 1410 case INDEX_op_qemu_ld_a32_i64: 1411 case INDEX_op_qemu_ld_a64_i64: 1412 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1413 break; 1414 case INDEX_op_qemu_st_a32_i32: 1415 case INDEX_op_qemu_st_a64_i32: 1416 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1417 break; 1418 case INDEX_op_qemu_st_a32_i64: 1419 case INDEX_op_qemu_st_a64_i64: 1420 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1421 break; 1422 1423 case INDEX_op_ld32s_i64: 1424 tcg_out_ldst(s, a0, a1, a2, LDSW); 1425 break; 1426 case INDEX_op_ld_i64: 1427 tcg_out_ldst(s, a0, a1, a2, LDX); 1428 break; 1429 case INDEX_op_st_i64: 1430 tcg_out_ldst(s, a0, a1, a2, STX); 1431 break; 1432 case INDEX_op_shl_i64: 1433 c = SHIFT_SLLX; 1434 do_shift64: 1435 /* Limit immediate shift count lest we create an illegal insn. */ 1436 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); 1437 break; 1438 case INDEX_op_shr_i64: 1439 c = SHIFT_SRLX; 1440 goto do_shift64; 1441 case INDEX_op_sar_i64: 1442 c = SHIFT_SRAX; 1443 goto do_shift64; 1444 case INDEX_op_mul_i64: 1445 c = ARITH_MULX; 1446 goto gen_arith; 1447 case INDEX_op_div_i64: 1448 c = ARITH_SDIVX; 1449 goto gen_arith; 1450 case INDEX_op_divu_i64: 1451 c = ARITH_UDIVX; 1452 goto gen_arith; 1453 1454 case INDEX_op_brcond_i64: 1455 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1456 break; 1457 case INDEX_op_setcond_i64: 1458 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false); 1459 break; 1460 case INDEX_op_negsetcond_i64: 1461 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true); 1462 break; 1463 case INDEX_op_movcond_i64: 1464 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1465 break; 1466 case INDEX_op_add2_i64: 1467 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1468 const_args[4], args[5], const_args[5], false); 1469 break; 1470 case INDEX_op_sub2_i64: 1471 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1472 const_args[4], args[5], const_args[5], true); 1473 break; 1474 case INDEX_op_muluh_i64: 1475 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); 1476 break; 1477 1478 gen_arith: 1479 tcg_out_arithc(s, a0, a1, a2, c2, c); 1480 break; 1481 1482 gen_arith1: 1483 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); 1484 break; 1485 1486 case INDEX_op_mb: 1487 tcg_out_mb(s, a0); 1488 break; 1489 1490 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1491 case INDEX_op_mov_i64: 1492 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1493 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1494 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1495 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1496 case INDEX_op_ext8s_i64: 1497 case INDEX_op_ext8u_i32: 1498 case INDEX_op_ext8u_i64: 1499 case INDEX_op_ext16s_i32: 1500 case INDEX_op_ext16s_i64: 1501 case INDEX_op_ext16u_i32: 1502 case INDEX_op_ext16u_i64: 1503 case INDEX_op_ext32s_i64: 1504 case INDEX_op_ext32u_i64: 1505 case INDEX_op_ext_i32_i64: 1506 case INDEX_op_extu_i32_i64: 1507 default: 1508 g_assert_not_reached(); 1509 } 1510} 1511 1512static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 1513{ 1514 switch (op) { 1515 case INDEX_op_goto_ptr: 1516 return C_O0_I1(r); 1517 1518 case INDEX_op_ld8u_i32: 1519 case INDEX_op_ld8u_i64: 1520 case INDEX_op_ld8s_i32: 1521 case INDEX_op_ld8s_i64: 1522 case INDEX_op_ld16u_i32: 1523 case INDEX_op_ld16u_i64: 1524 case INDEX_op_ld16s_i32: 1525 case INDEX_op_ld16s_i64: 1526 case INDEX_op_ld_i32: 1527 case INDEX_op_ld32u_i64: 1528 case INDEX_op_ld32s_i64: 1529 case INDEX_op_ld_i64: 1530 case INDEX_op_neg_i32: 1531 case INDEX_op_neg_i64: 1532 case INDEX_op_not_i32: 1533 case INDEX_op_not_i64: 1534 case INDEX_op_ext32s_i64: 1535 case INDEX_op_ext32u_i64: 1536 case INDEX_op_ext_i32_i64: 1537 case INDEX_op_extu_i32_i64: 1538 case INDEX_op_qemu_ld_a32_i32: 1539 case INDEX_op_qemu_ld_a64_i32: 1540 case INDEX_op_qemu_ld_a32_i64: 1541 case INDEX_op_qemu_ld_a64_i64: 1542 return C_O1_I1(r, r); 1543 1544 case INDEX_op_st8_i32: 1545 case INDEX_op_st8_i64: 1546 case INDEX_op_st16_i32: 1547 case INDEX_op_st16_i64: 1548 case INDEX_op_st_i32: 1549 case INDEX_op_st32_i64: 1550 case INDEX_op_st_i64: 1551 case INDEX_op_qemu_st_a32_i32: 1552 case INDEX_op_qemu_st_a64_i32: 1553 case INDEX_op_qemu_st_a32_i64: 1554 case INDEX_op_qemu_st_a64_i64: 1555 return C_O0_I2(rZ, r); 1556 1557 case INDEX_op_add_i32: 1558 case INDEX_op_add_i64: 1559 case INDEX_op_mul_i32: 1560 case INDEX_op_mul_i64: 1561 case INDEX_op_div_i32: 1562 case INDEX_op_div_i64: 1563 case INDEX_op_divu_i32: 1564 case INDEX_op_divu_i64: 1565 case INDEX_op_sub_i32: 1566 case INDEX_op_sub_i64: 1567 case INDEX_op_and_i32: 1568 case INDEX_op_and_i64: 1569 case INDEX_op_andc_i32: 1570 case INDEX_op_andc_i64: 1571 case INDEX_op_or_i32: 1572 case INDEX_op_or_i64: 1573 case INDEX_op_orc_i32: 1574 case INDEX_op_orc_i64: 1575 case INDEX_op_xor_i32: 1576 case INDEX_op_xor_i64: 1577 case INDEX_op_shl_i32: 1578 case INDEX_op_shl_i64: 1579 case INDEX_op_shr_i32: 1580 case INDEX_op_shr_i64: 1581 case INDEX_op_sar_i32: 1582 case INDEX_op_sar_i64: 1583 case INDEX_op_setcond_i32: 1584 case INDEX_op_setcond_i64: 1585 case INDEX_op_negsetcond_i32: 1586 case INDEX_op_negsetcond_i64: 1587 return C_O1_I2(r, rZ, rJ); 1588 1589 case INDEX_op_brcond_i32: 1590 case INDEX_op_brcond_i64: 1591 return C_O0_I2(rZ, rJ); 1592 case INDEX_op_movcond_i32: 1593 case INDEX_op_movcond_i64: 1594 return C_O1_I4(r, rZ, rJ, rI, 0); 1595 case INDEX_op_add2_i32: 1596 case INDEX_op_add2_i64: 1597 case INDEX_op_sub2_i32: 1598 case INDEX_op_sub2_i64: 1599 return C_O2_I4(r, r, rZ, rZ, rJ, rJ); 1600 case INDEX_op_mulu2_i32: 1601 case INDEX_op_muls2_i32: 1602 return C_O2_I2(r, r, rZ, rJ); 1603 case INDEX_op_muluh_i64: 1604 return C_O1_I2(r, r, r); 1605 1606 default: 1607 g_assert_not_reached(); 1608 } 1609} 1610 1611static void tcg_target_init(TCGContext *s) 1612{ 1613 /* 1614 * Only probe for the platform and capabilities if we haven't already 1615 * determined maximum values at compile time. 1616 */ 1617#ifndef use_vis3_instructions 1618 { 1619 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 1620 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; 1621 } 1622#endif 1623 1624 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 1625 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 1626 1627 tcg_target_call_clobber_regs = 0; 1628 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); 1629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); 1630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); 1631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); 1632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); 1633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); 1634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); 1635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); 1636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); 1637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); 1638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); 1639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); 1640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); 1641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); 1642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); 1643 1644 s->reserved_regs = 0; 1645 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ 1646 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ 1647 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ 1648 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ 1649 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ 1650 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ 1651 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ 1652 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ 1653 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ 1654} 1655 1656#define ELF_HOST_MACHINE EM_SPARCV9 1657 1658typedef struct { 1659 DebugFrameHeader h; 1660 uint8_t fde_def_cfa[4]; 1661 uint8_t fde_win_save; 1662 uint8_t fde_ret_save[3]; 1663} DebugFrame; 1664 1665static const DebugFrame debug_frame = { 1666 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 1667 .h.cie.id = -1, 1668 .h.cie.version = 1, 1669 .h.cie.code_align = 1, 1670 .h.cie.data_align = -sizeof(void *) & 0x7f, 1671 .h.cie.return_column = 15, /* o7 */ 1672 1673 /* Total FDE size does not include the "len" member. */ 1674 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1675 1676 .fde_def_cfa = { 1677 12, 30, /* DW_CFA_def_cfa i6, 2047 */ 1678 (2047 & 0x7f) | 0x80, (2047 >> 7) 1679 }, 1680 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ 1681 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ 1682}; 1683 1684void tcg_register_jit(const void *buf, size_t buf_size) 1685{ 1686 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1687} 1688