1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29#include "elf.h" 30 31#define TCG_CT_CONST_S16 (1 << 8) 32#define TCG_CT_CONST_S32 (1 << 9) 33#define TCG_CT_CONST_U32 (1 << 10) 34#define TCG_CT_CONST_ZERO (1 << 11) 35#define TCG_CT_CONST_P32 (1 << 12) 36#define TCG_CT_CONST_INV (1 << 13) 37#define TCG_CT_CONST_INVRISBG (1 << 14) 38#define TCG_CT_CONST_CMP (1 << 15) 39 40#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 41#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 42 43/* Several places within the instruction set 0 means "no register" 44 rather than TCG_REG_R0. */ 45#define TCG_REG_NONE 0 46 47/* A scratch register that may be be used throughout the backend. */ 48#define TCG_TMP0 TCG_REG_R1 49#define TCG_VEC_TMP0 TCG_REG_V31 50 51#define TCG_GUEST_BASE_REG TCG_REG_R13 52 53/* All of the following instructions are prefixed with their instruction 54 format, and are defined as 8- or 16-bit quantities, even when the two 55 halves of the 16-bit quantity may appear 32 bits apart in the insn. 56 This makes it easy to copy the values from the tables in Appendix B. */ 57typedef enum S390Opcode { 58 RIL_AFI = 0xc209, 59 RIL_AGFI = 0xc208, 60 RIL_ALFI = 0xc20b, 61 RIL_ALGFI = 0xc20a, 62 RIL_BRASL = 0xc005, 63 RIL_BRCL = 0xc004, 64 RIL_CFI = 0xc20d, 65 RIL_CGFI = 0xc20c, 66 RIL_CLFI = 0xc20f, 67 RIL_CLGFI = 0xc20e, 68 RIL_CLRL = 0xc60f, 69 RIL_CLGRL = 0xc60a, 70 RIL_CRL = 0xc60d, 71 RIL_CGRL = 0xc608, 72 RIL_IIHF = 0xc008, 73 RIL_IILF = 0xc009, 74 RIL_LARL = 0xc000, 75 RIL_LGFI = 0xc001, 76 RIL_LGRL = 0xc408, 77 RIL_LLIHF = 0xc00e, 78 RIL_LLILF = 0xc00f, 79 RIL_LRL = 0xc40d, 80 RIL_MSFI = 0xc201, 81 RIL_MSGFI = 0xc200, 82 RIL_NIHF = 0xc00a, 83 RIL_NILF = 0xc00b, 84 RIL_OIHF = 0xc00c, 85 RIL_OILF = 0xc00d, 86 RIL_SLFI = 0xc205, 87 RIL_SLGFI = 0xc204, 88 RIL_XIHF = 0xc006, 89 RIL_XILF = 0xc007, 90 91 RI_AGHI = 0xa70b, 92 RI_AHI = 0xa70a, 93 RI_BRC = 0xa704, 94 RI_CHI = 0xa70e, 95 RI_CGHI = 0xa70f, 96 RI_IIHH = 0xa500, 97 RI_IIHL = 0xa501, 98 RI_IILH = 0xa502, 99 RI_IILL = 0xa503, 100 RI_LGHI = 0xa709, 101 RI_LLIHH = 0xa50c, 102 RI_LLIHL = 0xa50d, 103 RI_LLILH = 0xa50e, 104 RI_LLILL = 0xa50f, 105 RI_MGHI = 0xa70d, 106 RI_MHI = 0xa70c, 107 RI_NIHH = 0xa504, 108 RI_NIHL = 0xa505, 109 RI_NILH = 0xa506, 110 RI_NILL = 0xa507, 111 RI_OIHH = 0xa508, 112 RI_OIHL = 0xa509, 113 RI_OILH = 0xa50a, 114 RI_OILL = 0xa50b, 115 RI_TMLL = 0xa701, 116 RI_TMLH = 0xa700, 117 RI_TMHL = 0xa703, 118 RI_TMHH = 0xa702, 119 120 RIEb_CGRJ = 0xec64, 121 RIEb_CLGRJ = 0xec65, 122 RIEb_CLRJ = 0xec77, 123 RIEb_CRJ = 0xec76, 124 125 RIEc_CGIJ = 0xec7c, 126 RIEc_CIJ = 0xec7e, 127 RIEc_CLGIJ = 0xec7d, 128 RIEc_CLIJ = 0xec7f, 129 130 RIEf_RISBG = 0xec55, 131 132 RIEg_LOCGHI = 0xec46, 133 134 RRE_AGR = 0xb908, 135 RRE_ALGR = 0xb90a, 136 RRE_ALCR = 0xb998, 137 RRE_ALCGR = 0xb988, 138 RRE_ALGFR = 0xb91a, 139 RRE_CGR = 0xb920, 140 RRE_CLGR = 0xb921, 141 RRE_DLGR = 0xb987, 142 RRE_DLR = 0xb997, 143 RRE_DSGFR = 0xb91d, 144 RRE_DSGR = 0xb90d, 145 RRE_FLOGR = 0xb983, 146 RRE_LGBR = 0xb906, 147 RRE_LCGR = 0xb903, 148 RRE_LGFR = 0xb914, 149 RRE_LGHR = 0xb907, 150 RRE_LGR = 0xb904, 151 RRE_LLGCR = 0xb984, 152 RRE_LLGFR = 0xb916, 153 RRE_LLGHR = 0xb985, 154 RRE_LRVR = 0xb91f, 155 RRE_LRVGR = 0xb90f, 156 RRE_LTGR = 0xb902, 157 RRE_MLGR = 0xb986, 158 RRE_MSGR = 0xb90c, 159 RRE_MSR = 0xb252, 160 RRE_NGR = 0xb980, 161 RRE_OGR = 0xb981, 162 RRE_SGR = 0xb909, 163 RRE_SLGR = 0xb90b, 164 RRE_SLBR = 0xb999, 165 RRE_SLBGR = 0xb989, 166 RRE_XGR = 0xb982, 167 168 RRFa_MGRK = 0xb9ec, 169 RRFa_MSRKC = 0xb9fd, 170 RRFa_MSGRKC = 0xb9ed, 171 RRFa_NCRK = 0xb9f5, 172 RRFa_NCGRK = 0xb9e5, 173 RRFa_NNRK = 0xb974, 174 RRFa_NNGRK = 0xb964, 175 RRFa_NORK = 0xb976, 176 RRFa_NOGRK = 0xb966, 177 RRFa_NRK = 0xb9f4, 178 RRFa_NGRK = 0xb9e4, 179 RRFa_NXRK = 0xb977, 180 RRFa_NXGRK = 0xb967, 181 RRFa_OCRK = 0xb975, 182 RRFa_OCGRK = 0xb965, 183 RRFa_ORK = 0xb9f6, 184 RRFa_OGRK = 0xb9e6, 185 RRFa_SRK = 0xb9f9, 186 RRFa_SGRK = 0xb9e9, 187 RRFa_SLRK = 0xb9fb, 188 RRFa_SLGRK = 0xb9eb, 189 RRFa_XRK = 0xb9f7, 190 RRFa_XGRK = 0xb9e7, 191 192 RRFam_SELGR = 0xb9e3, 193 194 RRFc_LOCR = 0xb9f2, 195 RRFc_LOCGR = 0xb9e2, 196 RRFc_POPCNT = 0xb9e1, 197 198 RR_AR = 0x1a, 199 RR_ALR = 0x1e, 200 RR_BASR = 0x0d, 201 RR_BCR = 0x07, 202 RR_CLR = 0x15, 203 RR_CR = 0x19, 204 RR_DR = 0x1d, 205 RR_LCR = 0x13, 206 RR_LR = 0x18, 207 RR_LTR = 0x12, 208 RR_NR = 0x14, 209 RR_OR = 0x16, 210 RR_SR = 0x1b, 211 RR_SLR = 0x1f, 212 RR_XR = 0x17, 213 214 RSY_RLL = 0xeb1d, 215 RSY_RLLG = 0xeb1c, 216 RSY_SLLG = 0xeb0d, 217 RSY_SLLK = 0xebdf, 218 RSY_SRAG = 0xeb0a, 219 RSY_SRAK = 0xebdc, 220 RSY_SRLG = 0xeb0c, 221 RSY_SRLK = 0xebde, 222 223 RS_SLL = 0x89, 224 RS_SRA = 0x8a, 225 RS_SRL = 0x88, 226 227 RXY_AG = 0xe308, 228 RXY_AY = 0xe35a, 229 RXY_CG = 0xe320, 230 RXY_CLG = 0xe321, 231 RXY_CLY = 0xe355, 232 RXY_CY = 0xe359, 233 RXY_LAY = 0xe371, 234 RXY_LB = 0xe376, 235 RXY_LG = 0xe304, 236 RXY_LGB = 0xe377, 237 RXY_LGF = 0xe314, 238 RXY_LGH = 0xe315, 239 RXY_LHY = 0xe378, 240 RXY_LLGC = 0xe390, 241 RXY_LLGF = 0xe316, 242 RXY_LLGH = 0xe391, 243 RXY_LMG = 0xeb04, 244 RXY_LPQ = 0xe38f, 245 RXY_LRV = 0xe31e, 246 RXY_LRVG = 0xe30f, 247 RXY_LRVH = 0xe31f, 248 RXY_LY = 0xe358, 249 RXY_NG = 0xe380, 250 RXY_OG = 0xe381, 251 RXY_STCY = 0xe372, 252 RXY_STG = 0xe324, 253 RXY_STHY = 0xe370, 254 RXY_STMG = 0xeb24, 255 RXY_STPQ = 0xe38e, 256 RXY_STRV = 0xe33e, 257 RXY_STRVG = 0xe32f, 258 RXY_STRVH = 0xe33f, 259 RXY_STY = 0xe350, 260 RXY_XG = 0xe382, 261 262 RX_A = 0x5a, 263 RX_C = 0x59, 264 RX_L = 0x58, 265 RX_LA = 0x41, 266 RX_LH = 0x48, 267 RX_ST = 0x50, 268 RX_STC = 0x42, 269 RX_STH = 0x40, 270 271 VRIa_VGBM = 0xe744, 272 VRIa_VREPI = 0xe745, 273 VRIb_VGM = 0xe746, 274 VRIc_VREP = 0xe74d, 275 276 VRRa_VLC = 0xe7de, 277 VRRa_VLP = 0xe7df, 278 VRRa_VLR = 0xe756, 279 VRRc_VA = 0xe7f3, 280 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 281 VRRc_VCH = 0xe7fb, /* " */ 282 VRRc_VCHL = 0xe7f9, /* " */ 283 VRRc_VERLLV = 0xe773, 284 VRRc_VESLV = 0xe770, 285 VRRc_VESRAV = 0xe77a, 286 VRRc_VESRLV = 0xe778, 287 VRRc_VML = 0xe7a2, 288 VRRc_VMN = 0xe7fe, 289 VRRc_VMNL = 0xe7fc, 290 VRRc_VMX = 0xe7ff, 291 VRRc_VMXL = 0xe7fd, 292 VRRc_VN = 0xe768, 293 VRRc_VNC = 0xe769, 294 VRRc_VNN = 0xe76e, 295 VRRc_VNO = 0xe76b, 296 VRRc_VNX = 0xe76c, 297 VRRc_VO = 0xe76a, 298 VRRc_VOC = 0xe76f, 299 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 300 VRRc_VS = 0xe7f7, 301 VRRa_VUPH = 0xe7d7, 302 VRRa_VUPL = 0xe7d6, 303 VRRc_VX = 0xe76d, 304 VRRe_VSEL = 0xe78d, 305 VRRf_VLVGP = 0xe762, 306 307 VRSa_VERLL = 0xe733, 308 VRSa_VESL = 0xe730, 309 VRSa_VESRA = 0xe73a, 310 VRSa_VESRL = 0xe738, 311 VRSb_VLVG = 0xe722, 312 VRSc_VLGV = 0xe721, 313 314 VRX_VL = 0xe706, 315 VRX_VLLEZ = 0xe704, 316 VRX_VLREP = 0xe705, 317 VRX_VST = 0xe70e, 318 VRX_VSTEF = 0xe70b, 319 VRX_VSTEG = 0xe70a, 320 321 NOP = 0x0707, 322} S390Opcode; 323 324#ifdef CONFIG_DEBUG_TCG 325static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 326 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 327 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 329 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 330 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 331 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 332 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 333}; 334#endif 335 336/* Since R6 is a potential argument register, choose it last of the 337 call-saved registers. Likewise prefer the call-clobbered registers 338 in reverse order to maximize the chance of avoiding the arguments. */ 339static const int tcg_target_reg_alloc_order[] = { 340 /* Call saved registers. */ 341 TCG_REG_R13, 342 TCG_REG_R12, 343 TCG_REG_R11, 344 TCG_REG_R10, 345 TCG_REG_R9, 346 TCG_REG_R8, 347 TCG_REG_R7, 348 TCG_REG_R6, 349 /* Call clobbered registers. */ 350 TCG_REG_R14, 351 TCG_REG_R0, 352 TCG_REG_R1, 353 /* Argument registers, in reverse order of allocation. */ 354 TCG_REG_R5, 355 TCG_REG_R4, 356 TCG_REG_R3, 357 TCG_REG_R2, 358 359 /* V8-V15 are call saved, and omitted. */ 360 TCG_REG_V0, 361 TCG_REG_V1, 362 TCG_REG_V2, 363 TCG_REG_V3, 364 TCG_REG_V4, 365 TCG_REG_V5, 366 TCG_REG_V6, 367 TCG_REG_V7, 368 TCG_REG_V16, 369 TCG_REG_V17, 370 TCG_REG_V18, 371 TCG_REG_V19, 372 TCG_REG_V20, 373 TCG_REG_V21, 374 TCG_REG_V22, 375 TCG_REG_V23, 376 TCG_REG_V24, 377 TCG_REG_V25, 378 TCG_REG_V26, 379 TCG_REG_V27, 380 TCG_REG_V28, 381 TCG_REG_V29, 382 TCG_REG_V30, 383 TCG_REG_V31, 384}; 385 386static const int tcg_target_call_iarg_regs[] = { 387 TCG_REG_R2, 388 TCG_REG_R3, 389 TCG_REG_R4, 390 TCG_REG_R5, 391 TCG_REG_R6, 392}; 393 394static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 395{ 396 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 397 tcg_debug_assert(slot == 0); 398 return TCG_REG_R2; 399} 400 401#define S390_CC_EQ 8 402#define S390_CC_LT 4 403#define S390_CC_GT 2 404#define S390_CC_OV 1 405#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 406#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 407#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 408#define S390_CC_NEVER 0 409#define S390_CC_ALWAYS 15 410 411#define S390_TM_EQ 8 /* CC == 0 */ 412#define S390_TM_NE 7 /* CC in {1,2,3} */ 413 414/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 415static const uint8_t tcg_cond_to_s390_cond[16] = { 416 [TCG_COND_EQ] = S390_CC_EQ, 417 [TCG_COND_NE] = S390_CC_NE, 418 [TCG_COND_TSTEQ] = S390_CC_EQ, 419 [TCG_COND_TSTNE] = S390_CC_NE, 420 [TCG_COND_LT] = S390_CC_LT, 421 [TCG_COND_LE] = S390_CC_LE, 422 [TCG_COND_GT] = S390_CC_GT, 423 [TCG_COND_GE] = S390_CC_GE, 424 [TCG_COND_LTU] = S390_CC_LT, 425 [TCG_COND_LEU] = S390_CC_LE, 426 [TCG_COND_GTU] = S390_CC_GT, 427 [TCG_COND_GEU] = S390_CC_GE, 428}; 429 430/* Condition codes that result from a LOAD AND TEST. Here, we have no 431 unsigned instruction variation, however since the test is vs zero we 432 can re-map the outcomes appropriately. */ 433static const uint8_t tcg_cond_to_ltr_cond[16] = { 434 [TCG_COND_EQ] = S390_CC_EQ, 435 [TCG_COND_NE] = S390_CC_NE, 436 [TCG_COND_TSTEQ] = S390_CC_ALWAYS, 437 [TCG_COND_TSTNE] = S390_CC_NEVER, 438 [TCG_COND_LT] = S390_CC_LT, 439 [TCG_COND_LE] = S390_CC_LE, 440 [TCG_COND_GT] = S390_CC_GT, 441 [TCG_COND_GE] = S390_CC_GE, 442 [TCG_COND_LTU] = S390_CC_NEVER, 443 [TCG_COND_LEU] = S390_CC_EQ, 444 [TCG_COND_GTU] = S390_CC_NE, 445 [TCG_COND_GEU] = S390_CC_ALWAYS, 446}; 447 448static const tcg_insn_unit *tb_ret_addr; 449uint64_t s390_facilities[3]; 450 451static inline bool is_general_reg(TCGReg r) 452{ 453 return r <= TCG_REG_R15; 454} 455 456static inline bool is_vector_reg(TCGReg r) 457{ 458 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 459} 460 461static bool patch_reloc(tcg_insn_unit *src_rw, int type, 462 intptr_t value, intptr_t addend) 463{ 464 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 465 intptr_t pcrel2; 466 uint32_t old; 467 468 value += addend; 469 pcrel2 = (tcg_insn_unit *)value - src_rx; 470 471 switch (type) { 472 case R_390_PC16DBL: 473 if (pcrel2 == (int16_t)pcrel2) { 474 tcg_patch16(src_rw, pcrel2); 475 return true; 476 } 477 break; 478 case R_390_PC32DBL: 479 if (pcrel2 == (int32_t)pcrel2) { 480 tcg_patch32(src_rw, pcrel2); 481 return true; 482 } 483 break; 484 case R_390_20: 485 if (value == sextract64(value, 0, 20)) { 486 old = *(uint32_t *)src_rw & 0xf00000ff; 487 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 488 tcg_patch32(src_rw, old); 489 return true; 490 } 491 break; 492 default: 493 g_assert_not_reached(); 494 } 495 return false; 496} 497 498static int is_const_p16(uint64_t val) 499{ 500 for (int i = 0; i < 4; ++i) { 501 uint64_t mask = 0xffffull << (i * 16); 502 if ((val & ~mask) == 0) { 503 return i; 504 } 505 } 506 return -1; 507} 508 509static int is_const_p32(uint64_t val) 510{ 511 if ((val & 0xffffffff00000000ull) == 0) { 512 return 0; 513 } 514 if ((val & 0x00000000ffffffffull) == 0) { 515 return 1; 516 } 517 return -1; 518} 519 520/* 521 * Accept bit patterns like these: 522 * 0....01....1 523 * 1....10....0 524 * 1..10..01..1 525 * 0..01..10..0 526 * Copied from gcc sources. 527 */ 528static bool risbg_mask(uint64_t c) 529{ 530 uint64_t lsb; 531 /* We don't change the number of transitions by inverting, 532 so make sure we start with the LSB zero. */ 533 if (c & 1) { 534 c = ~c; 535 } 536 /* Reject all zeros or all ones. */ 537 if (c == 0) { 538 return false; 539 } 540 /* Find the first transition. */ 541 lsb = c & -c; 542 /* Invert to look for a second transition. */ 543 c = ~c; 544 /* Erase the first transition. */ 545 c &= -lsb; 546 /* Find the second transition, if any. */ 547 lsb = c & -c; 548 /* Match if all the bits are 1's, or if c is zero. */ 549 return c == -lsb; 550} 551 552/* Test if a constant matches the constraint. */ 553static bool tcg_target_const_match(int64_t val, int ct, 554 TCGType type, TCGCond cond, int vece) 555{ 556 uint64_t uval = val; 557 558 if (ct & TCG_CT_CONST) { 559 return true; 560 } 561 if (type == TCG_TYPE_I32) { 562 uval = (uint32_t)val; 563 val = (int32_t)val; 564 } 565 566 if (ct & TCG_CT_CONST_CMP) { 567 switch (cond) { 568 case TCG_COND_EQ: 569 case TCG_COND_NE: 570 ct |= TCG_CT_CONST_S32 | TCG_CT_CONST_U32; /* CGFI or CLGFI */ 571 break; 572 case TCG_COND_LT: 573 case TCG_COND_GE: 574 case TCG_COND_LE: 575 case TCG_COND_GT: 576 ct |= TCG_CT_CONST_S32; /* CGFI */ 577 break; 578 case TCG_COND_LTU: 579 case TCG_COND_GEU: 580 case TCG_COND_LEU: 581 case TCG_COND_GTU: 582 ct |= TCG_CT_CONST_U32; /* CLGFI */ 583 break; 584 case TCG_COND_TSTNE: 585 case TCG_COND_TSTEQ: 586 if (is_const_p16(uval) >= 0) { 587 return true; /* TMxx */ 588 } 589 if (risbg_mask(uval)) { 590 return true; /* RISBG */ 591 } 592 break; 593 default: 594 g_assert_not_reached(); 595 } 596 } 597 598 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 599 return true; 600 } 601 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 602 return true; 603 } 604 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 605 return true; 606 } 607 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 608 return true; 609 } 610 611 if (ct & TCG_CT_CONST_INV) { 612 val = ~val; 613 } 614 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 615 return true; 616 } 617 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 618 return true; 619 } 620 return false; 621} 622 623/* Emit instructions according to the given instruction format. */ 624 625static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 626{ 627 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 628} 629 630static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 631 TCGReg r1, TCGReg r2) 632{ 633 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 634} 635 636/* RRF-a without the m4 field */ 637static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 638 TCGReg r1, TCGReg r2, TCGReg r3) 639{ 640 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 641} 642 643/* RRF-a with the m4 field */ 644static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 645 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 646{ 647 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 648} 649 650static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 651 TCGReg r1, TCGReg r2, int m3) 652{ 653 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 654} 655 656static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 657{ 658 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 659} 660 661static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 662 int i2, int m3) 663{ 664 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 665 tcg_out32(s, (i2 << 16) | (op & 0xff)); 666} 667 668static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 669{ 670 tcg_out16(s, op | (r1 << 4)); 671 tcg_out32(s, i2); 672} 673 674static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 675 TCGReg b2, TCGReg r3, int disp) 676{ 677 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 678 | (disp & 0xfff)); 679} 680 681static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 682 TCGReg b2, TCGReg r3, int disp) 683{ 684 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 685 tcg_out32(s, (op & 0xff) | (b2 << 28) 686 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 687} 688 689#define tcg_out_insn_RX tcg_out_insn_RS 690#define tcg_out_insn_RXY tcg_out_insn_RSY 691 692static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 693{ 694 /* 695 * Shift bit 4 of each regno to its corresponding bit of RXB. 696 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 697 * is the left-shift of the 4th operand. 698 */ 699 return ((v1 & 0x10) << (4 + 3)) 700 | ((v2 & 0x10) << (4 + 2)) 701 | ((v3 & 0x10) << (4 + 1)) 702 | ((v4 & 0x10) << (4 + 0)); 703} 704 705static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 706 TCGReg v1, uint16_t i2, int m3) 707{ 708 tcg_debug_assert(is_vector_reg(v1)); 709 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 710 tcg_out16(s, i2); 711 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 712} 713 714static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 715 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 716{ 717 tcg_debug_assert(is_vector_reg(v1)); 718 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 719 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 720 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 721} 722 723static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 724 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 725{ 726 tcg_debug_assert(is_vector_reg(v1)); 727 tcg_debug_assert(is_vector_reg(v3)); 728 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 729 tcg_out16(s, i2); 730 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 731} 732 733static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 734 TCGReg v1, TCGReg v2, int m3) 735{ 736 tcg_debug_assert(is_vector_reg(v1)); 737 tcg_debug_assert(is_vector_reg(v2)); 738 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 739 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 740} 741 742static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 743 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 744{ 745 tcg_debug_assert(is_vector_reg(v1)); 746 tcg_debug_assert(is_vector_reg(v2)); 747 tcg_debug_assert(is_vector_reg(v3)); 748 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 749 tcg_out16(s, v3 << 12); 750 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 751} 752 753static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 754 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 755{ 756 tcg_debug_assert(is_vector_reg(v1)); 757 tcg_debug_assert(is_vector_reg(v2)); 758 tcg_debug_assert(is_vector_reg(v3)); 759 tcg_debug_assert(is_vector_reg(v4)); 760 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 761 tcg_out16(s, v3 << 12); 762 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 763} 764 765static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 766 TCGReg v1, TCGReg r2, TCGReg r3) 767{ 768 tcg_debug_assert(is_vector_reg(v1)); 769 tcg_debug_assert(is_general_reg(r2)); 770 tcg_debug_assert(is_general_reg(r3)); 771 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 772 tcg_out16(s, r3 << 12); 773 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 774} 775 776static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 777 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 778{ 779 tcg_debug_assert(is_vector_reg(v1)); 780 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 781 tcg_debug_assert(is_general_reg(b2)); 782 tcg_debug_assert(is_vector_reg(v3)); 783 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 784 tcg_out16(s, b2 << 12 | d2); 785 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 786} 787 788static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 789 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 790{ 791 tcg_debug_assert(is_vector_reg(v1)); 792 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 793 tcg_debug_assert(is_general_reg(b2)); 794 tcg_debug_assert(is_general_reg(r3)); 795 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 796 tcg_out16(s, b2 << 12 | d2); 797 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 798} 799 800static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 801 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 802{ 803 tcg_debug_assert(is_general_reg(r1)); 804 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 805 tcg_debug_assert(is_general_reg(b2)); 806 tcg_debug_assert(is_vector_reg(v3)); 807 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 808 tcg_out16(s, b2 << 12 | d2); 809 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 810} 811 812static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 813 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 814{ 815 tcg_debug_assert(is_vector_reg(v1)); 816 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 817 tcg_debug_assert(is_general_reg(x2)); 818 tcg_debug_assert(is_general_reg(b2)); 819 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 820 tcg_out16(s, (b2 << 12) | d2); 821 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 822} 823 824/* Emit an opcode with "type-checking" of the format. */ 825#define tcg_out_insn(S, FMT, OP, ...) \ 826 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 827 828 829/* emit 64-bit shifts */ 830static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 831 TCGReg src, TCGReg sh_reg, int sh_imm) 832{ 833 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 834} 835 836/* emit 32-bit shifts */ 837static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 838 TCGReg sh_reg, int sh_imm) 839{ 840 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 841} 842 843static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 844{ 845 if (src == dst) { 846 return true; 847 } 848 switch (type) { 849 case TCG_TYPE_I32: 850 if (likely(is_general_reg(dst) && is_general_reg(src))) { 851 tcg_out_insn(s, RR, LR, dst, src); 852 break; 853 } 854 /* fallthru */ 855 856 case TCG_TYPE_I64: 857 if (likely(is_general_reg(dst))) { 858 if (likely(is_general_reg(src))) { 859 tcg_out_insn(s, RRE, LGR, dst, src); 860 } else { 861 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 862 } 863 break; 864 } else if (is_general_reg(src)) { 865 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 866 break; 867 } 868 /* fallthru */ 869 870 case TCG_TYPE_V64: 871 case TCG_TYPE_V128: 872 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 873 break; 874 875 default: 876 g_assert_not_reached(); 877 } 878 return true; 879} 880 881static const S390Opcode li_insns[4] = { 882 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 883}; 884static const S390Opcode oi_insns[4] = { 885 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 886}; 887static const S390Opcode lif_insns[2] = { 888 RIL_LLILF, RIL_LLIHF, 889}; 890static const S390Opcode tm_insns[4] = { 891 RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH 892}; 893 894/* load a register with an immediate value */ 895static void tcg_out_movi(TCGContext *s, TCGType type, 896 TCGReg ret, tcg_target_long sval) 897{ 898 tcg_target_ulong uval = sval; 899 ptrdiff_t pc_off; 900 int i; 901 902 if (type == TCG_TYPE_I32) { 903 uval = (uint32_t)sval; 904 sval = (int32_t)sval; 905 } 906 907 /* Try all 32-bit insns that can load it in one go. */ 908 if (sval >= -0x8000 && sval < 0x8000) { 909 tcg_out_insn(s, RI, LGHI, ret, sval); 910 return; 911 } 912 913 i = is_const_p16(uval); 914 if (i >= 0) { 915 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 916 return; 917 } 918 919 /* Try all 48-bit insns that can load it in one go. */ 920 if (sval == (int32_t)sval) { 921 tcg_out_insn(s, RIL, LGFI, ret, sval); 922 return; 923 } 924 925 i = is_const_p32(uval); 926 if (i >= 0) { 927 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 928 return; 929 } 930 931 /* Try for PC-relative address load. For odd addresses, add one. */ 932 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 933 if (pc_off == (int32_t)pc_off) { 934 tcg_out_insn(s, RIL, LARL, ret, pc_off); 935 if (sval & 1) { 936 tcg_out_insn(s, RI, AGHI, ret, 1); 937 } 938 return; 939 } 940 941 /* Otherwise, load it by parts. */ 942 i = is_const_p16((uint32_t)uval); 943 if (i >= 0) { 944 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 945 } else { 946 tcg_out_insn(s, RIL, LLILF, ret, uval); 947 } 948 uval >>= 32; 949 i = is_const_p16(uval); 950 if (i >= 0) { 951 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 952 } else { 953 tcg_out_insn(s, RIL, OIHF, ret, uval); 954 } 955} 956 957/* Emit a load/store type instruction. Inputs are: 958 DATA: The register to be loaded or stored. 959 BASE+OFS: The effective address. 960 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 961 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 962 963static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 964 TCGReg data, TCGReg base, TCGReg index, 965 tcg_target_long ofs) 966{ 967 if (ofs < -0x80000 || ofs >= 0x80000) { 968 /* Combine the low 20 bits of the offset with the actual load insn; 969 the high 44 bits must come from an immediate load. */ 970 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 971 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 972 ofs = low; 973 974 /* If we were already given an index register, add it in. */ 975 if (index != TCG_REG_NONE) { 976 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 977 } 978 index = TCG_TMP0; 979 } 980 981 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 982 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 983 } else { 984 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 985 } 986} 987 988static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 989 TCGReg data, TCGReg base, TCGReg index, 990 tcg_target_long ofs, int m3) 991{ 992 if (ofs < 0 || ofs >= 0x1000) { 993 if (ofs >= -0x80000 && ofs < 0x80000) { 994 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 995 base = TCG_TMP0; 996 index = TCG_REG_NONE; 997 ofs = 0; 998 } else { 999 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 1000 if (index != TCG_REG_NONE) { 1001 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 1002 } 1003 index = TCG_TMP0; 1004 ofs = 0; 1005 } 1006 } 1007 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 1008} 1009 1010/* load data without address translation or endianness conversion */ 1011static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 1012 TCGReg base, intptr_t ofs) 1013{ 1014 switch (type) { 1015 case TCG_TYPE_I32: 1016 if (likely(is_general_reg(data))) { 1017 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 1018 break; 1019 } 1020 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 1021 break; 1022 1023 case TCG_TYPE_I64: 1024 if (likely(is_general_reg(data))) { 1025 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 1026 break; 1027 } 1028 /* fallthru */ 1029 1030 case TCG_TYPE_V64: 1031 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 1032 break; 1033 1034 case TCG_TYPE_V128: 1035 /* Hint quadword aligned. */ 1036 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 1037 break; 1038 1039 default: 1040 g_assert_not_reached(); 1041 } 1042} 1043 1044static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1045 TCGReg base, intptr_t ofs) 1046{ 1047 switch (type) { 1048 case TCG_TYPE_I32: 1049 if (likely(is_general_reg(data))) { 1050 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1051 } else { 1052 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1053 } 1054 break; 1055 1056 case TCG_TYPE_I64: 1057 if (likely(is_general_reg(data))) { 1058 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1059 break; 1060 } 1061 /* fallthru */ 1062 1063 case TCG_TYPE_V64: 1064 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1065 break; 1066 1067 case TCG_TYPE_V128: 1068 /* Hint quadword aligned. */ 1069 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1070 break; 1071 1072 default: 1073 g_assert_not_reached(); 1074 } 1075} 1076 1077static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1078 TCGReg base, intptr_t ofs) 1079{ 1080 return false; 1081} 1082 1083static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1084{ 1085 return false; 1086} 1087 1088static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1089 tcg_target_long imm) 1090{ 1091 /* This function is only used for passing structs by reference. */ 1092 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1093} 1094 1095static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1096 int msb, int lsb, int ofs, int z) 1097{ 1098 /* Format RIE-f */ 1099 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1100 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1101 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1102} 1103 1104static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1105{ 1106 tcg_out_insn(s, RRE, LGBR, dest, src); 1107} 1108 1109static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1110{ 1111 tcg_out_insn(s, RRE, LLGCR, dest, src); 1112} 1113 1114static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1115{ 1116 tcg_out_insn(s, RRE, LGHR, dest, src); 1117} 1118 1119static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1120{ 1121 tcg_out_insn(s, RRE, LLGHR, dest, src); 1122} 1123 1124static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1125{ 1126 tcg_out_insn(s, RRE, LGFR, dest, src); 1127} 1128 1129static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1130{ 1131 tcg_out_insn(s, RRE, LLGFR, dest, src); 1132} 1133 1134static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1135{ 1136 tcg_out_ext32s(s, dest, src); 1137} 1138 1139static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1140{ 1141 tcg_out_ext32u(s, dest, src); 1142} 1143 1144static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1145{ 1146 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1147} 1148 1149static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1150{ 1151 int msb, lsb; 1152 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1153 /* Achieve wraparound by swapping msb and lsb. */ 1154 msb = 64 - ctz64(~val); 1155 lsb = clz64(~val) - 1; 1156 } else { 1157 msb = clz64(val); 1158 lsb = 63 - ctz64(val); 1159 } 1160 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1161} 1162 1163static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1164{ 1165 static const S390Opcode ni_insns[4] = { 1166 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1167 }; 1168 static const S390Opcode nif_insns[2] = { 1169 RIL_NILF, RIL_NIHF 1170 }; 1171 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1172 int i; 1173 1174 /* Look for the zero-extensions. */ 1175 if ((val & valid) == 0xffffffff) { 1176 tcg_out_ext32u(s, dest, dest); 1177 return; 1178 } 1179 if ((val & valid) == 0xff) { 1180 tcg_out_ext8u(s, dest, dest); 1181 return; 1182 } 1183 if ((val & valid) == 0xffff) { 1184 tcg_out_ext16u(s, dest, dest); 1185 return; 1186 } 1187 1188 i = is_const_p16(~val & valid); 1189 if (i >= 0) { 1190 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1191 return; 1192 } 1193 1194 i = is_const_p32(~val & valid); 1195 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1196 if (i >= 0) { 1197 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1198 return; 1199 } 1200 1201 if (risbg_mask(val)) { 1202 tgen_andi_risbg(s, dest, dest, val); 1203 return; 1204 } 1205 1206 g_assert_not_reached(); 1207} 1208 1209static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1210{ 1211 static const S390Opcode oif_insns[2] = { 1212 RIL_OILF, RIL_OIHF 1213 }; 1214 1215 int i; 1216 1217 i = is_const_p16(val); 1218 if (i >= 0) { 1219 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1220 return; 1221 } 1222 1223 i = is_const_p32(val); 1224 if (i >= 0) { 1225 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1226 return; 1227 } 1228 1229 g_assert_not_reached(); 1230} 1231 1232static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1233{ 1234 switch (is_const_p32(val)) { 1235 case 0: 1236 tcg_out_insn(s, RIL, XILF, dest, val); 1237 break; 1238 case 1: 1239 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1240 break; 1241 default: 1242 g_assert_not_reached(); 1243 } 1244} 1245 1246static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1247 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1248{ 1249 bool is_unsigned = is_unsigned_cond(c); 1250 TCGCond inv_c = tcg_invert_cond(c); 1251 S390Opcode op; 1252 1253 if (is_tst_cond(c)) { 1254 tcg_debug_assert(!need_carry); 1255 1256 if (!c2const) { 1257 if (type == TCG_TYPE_I32) { 1258 tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); 1259 } else { 1260 tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); 1261 } 1262 goto exit; 1263 } 1264 1265 if (type == TCG_TYPE_I32) { 1266 c2 = (uint32_t)c2; 1267 } 1268 1269 int i = is_const_p16(c2); 1270 if (i >= 0) { 1271 tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); 1272 *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; 1273 return *inv_cc ^ 15; 1274 } 1275 1276 if (risbg_mask(c2)) { 1277 tgen_andi_risbg(s, TCG_REG_R0, r1, c2); 1278 goto exit; 1279 } 1280 g_assert_not_reached(); 1281 } 1282 1283 if (c2const) { 1284 if (c2 == 0) { 1285 if (!(is_unsigned && need_carry)) { 1286 if (type == TCG_TYPE_I32) { 1287 tcg_out_insn(s, RR, LTR, r1, r1); 1288 } else { 1289 tcg_out_insn(s, RRE, LTGR, r1, r1); 1290 } 1291 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1292 return tcg_cond_to_ltr_cond[c]; 1293 } 1294 } 1295 1296 if (!is_unsigned && c2 == (int16_t)c2) { 1297 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1298 tcg_out_insn_RI(s, op, r1, c2); 1299 goto exit; 1300 } 1301 1302 if (type == TCG_TYPE_I32) { 1303 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1304 tcg_out_insn_RIL(s, op, r1, c2); 1305 goto exit; 1306 } 1307 1308 /* Should match TCG_CT_CONST_CMP. */ 1309 switch (c) { 1310 case TCG_COND_LT: 1311 case TCG_COND_GE: 1312 case TCG_COND_LE: 1313 case TCG_COND_GT: 1314 tcg_debug_assert(c2 == (int32_t)c2); 1315 op = RIL_CGFI; 1316 break; 1317 case TCG_COND_EQ: 1318 case TCG_COND_NE: 1319 if (c2 == (int32_t)c2) { 1320 op = RIL_CGFI; 1321 break; 1322 } 1323 /* fall through */ 1324 case TCG_COND_LTU: 1325 case TCG_COND_GEU: 1326 case TCG_COND_LEU: 1327 case TCG_COND_GTU: 1328 tcg_debug_assert(c2 == (uint32_t)c2); 1329 op = RIL_CLGFI; 1330 break; 1331 default: 1332 g_assert_not_reached(); 1333 } 1334 tcg_out_insn_RIL(s, op, r1, c2); 1335 } else if (type == TCG_TYPE_I32) { 1336 op = (is_unsigned ? RR_CLR : RR_CR); 1337 tcg_out_insn_RR(s, op, r1, c2); 1338 } else { 1339 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1340 tcg_out_insn_RRE(s, op, r1, c2); 1341 } 1342 1343 exit: 1344 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1345 return tcg_cond_to_s390_cond[c]; 1346} 1347 1348static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1349 TCGArg c2, bool c2const, bool need_carry) 1350{ 1351 int inv_cc; 1352 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1353} 1354 1355static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1356 TCGReg dest, TCGReg c1, TCGArg c2, 1357 bool c2const, bool neg) 1358{ 1359 int cc; 1360 1361 /* With LOC2, we can always emit the minimum 3 insns. */ 1362 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1363 /* Emit: d = 0, d = (cc ? 1 : d). */ 1364 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1365 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1366 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1367 return; 1368 } 1369 1370 switch (cond) { 1371 case TCG_COND_GEU: 1372 case TCG_COND_LTU: 1373 case TCG_COND_LT: 1374 case TCG_COND_GE: 1375 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1376 if (!c2const) { 1377 TCGReg t = c1; 1378 c1 = c2; 1379 c2 = t; 1380 cond = tcg_swap_cond(cond); 1381 } 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 switch (cond) { 1388 case TCG_COND_NE: 1389 /* X != 0 is X > 0. */ 1390 if (c2const && c2 == 0) { 1391 cond = TCG_COND_GTU; 1392 } else { 1393 break; 1394 } 1395 /* fallthru */ 1396 1397 case TCG_COND_GTU: 1398 case TCG_COND_GT: 1399 /* 1400 * The result of a compare has CC=2 for GT and CC=3 unused. 1401 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1402 */ 1403 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1404 tcg_out_movi(s, type, dest, 0); 1405 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1406 if (neg) { 1407 if (type == TCG_TYPE_I32) { 1408 tcg_out_insn(s, RR, LCR, dest, dest); 1409 } else { 1410 tcg_out_insn(s, RRE, LCGR, dest, dest); 1411 } 1412 } 1413 return; 1414 1415 case TCG_COND_EQ: 1416 /* X == 0 is X <= 0. */ 1417 if (c2const && c2 == 0) { 1418 cond = TCG_COND_LEU; 1419 } else { 1420 break; 1421 } 1422 /* fallthru */ 1423 1424 case TCG_COND_LEU: 1425 case TCG_COND_LE: 1426 /* 1427 * As above, but we're looking for borrow, or !carry. 1428 * The second insn computes d - d - borrow, or -1 for true 1429 * and 0 for false. So we must mask to 1 bit afterward. 1430 */ 1431 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1432 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1433 if (!neg) { 1434 tgen_andi(s, type, dest, 1); 1435 } 1436 return; 1437 1438 default: 1439 g_assert_not_reached(); 1440 } 1441 1442 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1443 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1444 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1445 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1446 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1447} 1448 1449static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1450 TCGArg v3, int v3const, TCGReg v4, 1451 int cc, int inv_cc) 1452{ 1453 TCGReg src; 1454 1455 if (v3const) { 1456 if (dest == v4) { 1457 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1458 /* Emit: if (cc) dest = v3. */ 1459 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1460 return; 1461 } 1462 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1463 src = TCG_TMP0; 1464 } else { 1465 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1466 tcg_out_insn(s, RI, LGHI, dest, v3); 1467 cc = inv_cc; 1468 src = v4; 1469 } 1470 } else { 1471 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1472 /* Emit: dest = cc ? v3 : v4. */ 1473 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1474 return; 1475 } 1476 if (dest == v4) { 1477 src = v3; 1478 } else { 1479 tcg_out_mov(s, type, dest, v3); 1480 cc = inv_cc; 1481 src = v4; 1482 } 1483 } 1484 1485 /* Emit: if (cc) dest = src. */ 1486 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1487} 1488 1489static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1490 TCGReg c1, TCGArg c2, int c2const, 1491 TCGArg v3, int v3const, TCGReg v4) 1492{ 1493 int cc, inv_cc; 1494 1495 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1496 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1497} 1498 1499static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1500 TCGArg a2, int a2const) 1501{ 1502 /* Since this sets both R and R+1, we have no choice but to store the 1503 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1504 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1505 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1506 1507 if (a2const && a2 == 64) { 1508 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1509 return; 1510 } 1511 1512 /* 1513 * Conditions from FLOGR are: 1514 * 2 -> one bit found 1515 * 8 -> no one bit found 1516 */ 1517 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1518} 1519 1520static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1521{ 1522 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1523 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1524 if (type == TCG_TYPE_I32) { 1525 tcg_out_ext32u(s, dest, src); 1526 src = dest; 1527 } 1528 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1529 return; 1530 } 1531 1532 /* Without MIE3, each byte gets the count of bits for the byte. */ 1533 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1534 1535 /* Multiply to sum each byte at the top of the word. */ 1536 if (type == TCG_TYPE_I32) { 1537 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1538 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1539 } else { 1540 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1541 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1542 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1543 } 1544} 1545 1546static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1547 int ofs, int len, int z) 1548{ 1549 int lsb = (63 - ofs); 1550 int msb = lsb - (len - 1); 1551 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1552} 1553 1554static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1555 int ofs, int len) 1556{ 1557 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1558} 1559 1560static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1561{ 1562 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1563 if (off == (int16_t)off) { 1564 tcg_out_insn(s, RI, BRC, cc, off); 1565 } else if (off == (int32_t)off) { 1566 tcg_out_insn(s, RIL, BRCL, cc, off); 1567 } else { 1568 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1569 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1570 } 1571} 1572 1573static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1574{ 1575 if (l->has_value) { 1576 tgen_gotoi(s, cc, l->u.value_ptr); 1577 } else { 1578 tcg_out16(s, RI_BRC | (cc << 4)); 1579 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1580 s->code_ptr += 1; 1581 } 1582} 1583 1584static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1585 TCGReg r1, TCGReg r2, TCGLabel *l) 1586{ 1587 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1588 /* Format RIE-b */ 1589 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1590 tcg_out16(s, 0); 1591 tcg_out16(s, cc << 12 | (opc & 0xff)); 1592} 1593 1594static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1595 TCGReg r1, int i2, TCGLabel *l) 1596{ 1597 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1598 /* Format RIE-c */ 1599 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1600 tcg_out16(s, 0); 1601 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1602} 1603 1604static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1605 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1606{ 1607 int cc; 1608 1609 if (!is_tst_cond(c)) { 1610 bool is_unsigned = is_unsigned_cond(c); 1611 bool in_range; 1612 S390Opcode opc; 1613 1614 cc = tcg_cond_to_s390_cond[c]; 1615 1616 if (!c2const) { 1617 opc = (type == TCG_TYPE_I32 1618 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1619 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1620 tgen_compare_branch(s, opc, cc, r1, c2, l); 1621 return; 1622 } 1623 1624 /* 1625 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1626 * If the immediate we've been given does not fit that range, we'll 1627 * fall back to separate compare and branch instructions using the 1628 * larger comparison range afforded by COMPARE IMMEDIATE. 1629 */ 1630 if (type == TCG_TYPE_I32) { 1631 if (is_unsigned) { 1632 opc = RIEc_CLIJ; 1633 in_range = (uint32_t)c2 == (uint8_t)c2; 1634 } else { 1635 opc = RIEc_CIJ; 1636 in_range = (int32_t)c2 == (int8_t)c2; 1637 } 1638 } else { 1639 if (is_unsigned) { 1640 opc = RIEc_CLGIJ; 1641 in_range = (uint64_t)c2 == (uint8_t)c2; 1642 } else { 1643 opc = RIEc_CGIJ; 1644 in_range = (int64_t)c2 == (int8_t)c2; 1645 } 1646 } 1647 if (in_range) { 1648 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1649 return; 1650 } 1651 } 1652 1653 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1654 tgen_branch(s, cc, l); 1655} 1656 1657static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1658{ 1659 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1660 if (off == (int32_t)off) { 1661 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1662 } else { 1663 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1664 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1665 } 1666} 1667 1668static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1669 const TCGHelperInfo *info) 1670{ 1671 tcg_out_call_int(s, dest); 1672} 1673 1674typedef struct { 1675 TCGReg base; 1676 TCGReg index; 1677 int disp; 1678 TCGAtomAlign aa; 1679} HostAddress; 1680 1681bool tcg_target_has_memory_bswap(MemOp memop) 1682{ 1683 TCGAtomAlign aa; 1684 1685 if ((memop & MO_SIZE) <= MO_64) { 1686 return true; 1687 } 1688 1689 /* 1690 * Reject 16-byte memop with 16-byte atomicity, 1691 * but do allow a pair of 64-bit operations. 1692 */ 1693 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1694 return aa.atom <= MO_64; 1695} 1696 1697static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1698 HostAddress h) 1699{ 1700 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1701 case MO_UB: 1702 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1703 break; 1704 case MO_SB: 1705 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1706 break; 1707 1708 case MO_UW | MO_BSWAP: 1709 /* swapped unsigned halfword load with upper bits zeroed */ 1710 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1711 tcg_out_ext16u(s, data, data); 1712 break; 1713 case MO_UW: 1714 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1715 break; 1716 1717 case MO_SW | MO_BSWAP: 1718 /* swapped sign-extended halfword load */ 1719 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1720 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1721 break; 1722 case MO_SW: 1723 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1724 break; 1725 1726 case MO_UL | MO_BSWAP: 1727 /* swapped unsigned int load with upper bits zeroed */ 1728 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1729 tcg_out_ext32u(s, data, data); 1730 break; 1731 case MO_UL: 1732 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1733 break; 1734 1735 case MO_SL | MO_BSWAP: 1736 /* swapped sign-extended int load */ 1737 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1738 tcg_out_ext32s(s, data, data); 1739 break; 1740 case MO_SL: 1741 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1742 break; 1743 1744 case MO_UQ | MO_BSWAP: 1745 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1746 break; 1747 case MO_UQ: 1748 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1749 break; 1750 1751 default: 1752 g_assert_not_reached(); 1753 } 1754} 1755 1756static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1757 HostAddress h) 1758{ 1759 switch (opc & (MO_SIZE | MO_BSWAP)) { 1760 case MO_UB: 1761 if (h.disp >= 0 && h.disp < 0x1000) { 1762 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1763 } else { 1764 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1765 } 1766 break; 1767 1768 case MO_UW | MO_BSWAP: 1769 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1770 break; 1771 case MO_UW: 1772 if (h.disp >= 0 && h.disp < 0x1000) { 1773 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1774 } else { 1775 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1776 } 1777 break; 1778 1779 case MO_UL | MO_BSWAP: 1780 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1781 break; 1782 case MO_UL: 1783 if (h.disp >= 0 && h.disp < 0x1000) { 1784 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1785 } else { 1786 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1787 } 1788 break; 1789 1790 case MO_UQ | MO_BSWAP: 1791 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1792 break; 1793 case MO_UQ: 1794 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1795 break; 1796 1797 default: 1798 g_assert_not_reached(); 1799 } 1800} 1801 1802static const TCGLdstHelperParam ldst_helper_param = { 1803 .ntmp = 1, .tmp = { TCG_TMP0 } 1804}; 1805 1806static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1807{ 1808 MemOp opc = get_memop(lb->oi); 1809 1810 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1811 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1812 return false; 1813 } 1814 1815 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1816 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1817 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1818 1819 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1820 return true; 1821} 1822 1823static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1824{ 1825 MemOp opc = get_memop(lb->oi); 1826 1827 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1828 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1829 return false; 1830 } 1831 1832 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1833 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1834 1835 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1836 return true; 1837} 1838 1839/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1840#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1841 1842/* 1843 * For system-mode, perform the TLB load and compare. 1844 * For user-mode, perform any required alignment tests. 1845 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1846 * is required and fill in @h with the host address for the fast path. 1847 */ 1848static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1849 TCGReg addr_reg, MemOpIdx oi, 1850 bool is_ld) 1851{ 1852 TCGType addr_type = s->addr_type; 1853 TCGLabelQemuLdst *ldst = NULL; 1854 MemOp opc = get_memop(oi); 1855 MemOp s_bits = opc & MO_SIZE; 1856 unsigned a_mask; 1857 1858 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1859 a_mask = (1 << h->aa.align) - 1; 1860 1861 if (tcg_use_softmmu) { 1862 unsigned s_mask = (1 << s_bits) - 1; 1863 int mem_index = get_mmuidx(oi); 1864 int fast_off = tlb_mask_table_ofs(s, mem_index); 1865 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1866 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1867 int ofs, a_off; 1868 uint64_t tlb_mask; 1869 1870 ldst = new_ldst_label(s); 1871 ldst->is_ld = is_ld; 1872 ldst->oi = oi; 1873 ldst->addrlo_reg = addr_reg; 1874 1875 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1876 s->page_bits - CPU_TLB_ENTRY_BITS); 1877 1878 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1879 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1880 1881 /* 1882 * For aligned accesses, we check the first byte and include the 1883 * alignment bits within the address. For unaligned access, we 1884 * check that we don't cross pages using the address of the last 1885 * byte of the access. 1886 */ 1887 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1888 tlb_mask = (uint64_t)s->page_mask | a_mask; 1889 if (a_off == 0) { 1890 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1891 } else { 1892 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1893 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1894 } 1895 1896 if (is_ld) { 1897 ofs = offsetof(CPUTLBEntry, addr_read); 1898 } else { 1899 ofs = offsetof(CPUTLBEntry, addr_write); 1900 } 1901 if (addr_type == TCG_TYPE_I32) { 1902 ofs += HOST_BIG_ENDIAN * 4; 1903 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1904 } else { 1905 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1906 } 1907 1908 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1909 ldst->label_ptr[0] = s->code_ptr++; 1910 1911 h->index = TCG_TMP0; 1912 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1913 offsetof(CPUTLBEntry, addend)); 1914 1915 if (addr_type == TCG_TYPE_I32) { 1916 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1917 h->base = TCG_REG_NONE; 1918 } else { 1919 h->base = addr_reg; 1920 } 1921 h->disp = 0; 1922 } else { 1923 if (a_mask) { 1924 ldst = new_ldst_label(s); 1925 ldst->is_ld = is_ld; 1926 ldst->oi = oi; 1927 ldst->addrlo_reg = addr_reg; 1928 1929 tcg_debug_assert(a_mask <= 0xffff); 1930 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1931 1932 tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); 1933 ldst->label_ptr[0] = s->code_ptr++; 1934 } 1935 1936 h->base = addr_reg; 1937 if (addr_type == TCG_TYPE_I32) { 1938 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1939 h->base = TCG_TMP0; 1940 } 1941 if (guest_base < 0x80000) { 1942 h->index = TCG_REG_NONE; 1943 h->disp = guest_base; 1944 } else { 1945 h->index = TCG_GUEST_BASE_REG; 1946 h->disp = 0; 1947 } 1948 } 1949 1950 return ldst; 1951} 1952 1953static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1954 MemOpIdx oi, TCGType data_type) 1955{ 1956 TCGLabelQemuLdst *ldst; 1957 HostAddress h; 1958 1959 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1960 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 1961 1962 if (ldst) { 1963 ldst->type = data_type; 1964 ldst->datalo_reg = data_reg; 1965 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1966 } 1967} 1968 1969static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1970 MemOpIdx oi, TCGType data_type) 1971{ 1972 TCGLabelQemuLdst *ldst; 1973 HostAddress h; 1974 1975 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1976 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1977 1978 if (ldst) { 1979 ldst->type = data_type; 1980 ldst->datalo_reg = data_reg; 1981 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1982 } 1983} 1984 1985static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 1986 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1987{ 1988 TCGLabel *l1 = NULL, *l2 = NULL; 1989 TCGLabelQemuLdst *ldst; 1990 HostAddress h; 1991 bool need_bswap; 1992 bool use_pair; 1993 S390Opcode insn; 1994 1995 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1996 1997 use_pair = h.aa.atom < MO_128; 1998 need_bswap = get_memop(oi) & MO_BSWAP; 1999 2000 if (!use_pair) { 2001 /* 2002 * Atomicity requires we use LPQ. If we've already checked for 2003 * 16-byte alignment, that's all we need. If we arrive with 2004 * lesser alignment, we have determined that less than 16-byte 2005 * alignment can be satisfied with two 8-byte loads. 2006 */ 2007 if (h.aa.align < MO_128) { 2008 use_pair = true; 2009 l1 = gen_new_label(); 2010 l2 = gen_new_label(); 2011 2012 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 2013 tgen_branch(s, S390_TM_NE, l1); 2014 } 2015 2016 tcg_debug_assert(!need_bswap); 2017 tcg_debug_assert(datalo & 1); 2018 tcg_debug_assert(datahi == datalo - 1); 2019 insn = is_ld ? RXY_LPQ : RXY_STPQ; 2020 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 2021 2022 if (use_pair) { 2023 tgen_branch(s, S390_CC_ALWAYS, l2); 2024 tcg_out_label(s, l1); 2025 } 2026 } 2027 if (use_pair) { 2028 TCGReg d1, d2; 2029 2030 if (need_bswap) { 2031 d1 = datalo, d2 = datahi; 2032 insn = is_ld ? RXY_LRVG : RXY_STRVG; 2033 } else { 2034 d1 = datahi, d2 = datalo; 2035 insn = is_ld ? RXY_LG : RXY_STG; 2036 } 2037 2038 if (h.base == d1 || h.index == d1) { 2039 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 2040 h.base = TCG_TMP0; 2041 h.index = TCG_REG_NONE; 2042 h.disp = 0; 2043 } 2044 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 2045 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 2046 } 2047 if (l2) { 2048 tcg_out_label(s, l2); 2049 } 2050 2051 if (ldst) { 2052 ldst->type = TCG_TYPE_I128; 2053 ldst->datalo_reg = datalo; 2054 ldst->datahi_reg = datahi; 2055 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2056 } 2057} 2058 2059static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2060{ 2061 /* Reuse the zeroing that exists for goto_ptr. */ 2062 if (a0 == 0) { 2063 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 2064 } else { 2065 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 2066 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 2067 } 2068} 2069 2070static void tcg_out_goto_tb(TCGContext *s, int which) 2071{ 2072 /* 2073 * Branch displacement must be aligned for atomic patching; 2074 * see if we need to add extra nop before branch 2075 */ 2076 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 2077 tcg_out16(s, NOP); 2078 } 2079 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 2080 set_jmp_insn_offset(s, which); 2081 s->code_ptr += 2; 2082 set_jmp_reset_offset(s, which); 2083} 2084 2085void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2086 uintptr_t jmp_rx, uintptr_t jmp_rw) 2087{ 2088 if (!HAVE_FACILITY(GEN_INST_EXT)) { 2089 return; 2090 } 2091 /* patch the branch destination */ 2092 uintptr_t addr = tb->jmp_target_addr[n]; 2093 intptr_t disp = addr - (jmp_rx - 2); 2094 qatomic_set((int32_t *)jmp_rw, disp / 2); 2095 /* no need to flush icache explicitly */ 2096} 2097 2098# define OP_32_64(x) \ 2099 case glue(glue(INDEX_op_,x),_i32): \ 2100 case glue(glue(INDEX_op_,x),_i64) 2101 2102static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 2103 const TCGArg args[TCG_MAX_OP_ARGS], 2104 const int const_args[TCG_MAX_OP_ARGS]) 2105{ 2106 S390Opcode op, op2; 2107 TCGArg a0, a1, a2; 2108 2109 switch (opc) { 2110 case INDEX_op_goto_ptr: 2111 a0 = args[0]; 2112 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2113 break; 2114 2115 OP_32_64(ld8u): 2116 /* ??? LLC (RXY format) is only present with the extended-immediate 2117 facility, whereas LLGC is always present. */ 2118 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2119 break; 2120 2121 OP_32_64(ld8s): 2122 /* ??? LB is no smaller than LGB, so no point to using it. */ 2123 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2124 break; 2125 2126 OP_32_64(ld16u): 2127 /* ??? LLH (RXY format) is only present with the extended-immediate 2128 facility, whereas LLGH is always present. */ 2129 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2130 break; 2131 2132 case INDEX_op_ld16s_i32: 2133 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2134 break; 2135 2136 case INDEX_op_ld_i32: 2137 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2138 break; 2139 2140 OP_32_64(st8): 2141 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2142 TCG_REG_NONE, args[2]); 2143 break; 2144 2145 OP_32_64(st16): 2146 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2147 TCG_REG_NONE, args[2]); 2148 break; 2149 2150 case INDEX_op_st_i32: 2151 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2152 break; 2153 2154 case INDEX_op_add_i32: 2155 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2156 if (const_args[2]) { 2157 do_addi_32: 2158 if (a0 == a1) { 2159 if (a2 == (int16_t)a2) { 2160 tcg_out_insn(s, RI, AHI, a0, a2); 2161 break; 2162 } 2163 tcg_out_insn(s, RIL, AFI, a0, a2); 2164 break; 2165 } 2166 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2167 } else if (a0 == a1) { 2168 tcg_out_insn(s, RR, AR, a0, a2); 2169 } else { 2170 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2171 } 2172 break; 2173 case INDEX_op_sub_i32: 2174 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2175 if (const_args[2]) { 2176 a2 = -a2; 2177 goto do_addi_32; 2178 } else if (a0 == a1) { 2179 tcg_out_insn(s, RR, SR, a0, a2); 2180 } else { 2181 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2182 } 2183 break; 2184 2185 case INDEX_op_and_i32: 2186 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2187 if (const_args[2]) { 2188 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2189 tgen_andi(s, TCG_TYPE_I32, a0, a2); 2190 } else if (a0 == a1) { 2191 tcg_out_insn(s, RR, NR, a0, a2); 2192 } else { 2193 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2194 } 2195 break; 2196 case INDEX_op_or_i32: 2197 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2198 if (const_args[2]) { 2199 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2200 tgen_ori(s, a0, a2); 2201 } else if (a0 == a1) { 2202 tcg_out_insn(s, RR, OR, a0, a2); 2203 } else { 2204 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2205 } 2206 break; 2207 case INDEX_op_xor_i32: 2208 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2209 if (const_args[2]) { 2210 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2211 tcg_out_insn(s, RIL, XILF, a0, a2); 2212 } else if (a0 == a1) { 2213 tcg_out_insn(s, RR, XR, args[0], args[2]); 2214 } else { 2215 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2216 } 2217 break; 2218 2219 case INDEX_op_andc_i32: 2220 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2221 if (const_args[2]) { 2222 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2223 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); 2224 } else { 2225 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2226 } 2227 break; 2228 case INDEX_op_orc_i32: 2229 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2230 if (const_args[2]) { 2231 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2232 tgen_ori(s, a0, (uint32_t)~a2); 2233 } else { 2234 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2235 } 2236 break; 2237 case INDEX_op_eqv_i32: 2238 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2239 if (const_args[2]) { 2240 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2241 tcg_out_insn(s, RIL, XILF, a0, ~a2); 2242 } else { 2243 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2244 } 2245 break; 2246 case INDEX_op_nand_i32: 2247 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); 2248 break; 2249 case INDEX_op_nor_i32: 2250 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); 2251 break; 2252 2253 case INDEX_op_neg_i32: 2254 tcg_out_insn(s, RR, LCR, args[0], args[1]); 2255 break; 2256 case INDEX_op_not_i32: 2257 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); 2258 break; 2259 2260 case INDEX_op_mul_i32: 2261 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2262 if (const_args[2]) { 2263 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2264 if (a2 == (int16_t)a2) { 2265 tcg_out_insn(s, RI, MHI, a0, a2); 2266 } else { 2267 tcg_out_insn(s, RIL, MSFI, a0, a2); 2268 } 2269 } else if (a0 == a1) { 2270 tcg_out_insn(s, RRE, MSR, a0, a2); 2271 } else { 2272 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2273 } 2274 break; 2275 2276 case INDEX_op_div2_i32: 2277 tcg_debug_assert(args[0] == args[2]); 2278 tcg_debug_assert(args[1] == args[3]); 2279 tcg_debug_assert((args[1] & 1) == 0); 2280 tcg_debug_assert(args[0] == args[1] + 1); 2281 tcg_out_insn(s, RR, DR, args[1], args[4]); 2282 break; 2283 case INDEX_op_divu2_i32: 2284 tcg_debug_assert(args[0] == args[2]); 2285 tcg_debug_assert(args[1] == args[3]); 2286 tcg_debug_assert((args[1] & 1) == 0); 2287 tcg_debug_assert(args[0] == args[1] + 1); 2288 tcg_out_insn(s, RRE, DLR, args[1], args[4]); 2289 break; 2290 2291 case INDEX_op_shl_i32: 2292 op = RS_SLL; 2293 op2 = RSY_SLLK; 2294 do_shift32: 2295 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2296 if (a0 == a1) { 2297 if (const_args[2]) { 2298 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2299 } else { 2300 tcg_out_sh32(s, op, a0, a2, 0); 2301 } 2302 } else { 2303 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2304 if (const_args[2]) { 2305 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2306 } else { 2307 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2308 } 2309 } 2310 break; 2311 case INDEX_op_shr_i32: 2312 op = RS_SRL; 2313 op2 = RSY_SRLK; 2314 goto do_shift32; 2315 case INDEX_op_sar_i32: 2316 op = RS_SRA; 2317 op2 = RSY_SRAK; 2318 goto do_shift32; 2319 2320 case INDEX_op_rotl_i32: 2321 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2322 if (const_args[2]) { 2323 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2324 } else { 2325 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2326 } 2327 break; 2328 case INDEX_op_rotr_i32: 2329 if (const_args[2]) { 2330 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2331 TCG_REG_NONE, (32 - args[2]) & 31); 2332 } else { 2333 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2334 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2335 } 2336 break; 2337 2338 case INDEX_op_bswap16_i32: 2339 a0 = args[0], a1 = args[1], a2 = args[2]; 2340 tcg_out_insn(s, RRE, LRVR, a0, a1); 2341 if (a2 & TCG_BSWAP_OS) { 2342 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2343 } else { 2344 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2345 } 2346 break; 2347 case INDEX_op_bswap16_i64: 2348 a0 = args[0], a1 = args[1], a2 = args[2]; 2349 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2350 if (a2 & TCG_BSWAP_OS) { 2351 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2352 } else { 2353 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2354 } 2355 break; 2356 2357 case INDEX_op_bswap32_i32: 2358 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2359 break; 2360 case INDEX_op_bswap32_i64: 2361 a0 = args[0], a1 = args[1], a2 = args[2]; 2362 tcg_out_insn(s, RRE, LRVR, a0, a1); 2363 if (a2 & TCG_BSWAP_OS) { 2364 tcg_out_ext32s(s, a0, a0); 2365 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2366 tcg_out_ext32u(s, a0, a0); 2367 } 2368 break; 2369 2370 case INDEX_op_add2_i32: 2371 if (const_args[4]) { 2372 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2373 } else { 2374 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2375 } 2376 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2377 break; 2378 case INDEX_op_sub2_i32: 2379 if (const_args[4]) { 2380 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2381 } else { 2382 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2383 } 2384 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2385 break; 2386 2387 case INDEX_op_br: 2388 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2389 break; 2390 2391 case INDEX_op_brcond_i32: 2392 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2393 args[1], const_args[1], arg_label(args[3])); 2394 break; 2395 case INDEX_op_setcond_i32: 2396 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2397 args[2], const_args[2], false); 2398 break; 2399 case INDEX_op_negsetcond_i32: 2400 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2401 args[2], const_args[2], true); 2402 break; 2403 case INDEX_op_movcond_i32: 2404 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2405 args[2], const_args[2], args[3], const_args[3], args[4]); 2406 break; 2407 2408 case INDEX_op_qemu_ld_a32_i32: 2409 case INDEX_op_qemu_ld_a64_i32: 2410 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2411 break; 2412 case INDEX_op_qemu_ld_a32_i64: 2413 case INDEX_op_qemu_ld_a64_i64: 2414 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2415 break; 2416 case INDEX_op_qemu_st_a32_i32: 2417 case INDEX_op_qemu_st_a64_i32: 2418 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2419 break; 2420 case INDEX_op_qemu_st_a32_i64: 2421 case INDEX_op_qemu_st_a64_i64: 2422 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2423 break; 2424 case INDEX_op_qemu_ld_a32_i128: 2425 case INDEX_op_qemu_ld_a64_i128: 2426 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2427 break; 2428 case INDEX_op_qemu_st_a32_i128: 2429 case INDEX_op_qemu_st_a64_i128: 2430 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2431 break; 2432 2433 case INDEX_op_ld16s_i64: 2434 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2435 break; 2436 case INDEX_op_ld32u_i64: 2437 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2438 break; 2439 case INDEX_op_ld32s_i64: 2440 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2441 break; 2442 case INDEX_op_ld_i64: 2443 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2444 break; 2445 2446 case INDEX_op_st32_i64: 2447 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2448 break; 2449 case INDEX_op_st_i64: 2450 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2451 break; 2452 2453 case INDEX_op_add_i64: 2454 a0 = args[0], a1 = args[1], a2 = args[2]; 2455 if (const_args[2]) { 2456 do_addi_64: 2457 if (a0 == a1) { 2458 if (a2 == (int16_t)a2) { 2459 tcg_out_insn(s, RI, AGHI, a0, a2); 2460 break; 2461 } 2462 if (a2 == (int32_t)a2) { 2463 tcg_out_insn(s, RIL, AGFI, a0, a2); 2464 break; 2465 } 2466 if (a2 == (uint32_t)a2) { 2467 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2468 break; 2469 } 2470 if (-a2 == (uint32_t)-a2) { 2471 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2472 break; 2473 } 2474 } 2475 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2476 } else if (a0 == a1) { 2477 tcg_out_insn(s, RRE, AGR, a0, a2); 2478 } else { 2479 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2480 } 2481 break; 2482 case INDEX_op_sub_i64: 2483 a0 = args[0], a1 = args[1], a2 = args[2]; 2484 if (const_args[2]) { 2485 a2 = -a2; 2486 goto do_addi_64; 2487 } else { 2488 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2489 } 2490 break; 2491 2492 case INDEX_op_and_i64: 2493 a0 = args[0], a1 = args[1], a2 = args[2]; 2494 if (const_args[2]) { 2495 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2496 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); 2497 } else { 2498 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2499 } 2500 break; 2501 case INDEX_op_or_i64: 2502 a0 = args[0], a1 = args[1], a2 = args[2]; 2503 if (const_args[2]) { 2504 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2505 tgen_ori(s, a0, a2); 2506 } else { 2507 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2508 } 2509 break; 2510 case INDEX_op_xor_i64: 2511 a0 = args[0], a1 = args[1], a2 = args[2]; 2512 if (const_args[2]) { 2513 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2514 tgen_xori(s, a0, a2); 2515 } else { 2516 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2517 } 2518 break; 2519 2520 case INDEX_op_andc_i64: 2521 a0 = args[0], a1 = args[1], a2 = args[2]; 2522 if (const_args[2]) { 2523 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2524 tgen_andi(s, TCG_TYPE_I64, a0, ~a2); 2525 } else { 2526 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2527 } 2528 break; 2529 case INDEX_op_orc_i64: 2530 a0 = args[0], a1 = args[1], a2 = args[2]; 2531 if (const_args[2]) { 2532 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2533 tgen_ori(s, a0, ~a2); 2534 } else { 2535 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2536 } 2537 break; 2538 case INDEX_op_eqv_i64: 2539 a0 = args[0], a1 = args[1], a2 = args[2]; 2540 if (const_args[2]) { 2541 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2542 tgen_xori(s, a0, ~a2); 2543 } else { 2544 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2545 } 2546 break; 2547 case INDEX_op_nand_i64: 2548 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); 2549 break; 2550 case INDEX_op_nor_i64: 2551 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); 2552 break; 2553 2554 case INDEX_op_neg_i64: 2555 tcg_out_insn(s, RRE, LCGR, args[0], args[1]); 2556 break; 2557 case INDEX_op_not_i64: 2558 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); 2559 break; 2560 case INDEX_op_bswap64_i64: 2561 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2562 break; 2563 2564 case INDEX_op_mul_i64: 2565 a0 = args[0], a1 = args[1], a2 = args[2]; 2566 if (const_args[2]) { 2567 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2568 if (a2 == (int16_t)a2) { 2569 tcg_out_insn(s, RI, MGHI, a0, a2); 2570 } else { 2571 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2572 } 2573 } else if (a0 == a1) { 2574 tcg_out_insn(s, RRE, MSGR, a0, a2); 2575 } else { 2576 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2577 } 2578 break; 2579 2580 case INDEX_op_div2_i64: 2581 /* 2582 * ??? We get an unnecessary sign-extension of the dividend 2583 * into op0 with this definition, but as we do in fact always 2584 * produce both quotient and remainder using INDEX_op_div_i64 2585 * instead requires jumping through even more hoops. 2586 */ 2587 tcg_debug_assert(args[0] == args[2]); 2588 tcg_debug_assert(args[1] == args[3]); 2589 tcg_debug_assert((args[1] & 1) == 0); 2590 tcg_debug_assert(args[0] == args[1] + 1); 2591 tcg_out_insn(s, RRE, DSGR, args[1], args[4]); 2592 break; 2593 case INDEX_op_divu2_i64: 2594 tcg_debug_assert(args[0] == args[2]); 2595 tcg_debug_assert(args[1] == args[3]); 2596 tcg_debug_assert((args[1] & 1) == 0); 2597 tcg_debug_assert(args[0] == args[1] + 1); 2598 tcg_out_insn(s, RRE, DLGR, args[1], args[4]); 2599 break; 2600 case INDEX_op_mulu2_i64: 2601 tcg_debug_assert(args[0] == args[2]); 2602 tcg_debug_assert((args[1] & 1) == 0); 2603 tcg_debug_assert(args[0] == args[1] + 1); 2604 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2605 break; 2606 case INDEX_op_muls2_i64: 2607 tcg_debug_assert((args[1] & 1) == 0); 2608 tcg_debug_assert(args[0] == args[1] + 1); 2609 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2610 break; 2611 2612 case INDEX_op_shl_i64: 2613 op = RSY_SLLG; 2614 do_shift64: 2615 if (const_args[2]) { 2616 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2617 } else { 2618 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2619 } 2620 break; 2621 case INDEX_op_shr_i64: 2622 op = RSY_SRLG; 2623 goto do_shift64; 2624 case INDEX_op_sar_i64: 2625 op = RSY_SRAG; 2626 goto do_shift64; 2627 2628 case INDEX_op_rotl_i64: 2629 if (const_args[2]) { 2630 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2631 TCG_REG_NONE, args[2]); 2632 } else { 2633 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2634 } 2635 break; 2636 case INDEX_op_rotr_i64: 2637 if (const_args[2]) { 2638 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2639 TCG_REG_NONE, (64 - args[2]) & 63); 2640 } else { 2641 /* We can use the smaller 32-bit negate because only the 2642 low 6 bits are examined for the rotate. */ 2643 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2644 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2645 } 2646 break; 2647 2648 case INDEX_op_add2_i64: 2649 if (const_args[4]) { 2650 if ((int64_t)args[4] >= 0) { 2651 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2652 } else { 2653 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2654 } 2655 } else { 2656 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2657 } 2658 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2659 break; 2660 case INDEX_op_sub2_i64: 2661 if (const_args[4]) { 2662 if ((int64_t)args[4] >= 0) { 2663 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2664 } else { 2665 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2666 } 2667 } else { 2668 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2669 } 2670 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2671 break; 2672 2673 case INDEX_op_brcond_i64: 2674 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2675 args[1], const_args[1], arg_label(args[3])); 2676 break; 2677 case INDEX_op_setcond_i64: 2678 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2679 args[2], const_args[2], false); 2680 break; 2681 case INDEX_op_negsetcond_i64: 2682 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2683 args[2], const_args[2], true); 2684 break; 2685 case INDEX_op_movcond_i64: 2686 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2687 args[2], const_args[2], args[3], const_args[3], args[4]); 2688 break; 2689 2690 OP_32_64(deposit): 2691 a0 = args[0], a1 = args[1], a2 = args[2]; 2692 if (const_args[1]) { 2693 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2694 } else { 2695 /* Since we can't support "0Z" as a constraint, we allow a1 in 2696 any register. Fix things up as if a matching constraint. */ 2697 if (a0 != a1) { 2698 TCGType type = (opc == INDEX_op_deposit_i64); 2699 if (a0 == a2) { 2700 tcg_out_mov(s, type, TCG_TMP0, a2); 2701 a2 = TCG_TMP0; 2702 } 2703 tcg_out_mov(s, type, a0, a1); 2704 } 2705 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2706 } 2707 break; 2708 2709 OP_32_64(extract): 2710 tgen_extract(s, args[0], args[1], args[2], args[3]); 2711 break; 2712 2713 case INDEX_op_clz_i64: 2714 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2715 break; 2716 2717 case INDEX_op_ctpop_i32: 2718 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2719 break; 2720 case INDEX_op_ctpop_i64: 2721 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2722 break; 2723 2724 case INDEX_op_mb: 2725 /* The host memory model is quite strong, we simply need to 2726 serialize the instruction stream. */ 2727 if (args[0] & TCG_MO_ST_LD) { 2728 /* fast-bcr-serialization facility (45) is present */ 2729 tcg_out_insn(s, RR, BCR, 14, 0); 2730 } 2731 break; 2732 2733 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2734 case INDEX_op_mov_i64: 2735 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2736 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2737 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2738 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2739 case INDEX_op_ext8s_i64: 2740 case INDEX_op_ext8u_i32: 2741 case INDEX_op_ext8u_i64: 2742 case INDEX_op_ext16s_i32: 2743 case INDEX_op_ext16s_i64: 2744 case INDEX_op_ext16u_i32: 2745 case INDEX_op_ext16u_i64: 2746 case INDEX_op_ext32s_i64: 2747 case INDEX_op_ext32u_i64: 2748 case INDEX_op_ext_i32_i64: 2749 case INDEX_op_extu_i32_i64: 2750 case INDEX_op_extrl_i64_i32: 2751 default: 2752 g_assert_not_reached(); 2753 } 2754} 2755 2756static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2757 TCGReg dst, TCGReg src) 2758{ 2759 if (is_general_reg(src)) { 2760 /* Replicate general register into two MO_64. */ 2761 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2762 if (vece == MO_64) { 2763 return true; 2764 } 2765 src = dst; 2766 } 2767 2768 /* 2769 * Recall that the "standard" integer, within a vector, is the 2770 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2771 */ 2772 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2773 return true; 2774} 2775 2776static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2777 TCGReg dst, TCGReg base, intptr_t offset) 2778{ 2779 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2780 return true; 2781} 2782 2783static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2784 TCGReg dst, int64_t val) 2785{ 2786 int i, mask, msb, lsb; 2787 2788 /* Look for int16_t elements. */ 2789 if (vece <= MO_16 || 2790 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2791 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2792 return; 2793 } 2794 2795 /* Look for bit masks. */ 2796 if (vece == MO_32) { 2797 if (risbg_mask((int32_t)val)) { 2798 /* Handle wraparound by swapping msb and lsb. */ 2799 if ((val & 0x80000001u) == 0x80000001u) { 2800 msb = 32 - ctz32(~val); 2801 lsb = clz32(~val) - 1; 2802 } else { 2803 msb = clz32(val); 2804 lsb = 31 - ctz32(val); 2805 } 2806 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2807 return; 2808 } 2809 } else { 2810 if (risbg_mask(val)) { 2811 /* Handle wraparound by swapping msb and lsb. */ 2812 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2813 /* Handle wraparound by swapping msb and lsb. */ 2814 msb = 64 - ctz64(~val); 2815 lsb = clz64(~val) - 1; 2816 } else { 2817 msb = clz64(val); 2818 lsb = 63 - ctz64(val); 2819 } 2820 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2821 return; 2822 } 2823 } 2824 2825 /* Look for all bytes 0x00 or 0xff. */ 2826 for (i = mask = 0; i < 8; i++) { 2827 uint8_t byte = val >> (i * 8); 2828 if (byte == 0xff) { 2829 mask |= 1 << i; 2830 } else if (byte != 0) { 2831 break; 2832 } 2833 } 2834 if (i == 8) { 2835 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2836 return; 2837 } 2838 2839 /* Otherwise, stuff it in the constant pool. */ 2840 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2841 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2842 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2843} 2844 2845static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 2846 TCGReg a1, TCGReg a2, TCGCond cond) 2847{ 2848 bool need_swap = false, need_inv = false; 2849 2850 switch (cond) { 2851 case TCG_COND_EQ: 2852 case TCG_COND_GT: 2853 case TCG_COND_GTU: 2854 break; 2855 case TCG_COND_NE: 2856 case TCG_COND_LE: 2857 case TCG_COND_LEU: 2858 need_inv = true; 2859 break; 2860 case TCG_COND_LT: 2861 case TCG_COND_LTU: 2862 need_swap = true; 2863 break; 2864 case TCG_COND_GE: 2865 case TCG_COND_GEU: 2866 need_swap = need_inv = true; 2867 break; 2868 default: 2869 g_assert_not_reached(); 2870 } 2871 2872 if (need_inv) { 2873 cond = tcg_invert_cond(cond); 2874 } 2875 if (need_swap) { 2876 TCGReg swap = a1; 2877 a1 = a2; 2878 a2 = swap; 2879 cond = tcg_swap_cond(cond); 2880 } 2881 2882 switch (cond) { 2883 case TCG_COND_EQ: 2884 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 2885 break; 2886 case TCG_COND_GT: 2887 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 2888 break; 2889 case TCG_COND_GTU: 2890 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 2891 break; 2892 default: 2893 g_assert_not_reached(); 2894 } 2895 return need_inv; 2896} 2897 2898static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 2899 TCGReg a1, TCGReg a2, TCGCond cond) 2900{ 2901 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 2902 tcg_out_insn(s, VRRc, VNO, a0, a0, a0, 0); 2903 } 2904} 2905 2906static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 2907 TCGReg c1, TCGReg c2, 2908 TCGReg v3, TCGReg v4, TCGCond cond) 2909{ 2910 if (tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP0, c1, c2, cond)) { 2911 TCGReg swap = v3; 2912 v3 = v4; 2913 v4 = swap; 2914 } 2915 tcg_out_insn(s, VRRe, VSEL, a0, v3, v4, TCG_VEC_TMP0); 2916} 2917 2918static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2919 unsigned vecl, unsigned vece, 2920 const TCGArg args[TCG_MAX_OP_ARGS], 2921 const int const_args[TCG_MAX_OP_ARGS]) 2922{ 2923 TCGType type = vecl + TCG_TYPE_V64; 2924 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 2925 2926 switch (opc) { 2927 case INDEX_op_ld_vec: 2928 tcg_out_ld(s, type, a0, a1, a2); 2929 break; 2930 case INDEX_op_st_vec: 2931 tcg_out_st(s, type, a0, a1, a2); 2932 break; 2933 case INDEX_op_dupm_vec: 2934 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2935 break; 2936 2937 case INDEX_op_abs_vec: 2938 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 2939 break; 2940 case INDEX_op_neg_vec: 2941 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 2942 break; 2943 case INDEX_op_not_vec: 2944 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 2945 break; 2946 2947 case INDEX_op_add_vec: 2948 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 2949 break; 2950 case INDEX_op_sub_vec: 2951 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 2952 break; 2953 case INDEX_op_and_vec: 2954 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 2955 break; 2956 case INDEX_op_andc_vec: 2957 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 2958 break; 2959 case INDEX_op_mul_vec: 2960 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 2961 break; 2962 case INDEX_op_or_vec: 2963 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 2964 break; 2965 case INDEX_op_orc_vec: 2966 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 2967 break; 2968 case INDEX_op_xor_vec: 2969 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 2970 break; 2971 case INDEX_op_nand_vec: 2972 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 2973 break; 2974 case INDEX_op_nor_vec: 2975 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 2976 break; 2977 case INDEX_op_eqv_vec: 2978 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 2979 break; 2980 2981 case INDEX_op_shli_vec: 2982 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 2983 break; 2984 case INDEX_op_shri_vec: 2985 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 2986 break; 2987 case INDEX_op_sari_vec: 2988 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 2989 break; 2990 case INDEX_op_rotli_vec: 2991 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 2992 break; 2993 case INDEX_op_shls_vec: 2994 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 2995 break; 2996 case INDEX_op_shrs_vec: 2997 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 2998 break; 2999 case INDEX_op_sars_vec: 3000 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 3001 break; 3002 case INDEX_op_rotls_vec: 3003 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 3004 break; 3005 case INDEX_op_shlv_vec: 3006 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 3007 break; 3008 case INDEX_op_shrv_vec: 3009 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 3010 break; 3011 case INDEX_op_sarv_vec: 3012 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 3013 break; 3014 case INDEX_op_rotlv_vec: 3015 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 3016 break; 3017 3018 case INDEX_op_smin_vec: 3019 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 3020 break; 3021 case INDEX_op_smax_vec: 3022 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 3023 break; 3024 case INDEX_op_umin_vec: 3025 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 3026 break; 3027 case INDEX_op_umax_vec: 3028 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 3029 break; 3030 3031 case INDEX_op_bitsel_vec: 3032 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 3033 break; 3034 3035 case INDEX_op_cmp_vec: 3036 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 3037 break; 3038 case INDEX_op_cmpsel_vec: 3039 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, args[3], args[4], args[5]); 3040 break; 3041 3042 case INDEX_op_s390_vuph_vec: 3043 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 3044 break; 3045 case INDEX_op_s390_vupl_vec: 3046 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 3047 break; 3048 case INDEX_op_s390_vpks_vec: 3049 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 3050 break; 3051 3052 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3053 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3054 default: 3055 g_assert_not_reached(); 3056 } 3057} 3058 3059int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3060{ 3061 switch (opc) { 3062 case INDEX_op_abs_vec: 3063 case INDEX_op_add_vec: 3064 case INDEX_op_and_vec: 3065 case INDEX_op_andc_vec: 3066 case INDEX_op_bitsel_vec: 3067 case INDEX_op_eqv_vec: 3068 case INDEX_op_nand_vec: 3069 case INDEX_op_neg_vec: 3070 case INDEX_op_nor_vec: 3071 case INDEX_op_not_vec: 3072 case INDEX_op_or_vec: 3073 case INDEX_op_orc_vec: 3074 case INDEX_op_rotli_vec: 3075 case INDEX_op_rotls_vec: 3076 case INDEX_op_rotlv_vec: 3077 case INDEX_op_sari_vec: 3078 case INDEX_op_sars_vec: 3079 case INDEX_op_sarv_vec: 3080 case INDEX_op_shli_vec: 3081 case INDEX_op_shls_vec: 3082 case INDEX_op_shlv_vec: 3083 case INDEX_op_shri_vec: 3084 case INDEX_op_shrs_vec: 3085 case INDEX_op_shrv_vec: 3086 case INDEX_op_smax_vec: 3087 case INDEX_op_smin_vec: 3088 case INDEX_op_sub_vec: 3089 case INDEX_op_umax_vec: 3090 case INDEX_op_umin_vec: 3091 case INDEX_op_xor_vec: 3092 case INDEX_op_cmp_vec: 3093 case INDEX_op_cmpsel_vec: 3094 return 1; 3095 case INDEX_op_rotrv_vec: 3096 return -1; 3097 case INDEX_op_mul_vec: 3098 return vece < MO_64; 3099 case INDEX_op_ssadd_vec: 3100 case INDEX_op_sssub_vec: 3101 return vece < MO_64 ? -1 : 0; 3102 default: 3103 return 0; 3104 } 3105} 3106 3107static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3108 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3109{ 3110 TCGv_vec h1 = tcg_temp_new_vec(type); 3111 TCGv_vec h2 = tcg_temp_new_vec(type); 3112 TCGv_vec l1 = tcg_temp_new_vec(type); 3113 TCGv_vec l2 = tcg_temp_new_vec(type); 3114 3115 tcg_debug_assert (vece < MO_64); 3116 3117 /* Unpack with sign-extension. */ 3118 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3119 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3120 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3121 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3122 3123 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3124 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3125 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3126 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3127 3128 /* Arithmetic on a wider element size. */ 3129 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3130 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3131 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3132 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3133 3134 /* Pack with saturation. */ 3135 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3136 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3137 3138 tcg_temp_free_vec(h1); 3139 tcg_temp_free_vec(h2); 3140 tcg_temp_free_vec(l1); 3141 tcg_temp_free_vec(l2); 3142} 3143 3144void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3145 TCGArg a0, ...) 3146{ 3147 va_list va; 3148 TCGv_vec v0, v1, v2, t0; 3149 3150 va_start(va, a0); 3151 v0 = temp_tcgv_vec(arg_temp(a0)); 3152 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3153 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3154 3155 switch (opc) { 3156 case INDEX_op_rotrv_vec: 3157 t0 = tcg_temp_new_vec(type); 3158 tcg_gen_neg_vec(vece, t0, v2); 3159 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3160 tcg_temp_free_vec(t0); 3161 break; 3162 3163 case INDEX_op_ssadd_vec: 3164 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3165 break; 3166 case INDEX_op_sssub_vec: 3167 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3168 break; 3169 3170 default: 3171 g_assert_not_reached(); 3172 } 3173 va_end(va); 3174} 3175 3176static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3177{ 3178 switch (op) { 3179 case INDEX_op_goto_ptr: 3180 return C_O0_I1(r); 3181 3182 case INDEX_op_ld8u_i32: 3183 case INDEX_op_ld8u_i64: 3184 case INDEX_op_ld8s_i32: 3185 case INDEX_op_ld8s_i64: 3186 case INDEX_op_ld16u_i32: 3187 case INDEX_op_ld16u_i64: 3188 case INDEX_op_ld16s_i32: 3189 case INDEX_op_ld16s_i64: 3190 case INDEX_op_ld_i32: 3191 case INDEX_op_ld32u_i64: 3192 case INDEX_op_ld32s_i64: 3193 case INDEX_op_ld_i64: 3194 return C_O1_I1(r, r); 3195 3196 case INDEX_op_st8_i32: 3197 case INDEX_op_st8_i64: 3198 case INDEX_op_st16_i32: 3199 case INDEX_op_st16_i64: 3200 case INDEX_op_st_i32: 3201 case INDEX_op_st32_i64: 3202 case INDEX_op_st_i64: 3203 return C_O0_I2(r, r); 3204 3205 case INDEX_op_add_i32: 3206 case INDEX_op_add_i64: 3207 case INDEX_op_shl_i64: 3208 case INDEX_op_shr_i64: 3209 case INDEX_op_sar_i64: 3210 case INDEX_op_rotl_i32: 3211 case INDEX_op_rotl_i64: 3212 case INDEX_op_rotr_i32: 3213 case INDEX_op_rotr_i64: 3214 case INDEX_op_setcond_i32: 3215 case INDEX_op_negsetcond_i32: 3216 return C_O1_I2(r, r, ri); 3217 case INDEX_op_setcond_i64: 3218 case INDEX_op_negsetcond_i64: 3219 return C_O1_I2(r, r, rC); 3220 3221 case INDEX_op_clz_i64: 3222 return C_O1_I2(r, r, rI); 3223 3224 case INDEX_op_sub_i32: 3225 case INDEX_op_sub_i64: 3226 case INDEX_op_and_i32: 3227 case INDEX_op_or_i32: 3228 case INDEX_op_xor_i32: 3229 return C_O1_I2(r, r, ri); 3230 case INDEX_op_and_i64: 3231 return C_O1_I2(r, r, rNKR); 3232 case INDEX_op_or_i64: 3233 case INDEX_op_xor_i64: 3234 return C_O1_I2(r, r, rK); 3235 3236 case INDEX_op_andc_i32: 3237 case INDEX_op_orc_i32: 3238 case INDEX_op_eqv_i32: 3239 return C_O1_I2(r, r, ri); 3240 case INDEX_op_andc_i64: 3241 return C_O1_I2(r, r, rKR); 3242 case INDEX_op_orc_i64: 3243 case INDEX_op_eqv_i64: 3244 return C_O1_I2(r, r, rNK); 3245 3246 case INDEX_op_nand_i32: 3247 case INDEX_op_nand_i64: 3248 case INDEX_op_nor_i32: 3249 case INDEX_op_nor_i64: 3250 return C_O1_I2(r, r, r); 3251 3252 case INDEX_op_mul_i32: 3253 return (HAVE_FACILITY(MISC_INSN_EXT2) 3254 ? C_O1_I2(r, r, ri) 3255 : C_O1_I2(r, 0, ri)); 3256 case INDEX_op_mul_i64: 3257 return (HAVE_FACILITY(MISC_INSN_EXT2) 3258 ? C_O1_I2(r, r, rJ) 3259 : C_O1_I2(r, 0, rJ)); 3260 3261 case INDEX_op_shl_i32: 3262 case INDEX_op_shr_i32: 3263 case INDEX_op_sar_i32: 3264 return C_O1_I2(r, r, ri); 3265 3266 case INDEX_op_brcond_i32: 3267 return C_O0_I2(r, ri); 3268 case INDEX_op_brcond_i64: 3269 return C_O0_I2(r, rC); 3270 3271 case INDEX_op_bswap16_i32: 3272 case INDEX_op_bswap16_i64: 3273 case INDEX_op_bswap32_i32: 3274 case INDEX_op_bswap32_i64: 3275 case INDEX_op_bswap64_i64: 3276 case INDEX_op_neg_i32: 3277 case INDEX_op_neg_i64: 3278 case INDEX_op_not_i32: 3279 case INDEX_op_not_i64: 3280 case INDEX_op_ext8s_i32: 3281 case INDEX_op_ext8s_i64: 3282 case INDEX_op_ext8u_i32: 3283 case INDEX_op_ext8u_i64: 3284 case INDEX_op_ext16s_i32: 3285 case INDEX_op_ext16s_i64: 3286 case INDEX_op_ext16u_i32: 3287 case INDEX_op_ext16u_i64: 3288 case INDEX_op_ext32s_i64: 3289 case INDEX_op_ext32u_i64: 3290 case INDEX_op_ext_i32_i64: 3291 case INDEX_op_extu_i32_i64: 3292 case INDEX_op_extract_i32: 3293 case INDEX_op_extract_i64: 3294 case INDEX_op_ctpop_i32: 3295 case INDEX_op_ctpop_i64: 3296 return C_O1_I1(r, r); 3297 3298 case INDEX_op_qemu_ld_a32_i32: 3299 case INDEX_op_qemu_ld_a64_i32: 3300 case INDEX_op_qemu_ld_a32_i64: 3301 case INDEX_op_qemu_ld_a64_i64: 3302 return C_O1_I1(r, r); 3303 case INDEX_op_qemu_st_a32_i64: 3304 case INDEX_op_qemu_st_a64_i64: 3305 case INDEX_op_qemu_st_a32_i32: 3306 case INDEX_op_qemu_st_a64_i32: 3307 return C_O0_I2(r, r); 3308 case INDEX_op_qemu_ld_a32_i128: 3309 case INDEX_op_qemu_ld_a64_i128: 3310 return C_O2_I1(o, m, r); 3311 case INDEX_op_qemu_st_a32_i128: 3312 case INDEX_op_qemu_st_a64_i128: 3313 return C_O0_I3(o, m, r); 3314 3315 case INDEX_op_deposit_i32: 3316 case INDEX_op_deposit_i64: 3317 return C_O1_I2(r, rZ, r); 3318 3319 case INDEX_op_movcond_i32: 3320 return C_O1_I4(r, r, ri, rI, r); 3321 case INDEX_op_movcond_i64: 3322 return C_O1_I4(r, r, rC, rI, r); 3323 3324 case INDEX_op_div2_i32: 3325 case INDEX_op_div2_i64: 3326 case INDEX_op_divu2_i32: 3327 case INDEX_op_divu2_i64: 3328 return C_O2_I3(o, m, 0, 1, r); 3329 3330 case INDEX_op_mulu2_i64: 3331 return C_O2_I2(o, m, 0, r); 3332 case INDEX_op_muls2_i64: 3333 return C_O2_I2(o, m, r, r); 3334 3335 case INDEX_op_add2_i32: 3336 case INDEX_op_sub2_i32: 3337 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3338 3339 case INDEX_op_add2_i64: 3340 case INDEX_op_sub2_i64: 3341 return C_N1_O1_I4(r, r, 0, 1, rJU, r); 3342 3343 case INDEX_op_st_vec: 3344 return C_O0_I2(v, r); 3345 case INDEX_op_ld_vec: 3346 case INDEX_op_dupm_vec: 3347 return C_O1_I1(v, r); 3348 case INDEX_op_dup_vec: 3349 return C_O1_I1(v, vr); 3350 case INDEX_op_abs_vec: 3351 case INDEX_op_neg_vec: 3352 case INDEX_op_not_vec: 3353 case INDEX_op_rotli_vec: 3354 case INDEX_op_sari_vec: 3355 case INDEX_op_shli_vec: 3356 case INDEX_op_shri_vec: 3357 case INDEX_op_s390_vuph_vec: 3358 case INDEX_op_s390_vupl_vec: 3359 return C_O1_I1(v, v); 3360 case INDEX_op_add_vec: 3361 case INDEX_op_sub_vec: 3362 case INDEX_op_and_vec: 3363 case INDEX_op_andc_vec: 3364 case INDEX_op_or_vec: 3365 case INDEX_op_orc_vec: 3366 case INDEX_op_xor_vec: 3367 case INDEX_op_nand_vec: 3368 case INDEX_op_nor_vec: 3369 case INDEX_op_eqv_vec: 3370 case INDEX_op_cmp_vec: 3371 case INDEX_op_mul_vec: 3372 case INDEX_op_rotlv_vec: 3373 case INDEX_op_rotrv_vec: 3374 case INDEX_op_shlv_vec: 3375 case INDEX_op_shrv_vec: 3376 case INDEX_op_sarv_vec: 3377 case INDEX_op_smax_vec: 3378 case INDEX_op_smin_vec: 3379 case INDEX_op_umax_vec: 3380 case INDEX_op_umin_vec: 3381 case INDEX_op_s390_vpks_vec: 3382 return C_O1_I2(v, v, v); 3383 case INDEX_op_rotls_vec: 3384 case INDEX_op_shls_vec: 3385 case INDEX_op_shrs_vec: 3386 case INDEX_op_sars_vec: 3387 return C_O1_I2(v, v, r); 3388 case INDEX_op_bitsel_vec: 3389 return C_O1_I3(v, v, v, v); 3390 case INDEX_op_cmpsel_vec: 3391 return C_O1_I4(v, v, v, v, v); 3392 3393 default: 3394 g_assert_not_reached(); 3395 } 3396} 3397 3398/* 3399 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3400 * Some distros have fixed this up locally, others have not. 3401 */ 3402#ifndef HWCAP_S390_VXRS 3403#define HWCAP_S390_VXRS 2048 3404#endif 3405 3406static void query_s390_facilities(void) 3407{ 3408 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3409 const char *which; 3410 3411 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3412 is present on all 64-bit systems, but let's check for it anyway. */ 3413 if (hwcap & HWCAP_S390_STFLE) { 3414 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3415 register void *r1 __asm__("1") = s390_facilities; 3416 3417 /* stfle 0(%r1) */ 3418 asm volatile(".word 0xb2b0,0x1000" 3419 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3420 } 3421 3422 /* 3423 * Use of vector registers requires os support beyond the facility bit. 3424 * If the kernel does not advertise support, disable the facility bits. 3425 * There is nothing else we currently care about in the 3rd word, so 3426 * disable VECTOR with one store. 3427 */ 3428 if (!(hwcap & HWCAP_S390_VXRS)) { 3429 s390_facilities[2] = 0; 3430 } 3431 3432 /* 3433 * Minimum supported cpu revision is z196. 3434 * Check for all required facilities. 3435 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3436 */ 3437 if (!HAVE_FACILITY(LONG_DISP)) { 3438 which = "long-displacement"; 3439 goto fail; 3440 } 3441 if (!HAVE_FACILITY(EXT_IMM)) { 3442 which = "extended-immediate"; 3443 goto fail; 3444 } 3445 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3446 which = "general-instructions-extension"; 3447 goto fail; 3448 } 3449 /* 3450 * Facility 45 is a big bin that contains: distinct-operands, 3451 * fast-BCR-serialization, high-word, population-count, 3452 * interlocked-access-1, and load/store-on-condition-1 3453 */ 3454 if (!HAVE_FACILITY(45)) { 3455 which = "45"; 3456 goto fail; 3457 } 3458 return; 3459 3460 fail: 3461 error_report("%s: missing required facility %s", __func__, which); 3462 exit(EXIT_FAILURE); 3463} 3464 3465static void tcg_target_init(TCGContext *s) 3466{ 3467 query_s390_facilities(); 3468 3469 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3470 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3471 if (HAVE_FACILITY(VECTOR)) { 3472 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3473 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3474 } 3475 3476 tcg_target_call_clobber_regs = 0; 3477 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3478 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3479 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3480 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3483 /* The r6 register is technically call-saved, but it's also a parameter 3484 register, so it can get killed by setup for the qemu_st helper. */ 3485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3486 /* The return register can be considered call-clobbered. */ 3487 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3488 3489 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3490 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3491 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3493 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3494 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3496 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3497 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3498 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3499 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3500 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3501 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3502 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3503 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3504 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3505 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3506 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3507 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3508 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3509 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3510 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3511 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3512 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3513 3514 s->reserved_regs = 0; 3515 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3516 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3517 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3518 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3519 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3520} 3521 3522#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3523 + TCG_STATIC_CALL_ARGS_SIZE \ 3524 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3525 3526static void tcg_target_qemu_prologue(TCGContext *s) 3527{ 3528 /* stmg %r6,%r15,48(%r15) (save registers) */ 3529 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3530 3531 /* aghi %r15,-frame_size */ 3532 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3533 3534 tcg_set_frame(s, TCG_REG_CALL_STACK, 3535 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3536 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3537 3538 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3539 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3540 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3541 } 3542 3543 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3544 3545 /* br %r3 (go to TB) */ 3546 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3547 3548 /* 3549 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3550 * and fall through to the rest of the epilogue. 3551 */ 3552 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3553 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3554 3555 /* TB epilogue */ 3556 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3557 3558 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3559 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3560 FRAME_SIZE + 48); 3561 3562 /* br %r14 (return) */ 3563 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3564} 3565 3566static void tcg_out_tb_start(TCGContext *s) 3567{ 3568 /* nothing to do */ 3569} 3570 3571static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3572{ 3573 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3574} 3575 3576typedef struct { 3577 DebugFrameHeader h; 3578 uint8_t fde_def_cfa[4]; 3579 uint8_t fde_reg_ofs[18]; 3580} DebugFrame; 3581 3582/* We're expecting a 2 byte uleb128 encoded value. */ 3583QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3584 3585#define ELF_HOST_MACHINE EM_S390 3586 3587static const DebugFrame debug_frame = { 3588 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3589 .h.cie.id = -1, 3590 .h.cie.version = 1, 3591 .h.cie.code_align = 1, 3592 .h.cie.data_align = 8, /* sleb128 8 */ 3593 .h.cie.return_column = TCG_REG_R14, 3594 3595 /* Total FDE size does not include the "len" member. */ 3596 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3597 3598 .fde_def_cfa = { 3599 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3600 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3601 (FRAME_SIZE >> 7) 3602 }, 3603 .fde_reg_ofs = { 3604 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3605 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3606 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3607 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3608 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3609 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3610 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3611 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3612 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3613 } 3614}; 3615 3616void tcg_register_jit(const void *buf, size_t buf_size) 3617{ 3618 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3619} 3620