xref: /openbmc/qemu/tcg/riscv/tcg-target-reg-bits.h (revision d53106c997e5c8e61e37ae9ff9f0e1f243b03968)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific register size
4  * Copyright (c) 2018 SiFive, Inc
5  */
6 
7 #ifndef TCG_TARGET_REG_BITS_H
8 #define TCG_TARGET_REG_BITS_H
9 
10 /*
11  * We don't support oversize guests.
12  * Since we will only build tcg once, this in turn requires a 64-bit host.
13  */
14 #if __riscv_xlen != 64
15 #error "unsupported code generation mode"
16 #endif
17 #define TCG_TARGET_REG_BITS 64
18 
19 #endif
20