1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33#include <asm/hwcap.h> 34 35#ifdef CONFIG_DEBUG_TCG 36static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 37 "zero", 38 "ra", 39 "tp", 40 "sp", 41 "a0", 42 "a1", 43 "a2", 44 "a3", 45 "a4", 46 "a5", 47 "a6", 48 "a7", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "t8", 58 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 59 "s9", 60 "s0", 61 "s1", 62 "s2", 63 "s3", 64 "s4", 65 "s5", 66 "s6", 67 "s7", 68 "s8", 69 "vr0", 70 "vr1", 71 "vr2", 72 "vr3", 73 "vr4", 74 "vr5", 75 "vr6", 76 "vr7", 77 "vr8", 78 "vr9", 79 "vr10", 80 "vr11", 81 "vr12", 82 "vr13", 83 "vr14", 84 "vr15", 85 "vr16", 86 "vr17", 87 "vr18", 88 "vr19", 89 "vr20", 90 "vr21", 91 "vr22", 92 "vr23", 93 "vr24", 94 "vr25", 95 "vr26", 96 "vr27", 97 "vr28", 98 "vr29", 99 "vr30", 100 "vr31", 101}; 102#endif 103 104static const int tcg_target_reg_alloc_order[] = { 105 /* Registers preserved across calls */ 106 /* TCG_REG_S0 reserved for TCG_AREG0 */ 107 TCG_REG_S1, 108 TCG_REG_S2, 109 TCG_REG_S3, 110 TCG_REG_S4, 111 TCG_REG_S5, 112 TCG_REG_S6, 113 TCG_REG_S7, 114 TCG_REG_S8, 115 TCG_REG_S9, 116 117 /* Registers (potentially) clobbered across calls */ 118 TCG_REG_T0, 119 TCG_REG_T1, 120 TCG_REG_T2, 121 TCG_REG_T3, 122 TCG_REG_T4, 123 TCG_REG_T5, 124 TCG_REG_T6, 125 TCG_REG_T7, 126 TCG_REG_T8, 127 128 /* Argument registers, opposite order of allocation. */ 129 TCG_REG_A7, 130 TCG_REG_A6, 131 TCG_REG_A5, 132 TCG_REG_A4, 133 TCG_REG_A3, 134 TCG_REG_A2, 135 TCG_REG_A1, 136 TCG_REG_A0, 137 138 /* Vector registers */ 139 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 140 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 141 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 142 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 143 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 144 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 145 /* V24 - V31 are caller-saved, and skipped. */ 146}; 147 148static const int tcg_target_call_iarg_regs[] = { 149 TCG_REG_A0, 150 TCG_REG_A1, 151 TCG_REG_A2, 152 TCG_REG_A3, 153 TCG_REG_A4, 154 TCG_REG_A5, 155 TCG_REG_A6, 156 TCG_REG_A7, 157}; 158 159static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 160{ 161 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 162 tcg_debug_assert(slot >= 0 && slot <= 1); 163 return TCG_REG_A0 + slot; 164} 165 166#define TCG_GUEST_BASE_REG TCG_REG_S1 167 168#define TCG_CT_CONST_ZERO 0x100 169#define TCG_CT_CONST_S12 0x200 170#define TCG_CT_CONST_S32 0x400 171#define TCG_CT_CONST_U12 0x800 172#define TCG_CT_CONST_C12 0x1000 173#define TCG_CT_CONST_WSZ 0x2000 174#define TCG_CT_CONST_VCMP 0x4000 175#define TCG_CT_CONST_VADD 0x8000 176 177#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 178#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 179 180static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 181{ 182 return sextract64(val, pos, len); 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, int ct, 187 TCGType type, TCGCond cond, int vece) 188{ 189 if (ct & TCG_CT_CONST) { 190 return true; 191 } 192 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 193 return true; 194 } 195 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 int64_t vec_val = sextract64(val, 0, 8 << vece); 211 if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) { 212 return true; 213 } 214 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 215 return true; 216 } 217 return false; 218} 219 220/* 221 * Relocations 222 */ 223 224/* 225 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 226 * complicated; a whopping stack machine is needed to stuff the fields, at 227 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 228 * needed. 229 * 230 * Hence, define our own simpler relocation types. Numbers are chosen as to 231 * not collide with potential future additions to the true ELF relocation 232 * type enum. 233 */ 234 235/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 236#define R_LOONGARCH_BR_SK16 256 237/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 238#define R_LOONGARCH_BR_SD10K16 257 239 240static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 241{ 242 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 243 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 244 245 tcg_debug_assert((offset & 3) == 0); 246 offset >>= 2; 247 if (offset == sextreg(offset, 0, 16)) { 248 *src_rw = deposit64(*src_rw, 10, 16, offset); 249 return true; 250 } 251 252 return false; 253} 254 255static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 256 const tcg_insn_unit *target) 257{ 258 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 259 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 260 261 tcg_debug_assert((offset & 3) == 0); 262 offset >>= 2; 263 if (offset == sextreg(offset, 0, 26)) { 264 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 265 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 266 return true; 267 } 268 269 return false; 270} 271 272static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 273 intptr_t value, intptr_t addend) 274{ 275 tcg_debug_assert(addend == 0); 276 switch (type) { 277 case R_LOONGARCH_BR_SK16: 278 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 279 case R_LOONGARCH_BR_SD10K16: 280 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 281 default: 282 g_assert_not_reached(); 283 } 284} 285 286#include "tcg-insn-defs.c.inc" 287 288/* 289 * TCG intrinsics 290 */ 291 292static void tcg_out_mb(TCGContext *s, TCGArg a0) 293{ 294 /* Baseline LoongArch only has the full barrier, unfortunately. */ 295 tcg_out_opc_dbar(s, 0); 296} 297 298static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 299{ 300 if (ret == arg) { 301 return true; 302 } 303 switch (type) { 304 case TCG_TYPE_I32: 305 case TCG_TYPE_I64: 306 /* 307 * Conventional register-register move used in LoongArch is 308 * `or dst, src, zero`. 309 */ 310 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 311 break; 312 case TCG_TYPE_V128: 313 tcg_out_opc_vori_b(s, ret, arg, 0); 314 break; 315 default: 316 g_assert_not_reached(); 317 } 318 return true; 319} 320 321/* Loads a 32-bit immediate into rd, sign-extended. */ 322static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 323{ 324 tcg_target_long lo = sextreg(val, 0, 12); 325 tcg_target_long hi12 = sextreg(val, 12, 20); 326 327 /* Single-instruction cases. */ 328 if (hi12 == 0) { 329 /* val fits in uimm12: ori rd, zero, val */ 330 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 331 return; 332 } 333 if (hi12 == sextreg(lo, 12, 20)) { 334 /* val fits in simm12: addi.w rd, zero, val */ 335 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 336 return; 337 } 338 339 /* High bits must be set; load with lu12i.w + optional ori. */ 340 tcg_out_opc_lu12i_w(s, rd, hi12); 341 if (lo != 0) { 342 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 343 } 344} 345 346static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 347 tcg_target_long val) 348{ 349 /* 350 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 351 * with dedicated instructions for filling the respective bitfields 352 * below: 353 * 354 * 6 5 4 3 355 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 356 * +-----------------------+---------------------------------------+... 357 * | hi52 | hi32 | 358 * +-----------------------+---------------------------------------+... 359 * 3 2 1 360 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 361 * ...+-------------------------------------+-------------------------+ 362 * | hi12 | lo | 363 * ...+-------------------------------------+-------------------------+ 364 * 365 * Check if val belong to one of the several fast cases, before falling 366 * back to the slow path. 367 */ 368 369 intptr_t pc_offset; 370 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 371 tcg_target_long hi12, hi32, hi52; 372 373 /* Value fits in signed i32. */ 374 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 375 tcg_out_movi_i32(s, rd, val); 376 return; 377 } 378 379 /* PC-relative cases. */ 380 pc_offset = tcg_pcrel_diff(s, (void *)val); 381 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 382 /* Single pcaddu2i. */ 383 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 384 return; 385 } 386 387 if (pc_offset == (int32_t)pc_offset) { 388 /* Offset within 32 bits; load with pcalau12i + ori. */ 389 val_lo = sextreg(val, 0, 12); 390 val_hi = val >> 12; 391 pc_hi = (val - pc_offset) >> 12; 392 offset_hi = val_hi - pc_hi; 393 394 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 395 tcg_out_opc_pcalau12i(s, rd, offset_hi); 396 if (val_lo != 0) { 397 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 398 } 399 return; 400 } 401 402 hi12 = sextreg(val, 12, 20); 403 hi32 = sextreg(val, 32, 20); 404 hi52 = sextreg(val, 52, 12); 405 406 /* Single cu52i.d case. */ 407 if ((hi52 != 0) && (ctz64(val) >= 52)) { 408 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 409 return; 410 } 411 412 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 413 tcg_out_movi_i32(s, rd, val); 414 415 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 416 if (hi32 != sextreg(hi12, 20, 20)) { 417 tcg_out_opc_cu32i_d(s, rd, hi32); 418 } 419 420 if (hi52 != sextreg(hi32, 20, 12)) { 421 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 422 } 423} 424 425static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 426 TCGReg rs, tcg_target_long imm) 427{ 428 tcg_target_long lo12 = sextreg(imm, 0, 12); 429 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 430 431 /* 432 * Note that there's a hole in between hi16 and lo12: 433 * 434 * 3 2 1 0 435 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 436 * ...+-------------------------------+-------+-----------------------+ 437 * | hi16 | | lo12 | 438 * ...+-------------------------------+-------+-----------------------+ 439 * 440 * For bits within that hole, it's more efficient to use LU12I and ADD. 441 */ 442 if (imm == (hi16 << 16) + lo12) { 443 if (hi16) { 444 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 445 rs = rd; 446 } 447 if (type == TCG_TYPE_I32) { 448 tcg_out_opc_addi_w(s, rd, rs, lo12); 449 } else if (lo12) { 450 tcg_out_opc_addi_d(s, rd, rs, lo12); 451 } else { 452 tcg_out_mov(s, type, rd, rs); 453 } 454 } else { 455 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 456 if (type == TCG_TYPE_I32) { 457 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 458 } else { 459 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 460 } 461 } 462} 463 464static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 465{ 466 return false; 467} 468 469static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 470 tcg_target_long imm) 471{ 472 /* This function is only used for passing structs by reference. */ 473 g_assert_not_reached(); 474} 475 476static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 477{ 478 tcg_out_opc_andi(s, ret, arg, 0xff); 479} 480 481static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 482{ 483 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 484} 485 486static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 487{ 488 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 489} 490 491static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 492{ 493 tcg_out_opc_sext_b(s, ret, arg); 494} 495 496static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 497{ 498 tcg_out_opc_sext_h(s, ret, arg); 499} 500 501static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 502{ 503 tcg_out_opc_addi_w(s, ret, arg, 0); 504} 505 506static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 507{ 508 if (ret != arg) { 509 tcg_out_ext32s(s, ret, arg); 510 } 511} 512 513static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 514{ 515 tcg_out_ext32u(s, ret, arg); 516} 517 518static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 519{ 520 tcg_out_ext32s(s, ret, arg); 521} 522 523static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 524 TCGReg a0, TCGReg a1, TCGReg a2, 525 bool c2, bool is_32bit) 526{ 527 if (c2) { 528 /* 529 * Fast path: semantics already satisfied due to constraint and 530 * insn behavior, single instruction is enough. 531 */ 532 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 533 /* all clz/ctz insns belong to DJ-format */ 534 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 535 return; 536 } 537 538 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 539 /* a0 = a1 ? REG_TMP0 : a2 */ 540 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 541 tcg_out_opc_masknez(s, a0, a2, a1); 542 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 543} 544 545#define SETCOND_INV TCG_TARGET_NB_REGS 546#define SETCOND_NEZ (SETCOND_INV << 1) 547#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 548 549static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 550 TCGReg arg1, tcg_target_long arg2, bool c2) 551{ 552 int flags = 0; 553 554 switch (cond) { 555 case TCG_COND_EQ: /* -> NE */ 556 case TCG_COND_GE: /* -> LT */ 557 case TCG_COND_GEU: /* -> LTU */ 558 case TCG_COND_GT: /* -> LE */ 559 case TCG_COND_GTU: /* -> LEU */ 560 cond = tcg_invert_cond(cond); 561 flags ^= SETCOND_INV; 562 break; 563 default: 564 break; 565 } 566 567 switch (cond) { 568 case TCG_COND_LE: 569 case TCG_COND_LEU: 570 /* 571 * If we have a constant input, the most efficient way to implement 572 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 573 * We don't need to care for this for LE because the constant input 574 * is still constrained to int32_t, and INT32_MAX+1 is representable 575 * in the 64-bit temporary register. 576 */ 577 if (c2) { 578 if (cond == TCG_COND_LEU) { 579 /* unsigned <= -1 is true */ 580 if (arg2 == -1) { 581 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 582 return ret; 583 } 584 cond = TCG_COND_LTU; 585 } else { 586 cond = TCG_COND_LT; 587 } 588 arg2 += 1; 589 } else { 590 TCGReg tmp = arg2; 591 arg2 = arg1; 592 arg1 = tmp; 593 cond = tcg_swap_cond(cond); /* LE -> GE */ 594 cond = tcg_invert_cond(cond); /* GE -> LT */ 595 flags ^= SETCOND_INV; 596 } 597 break; 598 default: 599 break; 600 } 601 602 switch (cond) { 603 case TCG_COND_NE: 604 flags |= SETCOND_NEZ; 605 if (!c2) { 606 tcg_out_opc_xor(s, ret, arg1, arg2); 607 } else if (arg2 == 0) { 608 ret = arg1; 609 } else if (arg2 >= 0 && arg2 <= 0xfff) { 610 tcg_out_opc_xori(s, ret, arg1, arg2); 611 } else { 612 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 613 } 614 break; 615 616 case TCG_COND_LT: 617 case TCG_COND_LTU: 618 if (c2) { 619 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 620 if (cond == TCG_COND_LT) { 621 tcg_out_opc_slti(s, ret, arg1, arg2); 622 } else { 623 tcg_out_opc_sltui(s, ret, arg1, arg2); 624 } 625 break; 626 } 627 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 628 arg2 = TCG_REG_TMP0; 629 } 630 if (cond == TCG_COND_LT) { 631 tcg_out_opc_slt(s, ret, arg1, arg2); 632 } else { 633 tcg_out_opc_sltu(s, ret, arg1, arg2); 634 } 635 break; 636 637 default: 638 g_assert_not_reached(); 639 break; 640 } 641 642 return ret | flags; 643} 644 645static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 646 TCGReg arg1, tcg_target_long arg2, bool c2) 647{ 648 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 649 650 if (tmpflags != ret) { 651 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 652 653 switch (tmpflags & SETCOND_FLAGS) { 654 case SETCOND_INV: 655 /* Intermediate result is boolean: simply invert. */ 656 tcg_out_opc_xori(s, ret, tmp, 1); 657 break; 658 case SETCOND_NEZ: 659 /* Intermediate result is zero/non-zero: test != 0. */ 660 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 661 break; 662 case SETCOND_NEZ | SETCOND_INV: 663 /* Intermediate result is zero/non-zero: test == 0. */ 664 tcg_out_opc_sltui(s, ret, tmp, 1); 665 break; 666 default: 667 g_assert_not_reached(); 668 } 669 } 670} 671 672static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 673 TCGReg c1, tcg_target_long c2, bool const2, 674 TCGReg v1, TCGReg v2) 675{ 676 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 677 TCGReg t; 678 679 /* Standardize the test below to t != 0. */ 680 if (tmpflags & SETCOND_INV) { 681 t = v1, v1 = v2, v2 = t; 682 } 683 684 t = tmpflags & ~SETCOND_FLAGS; 685 if (v1 == TCG_REG_ZERO) { 686 tcg_out_opc_masknez(s, ret, v2, t); 687 } else if (v2 == TCG_REG_ZERO) { 688 tcg_out_opc_maskeqz(s, ret, v1, t); 689 } else { 690 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 691 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 692 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 693 } 694} 695 696/* 697 * Branch helpers 698 */ 699 700static const struct { 701 LoongArchInsn op; 702 bool swap; 703} tcg_brcond_to_loongarch[] = { 704 [TCG_COND_EQ] = { OPC_BEQ, false }, 705 [TCG_COND_NE] = { OPC_BNE, false }, 706 [TCG_COND_LT] = { OPC_BGT, true }, 707 [TCG_COND_GE] = { OPC_BLE, true }, 708 [TCG_COND_LE] = { OPC_BLE, false }, 709 [TCG_COND_GT] = { OPC_BGT, false }, 710 [TCG_COND_LTU] = { OPC_BGTU, true }, 711 [TCG_COND_GEU] = { OPC_BLEU, true }, 712 [TCG_COND_LEU] = { OPC_BLEU, false }, 713 [TCG_COND_GTU] = { OPC_BGTU, false } 714}; 715 716static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 717 TCGReg arg2, TCGLabel *l) 718{ 719 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 720 721 tcg_debug_assert(op != 0); 722 723 if (tcg_brcond_to_loongarch[cond].swap) { 724 TCGReg t = arg1; 725 arg1 = arg2; 726 arg2 = t; 727 } 728 729 /* all conditional branch insns belong to DJSk16-format */ 730 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 731 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 732} 733 734static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 735{ 736 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 737 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 738 739 tcg_debug_assert((offset & 3) == 0); 740 if (offset == sextreg(offset, 0, 28)) { 741 /* short jump: +/- 256MiB */ 742 if (tail) { 743 tcg_out_opc_b(s, offset >> 2); 744 } else { 745 tcg_out_opc_bl(s, offset >> 2); 746 } 747 } else if (offset == sextreg(offset, 0, 38)) { 748 /* long jump: +/- 256GiB */ 749 tcg_target_long lo = sextreg(offset, 0, 18); 750 tcg_target_long hi = offset - lo; 751 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 752 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 753 } else { 754 /* far jump: 64-bit */ 755 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 756 tcg_target_long hi = (tcg_target_long)arg - lo; 757 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 758 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 759 } 760} 761 762static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 763 const TCGHelperInfo *info) 764{ 765 tcg_out_call_int(s, arg, false); 766} 767 768/* 769 * Load/store helpers 770 */ 771 772static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 773 TCGReg addr, intptr_t offset) 774{ 775 intptr_t imm12 = sextreg(offset, 0, 12); 776 777 if (offset != imm12) { 778 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 779 780 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 781 imm12 = sextreg(diff, 0, 12); 782 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 783 } else { 784 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 785 if (addr != TCG_REG_ZERO) { 786 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 787 } 788 } 789 addr = TCG_REG_TMP2; 790 } 791 792 switch (opc) { 793 case OPC_LD_B: 794 case OPC_LD_BU: 795 case OPC_LD_H: 796 case OPC_LD_HU: 797 case OPC_LD_W: 798 case OPC_LD_WU: 799 case OPC_LD_D: 800 case OPC_ST_B: 801 case OPC_ST_H: 802 case OPC_ST_W: 803 case OPC_ST_D: 804 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 805 break; 806 case OPC_FLD_S: 807 case OPC_FLD_D: 808 case OPC_FST_S: 809 case OPC_FST_D: 810 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 811 break; 812 default: 813 g_assert_not_reached(); 814 } 815} 816 817static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 818 TCGReg base, intptr_t offset) 819{ 820 switch (type) { 821 case TCG_TYPE_I32: 822 if (dest < TCG_REG_V0) { 823 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 824 } else { 825 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 826 } 827 break; 828 case TCG_TYPE_I64: 829 if (dest < TCG_REG_V0) { 830 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 831 } else { 832 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 833 } 834 break; 835 case TCG_TYPE_V128: 836 if (-0x800 <= offset && offset <= 0x7ff) { 837 tcg_out_opc_vld(s, dest, base, offset); 838 } else { 839 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 840 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 841 } 842 break; 843 default: 844 g_assert_not_reached(); 845 } 846} 847 848static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 849 TCGReg base, intptr_t offset) 850{ 851 switch (type) { 852 case TCG_TYPE_I32: 853 if (src < TCG_REG_V0) { 854 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 855 } else { 856 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 857 } 858 break; 859 case TCG_TYPE_I64: 860 if (src < TCG_REG_V0) { 861 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 862 } else { 863 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 864 } 865 break; 866 case TCG_TYPE_V128: 867 if (-0x800 <= offset && offset <= 0x7ff) { 868 tcg_out_opc_vst(s, src, base, offset); 869 } else { 870 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 871 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 872 } 873 break; 874 default: 875 g_assert_not_reached(); 876 } 877} 878 879static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 880 TCGReg base, intptr_t ofs) 881{ 882 if (val == 0) { 883 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 884 return true; 885 } 886 return false; 887} 888 889/* 890 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 891 */ 892 893static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 894{ 895 tcg_out_opc_b(s, 0); 896 return reloc_br_sd10k16(s->code_ptr - 1, target); 897} 898 899static const TCGLdstHelperParam ldst_helper_param = { 900 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 901}; 902 903static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 904{ 905 MemOp opc = get_memop(l->oi); 906 907 /* resolve label address */ 908 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 909 return false; 910 } 911 912 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 913 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 914 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 915 return tcg_out_goto(s, l->raddr); 916} 917 918static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 919{ 920 MemOp opc = get_memop(l->oi); 921 922 /* resolve label address */ 923 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 924 return false; 925 } 926 927 tcg_out_st_helper_args(s, l, &ldst_helper_param); 928 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 929 return tcg_out_goto(s, l->raddr); 930} 931 932typedef struct { 933 TCGReg base; 934 TCGReg index; 935 TCGAtomAlign aa; 936} HostAddress; 937 938bool tcg_target_has_memory_bswap(MemOp memop) 939{ 940 return false; 941} 942 943/* We expect to use a 12-bit negative offset from ENV. */ 944#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 945 946/* 947 * For system-mode, perform the TLB load and compare. 948 * For user-mode, perform any required alignment tests. 949 * In both cases, return a TCGLabelQemuLdst structure if the slow path 950 * is required and fill in @h with the host address for the fast path. 951 */ 952static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 953 TCGReg addr_reg, MemOpIdx oi, 954 bool is_ld) 955{ 956 TCGType addr_type = s->addr_type; 957 TCGLabelQemuLdst *ldst = NULL; 958 MemOp opc = get_memop(oi); 959 MemOp a_bits; 960 961 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 962 a_bits = h->aa.align; 963 964 if (tcg_use_softmmu) { 965 unsigned s_bits = opc & MO_SIZE; 966 int mem_index = get_mmuidx(oi); 967 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 968 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 969 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 970 971 ldst = new_ldst_label(s); 972 ldst->is_ld = is_ld; 973 ldst->oi = oi; 974 ldst->addrlo_reg = addr_reg; 975 976 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 977 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 978 979 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 980 s->page_bits - CPU_TLB_ENTRY_BITS); 981 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 982 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 983 984 /* Load the tlb comparator and the addend. */ 985 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 986 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 987 is_ld ? offsetof(CPUTLBEntry, addr_read) 988 : offsetof(CPUTLBEntry, addr_write)); 989 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 990 offsetof(CPUTLBEntry, addend)); 991 992 /* 993 * For aligned accesses, we check the first byte and include the 994 * alignment bits within the address. For unaligned access, we 995 * check that we don't cross pages using the address of the last 996 * byte of the access. 997 */ 998 if (a_bits < s_bits) { 999 unsigned a_mask = (1u << a_bits) - 1; 1000 unsigned s_mask = (1u << s_bits) - 1; 1001 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1002 } else { 1003 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1004 } 1005 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1006 a_bits, s->page_bits - 1); 1007 1008 /* Compare masked address with the TLB entry. */ 1009 ldst->label_ptr[0] = s->code_ptr; 1010 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1011 1012 h->index = TCG_REG_TMP2; 1013 } else { 1014 if (a_bits) { 1015 ldst = new_ldst_label(s); 1016 1017 ldst->is_ld = is_ld; 1018 ldst->oi = oi; 1019 ldst->addrlo_reg = addr_reg; 1020 1021 /* 1022 * Without micro-architecture details, we don't know which of 1023 * bstrpick or andi is faster, so use bstrpick as it's not 1024 * constrained by imm field width. Not to say alignments >= 2^12 1025 * are going to happen any time soon. 1026 */ 1027 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1028 1029 ldst->label_ptr[0] = s->code_ptr; 1030 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1031 } 1032 1033 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1034 } 1035 1036 if (addr_type == TCG_TYPE_I32) { 1037 h->base = TCG_REG_TMP0; 1038 tcg_out_ext32u(s, h->base, addr_reg); 1039 } else { 1040 h->base = addr_reg; 1041 } 1042 1043 return ldst; 1044} 1045 1046static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1047 TCGReg rd, HostAddress h) 1048{ 1049 /* Byte swapping is left to middle-end expansion. */ 1050 tcg_debug_assert((opc & MO_BSWAP) == 0); 1051 1052 switch (opc & MO_SSIZE) { 1053 case MO_UB: 1054 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1055 break; 1056 case MO_SB: 1057 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1058 break; 1059 case MO_UW: 1060 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1061 break; 1062 case MO_SW: 1063 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1064 break; 1065 case MO_UL: 1066 if (type == TCG_TYPE_I64) { 1067 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1068 break; 1069 } 1070 /* fallthrough */ 1071 case MO_SL: 1072 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1073 break; 1074 case MO_UQ: 1075 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1076 break; 1077 default: 1078 g_assert_not_reached(); 1079 } 1080} 1081 1082static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1083 MemOpIdx oi, TCGType data_type) 1084{ 1085 TCGLabelQemuLdst *ldst; 1086 HostAddress h; 1087 1088 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1089 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1090 1091 if (ldst) { 1092 ldst->type = data_type; 1093 ldst->datalo_reg = data_reg; 1094 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1095 } 1096} 1097 1098static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1099 TCGReg rd, HostAddress h) 1100{ 1101 /* Byte swapping is left to middle-end expansion. */ 1102 tcg_debug_assert((opc & MO_BSWAP) == 0); 1103 1104 switch (opc & MO_SIZE) { 1105 case MO_8: 1106 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1107 break; 1108 case MO_16: 1109 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1110 break; 1111 case MO_32: 1112 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1113 break; 1114 case MO_64: 1115 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1116 break; 1117 default: 1118 g_assert_not_reached(); 1119 } 1120} 1121 1122static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1123 MemOpIdx oi, TCGType data_type) 1124{ 1125 TCGLabelQemuLdst *ldst; 1126 HostAddress h; 1127 1128 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1129 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1130 1131 if (ldst) { 1132 ldst->type = data_type; 1133 ldst->datalo_reg = data_reg; 1134 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1135 } 1136} 1137 1138static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1139 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1140{ 1141 TCGLabelQemuLdst *ldst; 1142 HostAddress h; 1143 1144 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1145 1146 if (h.aa.atom == MO_128) { 1147 /* 1148 * Use VLDX/VSTX when 128-bit atomicity is required. 1149 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1150 */ 1151 if (is_ld) { 1152 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1153 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1154 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1155 } else { 1156 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1157 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1158 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1159 } 1160 } else { 1161 /* Otherwise use a pair of LD/ST. */ 1162 TCGReg base = h.base; 1163 if (h.index != TCG_REG_ZERO) { 1164 base = TCG_REG_TMP0; 1165 tcg_out_opc_add_d(s, base, h.base, h.index); 1166 } 1167 if (is_ld) { 1168 tcg_debug_assert(base != data_lo); 1169 tcg_out_opc_ld_d(s, data_lo, base, 0); 1170 tcg_out_opc_ld_d(s, data_hi, base, 8); 1171 } else { 1172 tcg_out_opc_st_d(s, data_lo, base, 0); 1173 tcg_out_opc_st_d(s, data_hi, base, 8); 1174 } 1175 } 1176 1177 if (ldst) { 1178 ldst->type = TCG_TYPE_I128; 1179 ldst->datalo_reg = data_lo; 1180 ldst->datahi_reg = data_hi; 1181 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1182 } 1183} 1184 1185/* 1186 * Entry-points 1187 */ 1188 1189static const tcg_insn_unit *tb_ret_addr; 1190 1191static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1192{ 1193 /* Reuse the zeroing that exists for goto_ptr. */ 1194 if (a0 == 0) { 1195 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1196 } else { 1197 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1198 tcg_out_call_int(s, tb_ret_addr, true); 1199 } 1200} 1201 1202static void tcg_out_goto_tb(TCGContext *s, int which) 1203{ 1204 /* 1205 * Direct branch, or load indirect address, to be patched 1206 * by tb_target_set_jmp_target. Check indirect load offset 1207 * in range early, regardless of direct branch distance, 1208 * via assert within tcg_out_opc_pcaddu2i. 1209 */ 1210 uintptr_t i_addr = get_jmp_target_addr(s, which); 1211 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1212 1213 set_jmp_insn_offset(s, which); 1214 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1215 1216 /* Finish the load and indirect branch. */ 1217 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1218 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1219 set_jmp_reset_offset(s, which); 1220} 1221 1222void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1223 uintptr_t jmp_rx, uintptr_t jmp_rw) 1224{ 1225 uintptr_t d_addr = tb->jmp_target_addr[n]; 1226 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1227 tcg_insn_unit insn; 1228 1229 /* Either directly branch, or load slot address for indirect branch. */ 1230 if (d_disp == sextreg(d_disp, 0, 26)) { 1231 insn = encode_sd10k16_insn(OPC_B, d_disp); 1232 } else { 1233 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1234 intptr_t i_disp = i_addr - jmp_rx; 1235 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1236 } 1237 1238 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1239 flush_idcache_range(jmp_rx, jmp_rw, 4); 1240} 1241 1242static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1243 const TCGArg args[TCG_MAX_OP_ARGS], 1244 const int const_args[TCG_MAX_OP_ARGS]) 1245{ 1246 TCGArg a0 = args[0]; 1247 TCGArg a1 = args[1]; 1248 TCGArg a2 = args[2]; 1249 TCGArg a3 = args[3]; 1250 int c2 = const_args[2]; 1251 1252 switch (opc) { 1253 case INDEX_op_mb: 1254 tcg_out_mb(s, a0); 1255 break; 1256 1257 case INDEX_op_goto_ptr: 1258 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1259 break; 1260 1261 case INDEX_op_br: 1262 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1263 0); 1264 tcg_out_opc_b(s, 0); 1265 break; 1266 1267 case INDEX_op_brcond_i32: 1268 case INDEX_op_brcond_i64: 1269 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1270 break; 1271 1272 case INDEX_op_extrh_i64_i32: 1273 tcg_out_opc_srai_d(s, a0, a1, 32); 1274 break; 1275 1276 case INDEX_op_not_i32: 1277 case INDEX_op_not_i64: 1278 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1279 break; 1280 1281 case INDEX_op_nor_i32: 1282 case INDEX_op_nor_i64: 1283 if (c2) { 1284 tcg_out_opc_ori(s, a0, a1, a2); 1285 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1286 } else { 1287 tcg_out_opc_nor(s, a0, a1, a2); 1288 } 1289 break; 1290 1291 case INDEX_op_andc_i32: 1292 case INDEX_op_andc_i64: 1293 if (c2) { 1294 /* guaranteed to fit due to constraint */ 1295 tcg_out_opc_andi(s, a0, a1, ~a2); 1296 } else { 1297 tcg_out_opc_andn(s, a0, a1, a2); 1298 } 1299 break; 1300 1301 case INDEX_op_orc_i32: 1302 case INDEX_op_orc_i64: 1303 if (c2) { 1304 /* guaranteed to fit due to constraint */ 1305 tcg_out_opc_ori(s, a0, a1, ~a2); 1306 } else { 1307 tcg_out_opc_orn(s, a0, a1, a2); 1308 } 1309 break; 1310 1311 case INDEX_op_and_i32: 1312 case INDEX_op_and_i64: 1313 if (c2) { 1314 tcg_out_opc_andi(s, a0, a1, a2); 1315 } else { 1316 tcg_out_opc_and(s, a0, a1, a2); 1317 } 1318 break; 1319 1320 case INDEX_op_or_i32: 1321 case INDEX_op_or_i64: 1322 if (c2) { 1323 tcg_out_opc_ori(s, a0, a1, a2); 1324 } else { 1325 tcg_out_opc_or(s, a0, a1, a2); 1326 } 1327 break; 1328 1329 case INDEX_op_xor_i32: 1330 case INDEX_op_xor_i64: 1331 if (c2) { 1332 tcg_out_opc_xori(s, a0, a1, a2); 1333 } else { 1334 tcg_out_opc_xor(s, a0, a1, a2); 1335 } 1336 break; 1337 1338 case INDEX_op_extract_i32: 1339 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1340 break; 1341 case INDEX_op_extract_i64: 1342 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1343 break; 1344 1345 case INDEX_op_deposit_i32: 1346 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1347 break; 1348 case INDEX_op_deposit_i64: 1349 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1350 break; 1351 1352 case INDEX_op_bswap16_i32: 1353 case INDEX_op_bswap16_i64: 1354 tcg_out_opc_revb_2h(s, a0, a1); 1355 if (a2 & TCG_BSWAP_OS) { 1356 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1357 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1358 tcg_out_ext16u(s, a0, a0); 1359 } 1360 break; 1361 1362 case INDEX_op_bswap32_i32: 1363 /* All 32-bit values are computed sign-extended in the register. */ 1364 a2 = TCG_BSWAP_OS; 1365 /* fallthrough */ 1366 case INDEX_op_bswap32_i64: 1367 tcg_out_opc_revb_2w(s, a0, a1); 1368 if (a2 & TCG_BSWAP_OS) { 1369 tcg_out_ext32s(s, a0, a0); 1370 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1371 tcg_out_ext32u(s, a0, a0); 1372 } 1373 break; 1374 1375 case INDEX_op_bswap64_i64: 1376 tcg_out_opc_revb_d(s, a0, a1); 1377 break; 1378 1379 case INDEX_op_clz_i32: 1380 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1381 break; 1382 case INDEX_op_clz_i64: 1383 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1384 break; 1385 1386 case INDEX_op_ctz_i32: 1387 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1388 break; 1389 case INDEX_op_ctz_i64: 1390 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1391 break; 1392 1393 case INDEX_op_shl_i32: 1394 if (c2) { 1395 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1396 } else { 1397 tcg_out_opc_sll_w(s, a0, a1, a2); 1398 } 1399 break; 1400 case INDEX_op_shl_i64: 1401 if (c2) { 1402 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1403 } else { 1404 tcg_out_opc_sll_d(s, a0, a1, a2); 1405 } 1406 break; 1407 1408 case INDEX_op_shr_i32: 1409 if (c2) { 1410 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1411 } else { 1412 tcg_out_opc_srl_w(s, a0, a1, a2); 1413 } 1414 break; 1415 case INDEX_op_shr_i64: 1416 if (c2) { 1417 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1418 } else { 1419 tcg_out_opc_srl_d(s, a0, a1, a2); 1420 } 1421 break; 1422 1423 case INDEX_op_sar_i32: 1424 if (c2) { 1425 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1426 } else { 1427 tcg_out_opc_sra_w(s, a0, a1, a2); 1428 } 1429 break; 1430 case INDEX_op_sar_i64: 1431 if (c2) { 1432 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1433 } else { 1434 tcg_out_opc_sra_d(s, a0, a1, a2); 1435 } 1436 break; 1437 1438 case INDEX_op_rotl_i32: 1439 /* transform into equivalent rotr/rotri */ 1440 if (c2) { 1441 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1442 } else { 1443 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1444 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1445 } 1446 break; 1447 case INDEX_op_rotl_i64: 1448 /* transform into equivalent rotr/rotri */ 1449 if (c2) { 1450 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1451 } else { 1452 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1453 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1454 } 1455 break; 1456 1457 case INDEX_op_rotr_i32: 1458 if (c2) { 1459 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1460 } else { 1461 tcg_out_opc_rotr_w(s, a0, a1, a2); 1462 } 1463 break; 1464 case INDEX_op_rotr_i64: 1465 if (c2) { 1466 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1467 } else { 1468 tcg_out_opc_rotr_d(s, a0, a1, a2); 1469 } 1470 break; 1471 1472 case INDEX_op_add_i32: 1473 if (c2) { 1474 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); 1475 } else { 1476 tcg_out_opc_add_w(s, a0, a1, a2); 1477 } 1478 break; 1479 case INDEX_op_add_i64: 1480 if (c2) { 1481 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); 1482 } else { 1483 tcg_out_opc_add_d(s, a0, a1, a2); 1484 } 1485 break; 1486 1487 case INDEX_op_sub_i32: 1488 if (c2) { 1489 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); 1490 } else { 1491 tcg_out_opc_sub_w(s, a0, a1, a2); 1492 } 1493 break; 1494 case INDEX_op_sub_i64: 1495 if (c2) { 1496 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); 1497 } else { 1498 tcg_out_opc_sub_d(s, a0, a1, a2); 1499 } 1500 break; 1501 1502 case INDEX_op_neg_i32: 1503 tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); 1504 break; 1505 case INDEX_op_neg_i64: 1506 tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); 1507 break; 1508 1509 case INDEX_op_mul_i32: 1510 tcg_out_opc_mul_w(s, a0, a1, a2); 1511 break; 1512 case INDEX_op_mul_i64: 1513 tcg_out_opc_mul_d(s, a0, a1, a2); 1514 break; 1515 1516 case INDEX_op_mulsh_i32: 1517 tcg_out_opc_mulh_w(s, a0, a1, a2); 1518 break; 1519 case INDEX_op_mulsh_i64: 1520 tcg_out_opc_mulh_d(s, a0, a1, a2); 1521 break; 1522 1523 case INDEX_op_muluh_i32: 1524 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1525 break; 1526 case INDEX_op_muluh_i64: 1527 tcg_out_opc_mulh_du(s, a0, a1, a2); 1528 break; 1529 1530 case INDEX_op_div_i32: 1531 tcg_out_opc_div_w(s, a0, a1, a2); 1532 break; 1533 case INDEX_op_div_i64: 1534 tcg_out_opc_div_d(s, a0, a1, a2); 1535 break; 1536 1537 case INDEX_op_divu_i32: 1538 tcg_out_opc_div_wu(s, a0, a1, a2); 1539 break; 1540 case INDEX_op_divu_i64: 1541 tcg_out_opc_div_du(s, a0, a1, a2); 1542 break; 1543 1544 case INDEX_op_rem_i32: 1545 tcg_out_opc_mod_w(s, a0, a1, a2); 1546 break; 1547 case INDEX_op_rem_i64: 1548 tcg_out_opc_mod_d(s, a0, a1, a2); 1549 break; 1550 1551 case INDEX_op_remu_i32: 1552 tcg_out_opc_mod_wu(s, a0, a1, a2); 1553 break; 1554 case INDEX_op_remu_i64: 1555 tcg_out_opc_mod_du(s, a0, a1, a2); 1556 break; 1557 1558 case INDEX_op_setcond_i32: 1559 case INDEX_op_setcond_i64: 1560 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1561 break; 1562 1563 case INDEX_op_movcond_i32: 1564 case INDEX_op_movcond_i64: 1565 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1566 break; 1567 1568 case INDEX_op_ld8s_i32: 1569 case INDEX_op_ld8s_i64: 1570 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1571 break; 1572 case INDEX_op_ld8u_i32: 1573 case INDEX_op_ld8u_i64: 1574 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1575 break; 1576 case INDEX_op_ld16s_i32: 1577 case INDEX_op_ld16s_i64: 1578 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1579 break; 1580 case INDEX_op_ld16u_i32: 1581 case INDEX_op_ld16u_i64: 1582 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1583 break; 1584 case INDEX_op_ld_i32: 1585 case INDEX_op_ld32s_i64: 1586 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1587 break; 1588 case INDEX_op_ld32u_i64: 1589 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1590 break; 1591 case INDEX_op_ld_i64: 1592 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1593 break; 1594 1595 case INDEX_op_st8_i32: 1596 case INDEX_op_st8_i64: 1597 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1598 break; 1599 case INDEX_op_st16_i32: 1600 case INDEX_op_st16_i64: 1601 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1602 break; 1603 case INDEX_op_st_i32: 1604 case INDEX_op_st32_i64: 1605 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1606 break; 1607 case INDEX_op_st_i64: 1608 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1609 break; 1610 1611 case INDEX_op_qemu_ld_a32_i32: 1612 case INDEX_op_qemu_ld_a64_i32: 1613 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1614 break; 1615 case INDEX_op_qemu_ld_a32_i64: 1616 case INDEX_op_qemu_ld_a64_i64: 1617 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1618 break; 1619 case INDEX_op_qemu_ld_a32_i128: 1620 case INDEX_op_qemu_ld_a64_i128: 1621 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1622 break; 1623 case INDEX_op_qemu_st_a32_i32: 1624 case INDEX_op_qemu_st_a64_i32: 1625 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1626 break; 1627 case INDEX_op_qemu_st_a32_i64: 1628 case INDEX_op_qemu_st_a64_i64: 1629 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1630 break; 1631 case INDEX_op_qemu_st_a32_i128: 1632 case INDEX_op_qemu_st_a64_i128: 1633 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1634 break; 1635 1636 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1637 case INDEX_op_mov_i64: 1638 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1639 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1640 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1641 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1642 case INDEX_op_ext8s_i64: 1643 case INDEX_op_ext8u_i32: 1644 case INDEX_op_ext8u_i64: 1645 case INDEX_op_ext16s_i32: 1646 case INDEX_op_ext16s_i64: 1647 case INDEX_op_ext16u_i32: 1648 case INDEX_op_ext16u_i64: 1649 case INDEX_op_ext32s_i64: 1650 case INDEX_op_ext32u_i64: 1651 case INDEX_op_ext_i32_i64: 1652 case INDEX_op_extu_i32_i64: 1653 case INDEX_op_extrl_i64_i32: 1654 default: 1655 g_assert_not_reached(); 1656 } 1657} 1658 1659static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1660 TCGReg rd, TCGReg rs) 1661{ 1662 switch (vece) { 1663 case MO_8: 1664 tcg_out_opc_vreplgr2vr_b(s, rd, rs); 1665 break; 1666 case MO_16: 1667 tcg_out_opc_vreplgr2vr_h(s, rd, rs); 1668 break; 1669 case MO_32: 1670 tcg_out_opc_vreplgr2vr_w(s, rd, rs); 1671 break; 1672 case MO_64: 1673 tcg_out_opc_vreplgr2vr_d(s, rd, rs); 1674 break; 1675 default: 1676 g_assert_not_reached(); 1677 } 1678 return true; 1679} 1680 1681static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1682 TCGReg r, TCGReg base, intptr_t offset) 1683{ 1684 /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */ 1685 if (offset < -0x800 || offset > 0x7ff || \ 1686 (offset & ((1 << vece) - 1)) != 0) { 1687 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1688 base = TCG_REG_TMP0; 1689 offset = 0; 1690 } 1691 offset >>= vece; 1692 1693 switch (vece) { 1694 case MO_8: 1695 tcg_out_opc_vldrepl_b(s, r, base, offset); 1696 break; 1697 case MO_16: 1698 tcg_out_opc_vldrepl_h(s, r, base, offset); 1699 break; 1700 case MO_32: 1701 tcg_out_opc_vldrepl_w(s, r, base, offset); 1702 break; 1703 case MO_64: 1704 tcg_out_opc_vldrepl_d(s, r, base, offset); 1705 break; 1706 default: 1707 g_assert_not_reached(); 1708 } 1709 return true; 1710} 1711 1712static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1713 TCGReg rd, int64_t v64) 1714{ 1715 /* Try vldi if imm can fit */ 1716 int64_t value = sextract64(v64, 0, 8 << vece); 1717 if (-0x200 <= value && value <= 0x1FF) { 1718 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 1719 tcg_out_opc_vldi(s, rd, imm); 1720 return; 1721 } 1722 1723 /* TODO: vldi patterns when imm 12 is set */ 1724 1725 /* Fallback to vreplgr2vr */ 1726 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 1727 switch (vece) { 1728 case MO_8: 1729 tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0); 1730 break; 1731 case MO_16: 1732 tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0); 1733 break; 1734 case MO_32: 1735 tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0); 1736 break; 1737 case MO_64: 1738 tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0); 1739 break; 1740 default: 1741 g_assert_not_reached(); 1742 } 1743} 1744 1745static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0, 1746 const TCGArg a1, const TCGArg a2, 1747 bool a2_is_const, bool is_add) 1748{ 1749 static const LoongArchInsn add_vec_insn[4] = { 1750 OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D 1751 }; 1752 static const LoongArchInsn add_vec_imm_insn[4] = { 1753 OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU 1754 }; 1755 static const LoongArchInsn sub_vec_insn[4] = { 1756 OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D 1757 }; 1758 static const LoongArchInsn sub_vec_imm_insn[4] = { 1759 OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU 1760 }; 1761 1762 if (a2_is_const) { 1763 int64_t value = sextract64(a2, 0, 8 << vece); 1764 if (!is_add) { 1765 value = -value; 1766 } 1767 1768 /* Try vaddi/vsubi */ 1769 if (0 <= value && value <= 0x1f) { 1770 tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \ 1771 a1, value)); 1772 return; 1773 } else if (-0x1f <= value && value < 0) { 1774 tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \ 1775 a1, -value)); 1776 return; 1777 } 1778 1779 /* constraint TCG_CT_CONST_VADD ensures unreachable */ 1780 g_assert_not_reached(); 1781 } 1782 1783 if (is_add) { 1784 tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2)); 1785 } else { 1786 tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2)); 1787 } 1788} 1789 1790static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 1791 unsigned vecl, unsigned vece, 1792 const TCGArg args[TCG_MAX_OP_ARGS], 1793 const int const_args[TCG_MAX_OP_ARGS]) 1794{ 1795 TCGType type = vecl + TCG_TYPE_V64; 1796 TCGArg a0, a1, a2, a3; 1797 TCGReg temp_vec = TCG_VEC_TMP0; 1798 1799 static const LoongArchInsn cmp_vec_insn[16][4] = { 1800 [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D}, 1801 [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D}, 1802 [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU}, 1803 [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D}, 1804 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU}, 1805 }; 1806 static const LoongArchInsn cmp_vec_imm_insn[16][4] = { 1807 [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D}, 1808 [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D}, 1809 [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU}, 1810 [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D}, 1811 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU}, 1812 }; 1813 LoongArchInsn insn; 1814 static const LoongArchInsn neg_vec_insn[4] = { 1815 OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D 1816 }; 1817 static const LoongArchInsn mul_vec_insn[4] = { 1818 OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D 1819 }; 1820 static const LoongArchInsn smin_vec_insn[4] = { 1821 OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D 1822 }; 1823 static const LoongArchInsn umin_vec_insn[4] = { 1824 OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU 1825 }; 1826 static const LoongArchInsn smax_vec_insn[4] = { 1827 OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D 1828 }; 1829 static const LoongArchInsn umax_vec_insn[4] = { 1830 OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU 1831 }; 1832 static const LoongArchInsn ssadd_vec_insn[4] = { 1833 OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D 1834 }; 1835 static const LoongArchInsn usadd_vec_insn[4] = { 1836 OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU 1837 }; 1838 static const LoongArchInsn sssub_vec_insn[4] = { 1839 OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D 1840 }; 1841 static const LoongArchInsn ussub_vec_insn[4] = { 1842 OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU 1843 }; 1844 static const LoongArchInsn shlv_vec_insn[4] = { 1845 OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D 1846 }; 1847 static const LoongArchInsn shrv_vec_insn[4] = { 1848 OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D 1849 }; 1850 static const LoongArchInsn sarv_vec_insn[4] = { 1851 OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D 1852 }; 1853 static const LoongArchInsn shli_vec_insn[4] = { 1854 OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D 1855 }; 1856 static const LoongArchInsn shri_vec_insn[4] = { 1857 OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D 1858 }; 1859 static const LoongArchInsn sari_vec_insn[4] = { 1860 OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D 1861 }; 1862 static const LoongArchInsn rotrv_vec_insn[4] = { 1863 OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D 1864 }; 1865 1866 a0 = args[0]; 1867 a1 = args[1]; 1868 a2 = args[2]; 1869 a3 = args[3]; 1870 1871 /* Currently only supports V128 */ 1872 tcg_debug_assert(type == TCG_TYPE_V128); 1873 1874 switch (opc) { 1875 case INDEX_op_st_vec: 1876 tcg_out_st(s, type, a0, a1, a2); 1877 break; 1878 case INDEX_op_ld_vec: 1879 tcg_out_ld(s, type, a0, a1, a2); 1880 break; 1881 case INDEX_op_and_vec: 1882 tcg_out_opc_vand_v(s, a0, a1, a2); 1883 break; 1884 case INDEX_op_andc_vec: 1885 /* 1886 * vandn vd, vj, vk: vd = vk & ~vj 1887 * andc_vec vd, vj, vk: vd = vj & ~vk 1888 * vk and vk are swapped 1889 */ 1890 tcg_out_opc_vandn_v(s, a0, a2, a1); 1891 break; 1892 case INDEX_op_or_vec: 1893 tcg_out_opc_vor_v(s, a0, a1, a2); 1894 break; 1895 case INDEX_op_orc_vec: 1896 tcg_out_opc_vorn_v(s, a0, a1, a2); 1897 break; 1898 case INDEX_op_xor_vec: 1899 tcg_out_opc_vxor_v(s, a0, a1, a2); 1900 break; 1901 case INDEX_op_nor_vec: 1902 tcg_out_opc_vnor_v(s, a0, a1, a2); 1903 break; 1904 case INDEX_op_not_vec: 1905 tcg_out_opc_vnor_v(s, a0, a1, a1); 1906 break; 1907 case INDEX_op_cmp_vec: 1908 { 1909 TCGCond cond = args[3]; 1910 if (const_args[2]) { 1911 /* 1912 * cmp_vec dest, src, value 1913 * Try vseqi/vslei/vslti 1914 */ 1915 int64_t value = sextract64(a2, 0, 8 << vece); 1916 if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \ 1917 cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) { 1918 tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \ 1919 a0, a1, value)); 1920 break; 1921 } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) && 1922 (0x00 <= value && value <= 0x1f)) { 1923 tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \ 1924 a0, a1, value)); 1925 break; 1926 } 1927 1928 /* 1929 * Fallback to: 1930 * dupi_vec temp, a2 1931 * cmp_vec a0, a1, temp, cond 1932 */ 1933 tcg_out_dupi_vec(s, type, vece, temp_vec, a2); 1934 a2 = temp_vec; 1935 } 1936 1937 insn = cmp_vec_insn[cond][vece]; 1938 if (insn == 0) { 1939 TCGArg t; 1940 t = a1, a1 = a2, a2 = t; 1941 cond = tcg_swap_cond(cond); 1942 insn = cmp_vec_insn[cond][vece]; 1943 tcg_debug_assert(insn != 0); 1944 } 1945 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 1946 } 1947 break; 1948 case INDEX_op_add_vec: 1949 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true); 1950 break; 1951 case INDEX_op_sub_vec: 1952 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false); 1953 break; 1954 case INDEX_op_neg_vec: 1955 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1)); 1956 break; 1957 case INDEX_op_mul_vec: 1958 tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2)); 1959 break; 1960 case INDEX_op_smin_vec: 1961 tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2)); 1962 break; 1963 case INDEX_op_smax_vec: 1964 tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2)); 1965 break; 1966 case INDEX_op_umin_vec: 1967 tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2)); 1968 break; 1969 case INDEX_op_umax_vec: 1970 tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2)); 1971 break; 1972 case INDEX_op_ssadd_vec: 1973 tcg_out32(s, encode_vdvjvk_insn(ssadd_vec_insn[vece], a0, a1, a2)); 1974 break; 1975 case INDEX_op_usadd_vec: 1976 tcg_out32(s, encode_vdvjvk_insn(usadd_vec_insn[vece], a0, a1, a2)); 1977 break; 1978 case INDEX_op_sssub_vec: 1979 tcg_out32(s, encode_vdvjvk_insn(sssub_vec_insn[vece], a0, a1, a2)); 1980 break; 1981 case INDEX_op_ussub_vec: 1982 tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2)); 1983 break; 1984 case INDEX_op_shlv_vec: 1985 tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2)); 1986 break; 1987 case INDEX_op_shrv_vec: 1988 tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2)); 1989 break; 1990 case INDEX_op_sarv_vec: 1991 tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2)); 1992 break; 1993 case INDEX_op_shli_vec: 1994 tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2)); 1995 break; 1996 case INDEX_op_shri_vec: 1997 tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2)); 1998 break; 1999 case INDEX_op_sari_vec: 2000 tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2)); 2001 break; 2002 case INDEX_op_rotrv_vec: 2003 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2)); 2004 break; 2005 case INDEX_op_rotlv_vec: 2006 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2007 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2)); 2008 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, 2009 temp_vec)); 2010 break; 2011 case INDEX_op_rotli_vec: 2012 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2013 a2 = extract32(-a2, 0, 3 + vece); 2014 switch (vece) { 2015 case MO_8: 2016 tcg_out_opc_vrotri_b(s, a0, a1, a2); 2017 break; 2018 case MO_16: 2019 tcg_out_opc_vrotri_h(s, a0, a1, a2); 2020 break; 2021 case MO_32: 2022 tcg_out_opc_vrotri_w(s, a0, a1, a2); 2023 break; 2024 case MO_64: 2025 tcg_out_opc_vrotri_d(s, a0, a1, a2); 2026 break; 2027 default: 2028 g_assert_not_reached(); 2029 } 2030 break; 2031 case INDEX_op_bitsel_vec: 2032 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2033 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2034 break; 2035 case INDEX_op_dupm_vec: 2036 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2037 break; 2038 default: 2039 g_assert_not_reached(); 2040 } 2041} 2042 2043int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2044{ 2045 switch (opc) { 2046 case INDEX_op_ld_vec: 2047 case INDEX_op_st_vec: 2048 case INDEX_op_dup_vec: 2049 case INDEX_op_dupm_vec: 2050 case INDEX_op_cmp_vec: 2051 case INDEX_op_add_vec: 2052 case INDEX_op_sub_vec: 2053 case INDEX_op_and_vec: 2054 case INDEX_op_andc_vec: 2055 case INDEX_op_or_vec: 2056 case INDEX_op_orc_vec: 2057 case INDEX_op_xor_vec: 2058 case INDEX_op_nor_vec: 2059 case INDEX_op_not_vec: 2060 case INDEX_op_neg_vec: 2061 case INDEX_op_mul_vec: 2062 case INDEX_op_smin_vec: 2063 case INDEX_op_smax_vec: 2064 case INDEX_op_umin_vec: 2065 case INDEX_op_umax_vec: 2066 case INDEX_op_ssadd_vec: 2067 case INDEX_op_usadd_vec: 2068 case INDEX_op_sssub_vec: 2069 case INDEX_op_ussub_vec: 2070 case INDEX_op_shlv_vec: 2071 case INDEX_op_shrv_vec: 2072 case INDEX_op_sarv_vec: 2073 case INDEX_op_bitsel_vec: 2074 return 1; 2075 default: 2076 return 0; 2077 } 2078} 2079 2080void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2081 TCGArg a0, ...) 2082{ 2083 g_assert_not_reached(); 2084} 2085 2086static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2087{ 2088 switch (op) { 2089 case INDEX_op_goto_ptr: 2090 return C_O0_I1(r); 2091 2092 case INDEX_op_st8_i32: 2093 case INDEX_op_st8_i64: 2094 case INDEX_op_st16_i32: 2095 case INDEX_op_st16_i64: 2096 case INDEX_op_st32_i64: 2097 case INDEX_op_st_i32: 2098 case INDEX_op_st_i64: 2099 case INDEX_op_qemu_st_a32_i32: 2100 case INDEX_op_qemu_st_a64_i32: 2101 case INDEX_op_qemu_st_a32_i64: 2102 case INDEX_op_qemu_st_a64_i64: 2103 return C_O0_I2(rZ, r); 2104 2105 case INDEX_op_qemu_ld_a32_i128: 2106 case INDEX_op_qemu_ld_a64_i128: 2107 return C_N2_I1(r, r, r); 2108 2109 case INDEX_op_qemu_st_a32_i128: 2110 case INDEX_op_qemu_st_a64_i128: 2111 return C_O0_I3(r, r, r); 2112 2113 case INDEX_op_brcond_i32: 2114 case INDEX_op_brcond_i64: 2115 return C_O0_I2(rZ, rZ); 2116 2117 case INDEX_op_ext8s_i32: 2118 case INDEX_op_ext8s_i64: 2119 case INDEX_op_ext8u_i32: 2120 case INDEX_op_ext8u_i64: 2121 case INDEX_op_ext16s_i32: 2122 case INDEX_op_ext16s_i64: 2123 case INDEX_op_ext16u_i32: 2124 case INDEX_op_ext16u_i64: 2125 case INDEX_op_ext32s_i64: 2126 case INDEX_op_ext32u_i64: 2127 case INDEX_op_extu_i32_i64: 2128 case INDEX_op_extrl_i64_i32: 2129 case INDEX_op_extrh_i64_i32: 2130 case INDEX_op_ext_i32_i64: 2131 case INDEX_op_neg_i32: 2132 case INDEX_op_neg_i64: 2133 case INDEX_op_not_i32: 2134 case INDEX_op_not_i64: 2135 case INDEX_op_extract_i32: 2136 case INDEX_op_extract_i64: 2137 case INDEX_op_bswap16_i32: 2138 case INDEX_op_bswap16_i64: 2139 case INDEX_op_bswap32_i32: 2140 case INDEX_op_bswap32_i64: 2141 case INDEX_op_bswap64_i64: 2142 case INDEX_op_ld8s_i32: 2143 case INDEX_op_ld8s_i64: 2144 case INDEX_op_ld8u_i32: 2145 case INDEX_op_ld8u_i64: 2146 case INDEX_op_ld16s_i32: 2147 case INDEX_op_ld16s_i64: 2148 case INDEX_op_ld16u_i32: 2149 case INDEX_op_ld16u_i64: 2150 case INDEX_op_ld32s_i64: 2151 case INDEX_op_ld32u_i64: 2152 case INDEX_op_ld_i32: 2153 case INDEX_op_ld_i64: 2154 case INDEX_op_qemu_ld_a32_i32: 2155 case INDEX_op_qemu_ld_a64_i32: 2156 case INDEX_op_qemu_ld_a32_i64: 2157 case INDEX_op_qemu_ld_a64_i64: 2158 return C_O1_I1(r, r); 2159 2160 case INDEX_op_andc_i32: 2161 case INDEX_op_andc_i64: 2162 case INDEX_op_orc_i32: 2163 case INDEX_op_orc_i64: 2164 /* 2165 * LoongArch insns for these ops don't have reg-imm forms, but we 2166 * can express using andi/ori if ~constant satisfies 2167 * TCG_CT_CONST_U12. 2168 */ 2169 return C_O1_I2(r, r, rC); 2170 2171 case INDEX_op_shl_i32: 2172 case INDEX_op_shl_i64: 2173 case INDEX_op_shr_i32: 2174 case INDEX_op_shr_i64: 2175 case INDEX_op_sar_i32: 2176 case INDEX_op_sar_i64: 2177 case INDEX_op_rotl_i32: 2178 case INDEX_op_rotl_i64: 2179 case INDEX_op_rotr_i32: 2180 case INDEX_op_rotr_i64: 2181 return C_O1_I2(r, r, ri); 2182 2183 case INDEX_op_add_i32: 2184 return C_O1_I2(r, r, ri); 2185 case INDEX_op_add_i64: 2186 return C_O1_I2(r, r, rJ); 2187 2188 case INDEX_op_and_i32: 2189 case INDEX_op_and_i64: 2190 case INDEX_op_nor_i32: 2191 case INDEX_op_nor_i64: 2192 case INDEX_op_or_i32: 2193 case INDEX_op_or_i64: 2194 case INDEX_op_xor_i32: 2195 case INDEX_op_xor_i64: 2196 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 2197 return C_O1_I2(r, r, rU); 2198 2199 case INDEX_op_clz_i32: 2200 case INDEX_op_clz_i64: 2201 case INDEX_op_ctz_i32: 2202 case INDEX_op_ctz_i64: 2203 return C_O1_I2(r, r, rW); 2204 2205 case INDEX_op_deposit_i32: 2206 case INDEX_op_deposit_i64: 2207 /* Must deposit into the same register as input */ 2208 return C_O1_I2(r, 0, rZ); 2209 2210 case INDEX_op_sub_i32: 2211 case INDEX_op_setcond_i32: 2212 return C_O1_I2(r, rZ, ri); 2213 case INDEX_op_sub_i64: 2214 case INDEX_op_setcond_i64: 2215 return C_O1_I2(r, rZ, rJ); 2216 2217 case INDEX_op_mul_i32: 2218 case INDEX_op_mul_i64: 2219 case INDEX_op_mulsh_i32: 2220 case INDEX_op_mulsh_i64: 2221 case INDEX_op_muluh_i32: 2222 case INDEX_op_muluh_i64: 2223 case INDEX_op_div_i32: 2224 case INDEX_op_div_i64: 2225 case INDEX_op_divu_i32: 2226 case INDEX_op_divu_i64: 2227 case INDEX_op_rem_i32: 2228 case INDEX_op_rem_i64: 2229 case INDEX_op_remu_i32: 2230 case INDEX_op_remu_i64: 2231 return C_O1_I2(r, rZ, rZ); 2232 2233 case INDEX_op_movcond_i32: 2234 case INDEX_op_movcond_i64: 2235 return C_O1_I4(r, rZ, rJ, rZ, rZ); 2236 2237 case INDEX_op_ld_vec: 2238 case INDEX_op_dupm_vec: 2239 case INDEX_op_dup_vec: 2240 return C_O1_I1(w, r); 2241 2242 case INDEX_op_st_vec: 2243 return C_O0_I2(w, r); 2244 2245 case INDEX_op_cmp_vec: 2246 return C_O1_I2(w, w, wM); 2247 2248 case INDEX_op_add_vec: 2249 case INDEX_op_sub_vec: 2250 return C_O1_I2(w, w, wA); 2251 2252 case INDEX_op_and_vec: 2253 case INDEX_op_andc_vec: 2254 case INDEX_op_or_vec: 2255 case INDEX_op_orc_vec: 2256 case INDEX_op_xor_vec: 2257 case INDEX_op_nor_vec: 2258 case INDEX_op_mul_vec: 2259 case INDEX_op_smin_vec: 2260 case INDEX_op_smax_vec: 2261 case INDEX_op_umin_vec: 2262 case INDEX_op_umax_vec: 2263 case INDEX_op_ssadd_vec: 2264 case INDEX_op_usadd_vec: 2265 case INDEX_op_sssub_vec: 2266 case INDEX_op_ussub_vec: 2267 case INDEX_op_shlv_vec: 2268 case INDEX_op_shrv_vec: 2269 case INDEX_op_sarv_vec: 2270 case INDEX_op_rotrv_vec: 2271 case INDEX_op_rotlv_vec: 2272 return C_O1_I2(w, w, w); 2273 2274 case INDEX_op_not_vec: 2275 case INDEX_op_neg_vec: 2276 case INDEX_op_shli_vec: 2277 case INDEX_op_shri_vec: 2278 case INDEX_op_sari_vec: 2279 case INDEX_op_rotli_vec: 2280 return C_O1_I1(w, w); 2281 2282 case INDEX_op_bitsel_vec: 2283 return C_O1_I3(w, w, w, w); 2284 2285 default: 2286 g_assert_not_reached(); 2287 } 2288} 2289 2290static const int tcg_target_callee_save_regs[] = { 2291 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2292 TCG_REG_S1, 2293 TCG_REG_S2, 2294 TCG_REG_S3, 2295 TCG_REG_S4, 2296 TCG_REG_S5, 2297 TCG_REG_S6, 2298 TCG_REG_S7, 2299 TCG_REG_S8, 2300 TCG_REG_S9, 2301 TCG_REG_RA, /* should be last for ABI compliance */ 2302}; 2303 2304/* Stack frame parameters. */ 2305#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2306#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2307#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2308#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2309 + TCG_TARGET_STACK_ALIGN - 1) \ 2310 & -TCG_TARGET_STACK_ALIGN) 2311#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2312 2313/* We're expecting to be able to use an immediate for frame allocation. */ 2314QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2315 2316/* Generate global QEMU prologue and epilogue code */ 2317static void tcg_target_qemu_prologue(TCGContext *s) 2318{ 2319 int i; 2320 2321 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2322 2323 /* TB prologue */ 2324 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2325 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2326 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2327 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2328 } 2329 2330 if (!tcg_use_softmmu && guest_base) { 2331 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2332 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2333 } 2334 2335 /* Call generated code */ 2336 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2337 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2338 2339 /* Return path for goto_ptr. Set return value to 0 */ 2340 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2341 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2342 2343 /* TB epilogue */ 2344 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2345 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2346 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2347 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2348 } 2349 2350 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2351 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2352} 2353 2354static void tcg_out_tb_start(TCGContext *s) 2355{ 2356 /* nothing to do */ 2357} 2358 2359static void tcg_target_init(TCGContext *s) 2360{ 2361 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2362 2363 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2364 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2365 error_report("TCG: unaligned access support required; exiting"); 2366 exit(EXIT_FAILURE); 2367 } 2368 2369 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2370 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2371 2372 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2373 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2374 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2375 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2376 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2377 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2378 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2379 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2380 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2381 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2382 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2383 2384 if (cpuinfo & CPUINFO_LSX) { 2385 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2386 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2387 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2388 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2389 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2390 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2391 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2392 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2393 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2394 } 2395 2396 s->reserved_regs = 0; 2397 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2398 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2399 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2400 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2401 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2402 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2403 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2404 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2405} 2406 2407typedef struct { 2408 DebugFrameHeader h; 2409 uint8_t fde_def_cfa[4]; 2410 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2411} DebugFrame; 2412 2413#define ELF_HOST_MACHINE EM_LOONGARCH 2414 2415static const DebugFrame debug_frame = { 2416 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2417 .h.cie.id = -1, 2418 .h.cie.version = 1, 2419 .h.cie.code_align = 1, 2420 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2421 .h.cie.return_column = TCG_REG_RA, 2422 2423 /* Total FDE size does not include the "len" member. */ 2424 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2425 2426 .fde_def_cfa = { 2427 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2428 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2429 (FRAME_SIZE >> 7) 2430 }, 2431 .fde_reg_ofs = { 2432 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2433 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2434 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2435 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2436 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2437 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2438 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2439 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2440 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2441 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2442 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2443 } 2444}; 2445 2446void tcg_register_jit(const void *buf, size_t buf_size) 2447{ 2448 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2449} 2450