1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33#include <asm/hwcap.h> 34 35#ifdef CONFIG_DEBUG_TCG 36static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 37 "zero", 38 "ra", 39 "tp", 40 "sp", 41 "a0", 42 "a1", 43 "a2", 44 "a3", 45 "a4", 46 "a5", 47 "a6", 48 "a7", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "t8", 58 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 59 "s9", 60 "s0", 61 "s1", 62 "s2", 63 "s3", 64 "s4", 65 "s5", 66 "s6", 67 "s7", 68 "s8", 69 "vr0", 70 "vr1", 71 "vr2", 72 "vr3", 73 "vr4", 74 "vr5", 75 "vr6", 76 "vr7", 77 "vr8", 78 "vr9", 79 "vr10", 80 "vr11", 81 "vr12", 82 "vr13", 83 "vr14", 84 "vr15", 85 "vr16", 86 "vr17", 87 "vr18", 88 "vr19", 89 "vr20", 90 "vr21", 91 "vr22", 92 "vr23", 93 "vr24", 94 "vr25", 95 "vr26", 96 "vr27", 97 "vr28", 98 "vr29", 99 "vr30", 100 "vr31", 101}; 102#endif 103 104static const int tcg_target_reg_alloc_order[] = { 105 /* Registers preserved across calls */ 106 /* TCG_REG_S0 reserved for TCG_AREG0 */ 107 TCG_REG_S1, 108 TCG_REG_S2, 109 TCG_REG_S3, 110 TCG_REG_S4, 111 TCG_REG_S5, 112 TCG_REG_S6, 113 TCG_REG_S7, 114 TCG_REG_S8, 115 TCG_REG_S9, 116 117 /* Registers (potentially) clobbered across calls */ 118 TCG_REG_T0, 119 TCG_REG_T1, 120 TCG_REG_T2, 121 TCG_REG_T3, 122 TCG_REG_T4, 123 TCG_REG_T5, 124 TCG_REG_T6, 125 TCG_REG_T7, 126 TCG_REG_T8, 127 128 /* Argument registers, opposite order of allocation. */ 129 TCG_REG_A7, 130 TCG_REG_A6, 131 TCG_REG_A5, 132 TCG_REG_A4, 133 TCG_REG_A3, 134 TCG_REG_A2, 135 TCG_REG_A1, 136 TCG_REG_A0, 137 138 /* Vector registers */ 139 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 140 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 141 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 142 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 143 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 144 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 145 /* V24 - V31 are caller-saved, and skipped. */ 146}; 147 148static const int tcg_target_call_iarg_regs[] = { 149 TCG_REG_A0, 150 TCG_REG_A1, 151 TCG_REG_A2, 152 TCG_REG_A3, 153 TCG_REG_A4, 154 TCG_REG_A5, 155 TCG_REG_A6, 156 TCG_REG_A7, 157}; 158 159static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 160{ 161 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 162 tcg_debug_assert(slot >= 0 && slot <= 1); 163 return TCG_REG_A0 + slot; 164} 165 166#define TCG_GUEST_BASE_REG TCG_REG_S1 167 168#define TCG_CT_CONST_ZERO 0x100 169#define TCG_CT_CONST_S12 0x200 170#define TCG_CT_CONST_S32 0x400 171#define TCG_CT_CONST_U12 0x800 172#define TCG_CT_CONST_C12 0x1000 173#define TCG_CT_CONST_WSZ 0x2000 174#define TCG_CT_CONST_VCMP 0x4000 175#define TCG_CT_CONST_VADD 0x8000 176 177#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 178#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 179 180static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 181{ 182 return sextract64(val, pos, len); 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, int ct, 187 TCGType type, TCGCond cond, int vece) 188{ 189 if (ct & TCG_CT_CONST) { 190 return true; 191 } 192 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 193 return true; 194 } 195 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 int64_t vec_val = sextract64(val, 0, 8 << vece); 211 if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) { 212 return true; 213 } 214 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 215 return true; 216 } 217 return false; 218} 219 220/* 221 * Relocations 222 */ 223 224/* 225 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 226 * complicated; a whopping stack machine is needed to stuff the fields, at 227 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 228 * needed. 229 * 230 * Hence, define our own simpler relocation types. Numbers are chosen as to 231 * not collide with potential future additions to the true ELF relocation 232 * type enum. 233 */ 234 235/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 236#define R_LOONGARCH_BR_SK16 256 237/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 238#define R_LOONGARCH_BR_SD10K16 257 239 240static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 241{ 242 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 243 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 244 245 tcg_debug_assert((offset & 3) == 0); 246 offset >>= 2; 247 if (offset == sextreg(offset, 0, 16)) { 248 *src_rw = deposit64(*src_rw, 10, 16, offset); 249 return true; 250 } 251 252 return false; 253} 254 255static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 256 const tcg_insn_unit *target) 257{ 258 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 259 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 260 261 tcg_debug_assert((offset & 3) == 0); 262 offset >>= 2; 263 if (offset == sextreg(offset, 0, 26)) { 264 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 265 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 266 return true; 267 } 268 269 return false; 270} 271 272static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 273 intptr_t value, intptr_t addend) 274{ 275 tcg_debug_assert(addend == 0); 276 switch (type) { 277 case R_LOONGARCH_BR_SK16: 278 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 279 case R_LOONGARCH_BR_SD10K16: 280 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 281 default: 282 g_assert_not_reached(); 283 } 284} 285 286#include "tcg-insn-defs.c.inc" 287 288/* 289 * TCG intrinsics 290 */ 291 292static void tcg_out_mb(TCGContext *s, TCGArg a0) 293{ 294 /* Baseline LoongArch only has the full barrier, unfortunately. */ 295 tcg_out_opc_dbar(s, 0); 296} 297 298static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 299{ 300 if (ret == arg) { 301 return true; 302 } 303 switch (type) { 304 case TCG_TYPE_I32: 305 case TCG_TYPE_I64: 306 if (ret < TCG_REG_V0) { 307 if (arg < TCG_REG_V0) { 308 /* 309 * Conventional register-register move used in LoongArch is 310 * `or dst, src, zero`. 311 */ 312 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 313 } else { 314 tcg_out_opc_movfr2gr_d(s, ret, arg); 315 } 316 } else { 317 if (arg < TCG_REG_V0) { 318 tcg_out_opc_movgr2fr_d(s, ret, arg); 319 } else { 320 tcg_out_opc_fmov_d(s, ret, arg); 321 } 322 } 323 break; 324 case TCG_TYPE_V128: 325 tcg_out_opc_vori_b(s, ret, arg, 0); 326 break; 327 default: 328 g_assert_not_reached(); 329 } 330 return true; 331} 332 333/* Loads a 32-bit immediate into rd, sign-extended. */ 334static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 335{ 336 tcg_target_long lo = sextreg(val, 0, 12); 337 tcg_target_long hi12 = sextreg(val, 12, 20); 338 339 /* Single-instruction cases. */ 340 if (hi12 == 0) { 341 /* val fits in uimm12: ori rd, zero, val */ 342 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 343 return; 344 } 345 if (hi12 == sextreg(lo, 12, 20)) { 346 /* val fits in simm12: addi.w rd, zero, val */ 347 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 348 return; 349 } 350 351 /* High bits must be set; load with lu12i.w + optional ori. */ 352 tcg_out_opc_lu12i_w(s, rd, hi12); 353 if (lo != 0) { 354 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 355 } 356} 357 358static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 359 tcg_target_long val) 360{ 361 /* 362 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 363 * with dedicated instructions for filling the respective bitfields 364 * below: 365 * 366 * 6 5 4 3 367 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 368 * +-----------------------+---------------------------------------+... 369 * | hi52 | hi32 | 370 * +-----------------------+---------------------------------------+... 371 * 3 2 1 372 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 373 * ...+-------------------------------------+-------------------------+ 374 * | hi12 | lo | 375 * ...+-------------------------------------+-------------------------+ 376 * 377 * Check if val belong to one of the several fast cases, before falling 378 * back to the slow path. 379 */ 380 381 intptr_t pc_offset; 382 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 383 tcg_target_long hi12, hi32, hi52; 384 385 /* Value fits in signed i32. */ 386 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 387 tcg_out_movi_i32(s, rd, val); 388 return; 389 } 390 391 /* PC-relative cases. */ 392 pc_offset = tcg_pcrel_diff(s, (void *)val); 393 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 394 /* Single pcaddu2i. */ 395 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 396 return; 397 } 398 399 if (pc_offset == (int32_t)pc_offset) { 400 /* Offset within 32 bits; load with pcalau12i + ori. */ 401 val_lo = sextreg(val, 0, 12); 402 val_hi = val >> 12; 403 pc_hi = (val - pc_offset) >> 12; 404 offset_hi = val_hi - pc_hi; 405 406 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 407 tcg_out_opc_pcalau12i(s, rd, offset_hi); 408 if (val_lo != 0) { 409 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 410 } 411 return; 412 } 413 414 hi12 = sextreg(val, 12, 20); 415 hi32 = sextreg(val, 32, 20); 416 hi52 = sextreg(val, 52, 12); 417 418 /* Single cu52i.d case. */ 419 if ((hi52 != 0) && (ctz64(val) >= 52)) { 420 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 421 return; 422 } 423 424 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 425 tcg_out_movi_i32(s, rd, val); 426 427 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 428 if (hi32 != sextreg(hi12, 20, 20)) { 429 tcg_out_opc_cu32i_d(s, rd, hi32); 430 } 431 432 if (hi52 != sextreg(hi32, 20, 12)) { 433 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 434 } 435} 436 437static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 438 TCGReg rs, tcg_target_long imm) 439{ 440 tcg_target_long lo12 = sextreg(imm, 0, 12); 441 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 442 443 /* 444 * Note that there's a hole in between hi16 and lo12: 445 * 446 * 3 2 1 0 447 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 448 * ...+-------------------------------+-------+-----------------------+ 449 * | hi16 | | lo12 | 450 * ...+-------------------------------+-------+-----------------------+ 451 * 452 * For bits within that hole, it's more efficient to use LU12I and ADD. 453 */ 454 if (imm == (hi16 << 16) + lo12) { 455 if (hi16) { 456 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 457 rs = rd; 458 } 459 if (type == TCG_TYPE_I32) { 460 tcg_out_opc_addi_w(s, rd, rs, lo12); 461 } else if (lo12) { 462 tcg_out_opc_addi_d(s, rd, rs, lo12); 463 } else { 464 tcg_out_mov(s, type, rd, rs); 465 } 466 } else { 467 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 468 if (type == TCG_TYPE_I32) { 469 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 470 } else { 471 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 472 } 473 } 474} 475 476static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 477{ 478 return false; 479} 480 481static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 482 tcg_target_long imm) 483{ 484 /* This function is only used for passing structs by reference. */ 485 g_assert_not_reached(); 486} 487 488static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 489{ 490 tcg_out_opc_andi(s, ret, arg, 0xff); 491} 492 493static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 494{ 495 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 496} 497 498static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 499{ 500 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 501} 502 503static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 504{ 505 tcg_out_opc_sext_b(s, ret, arg); 506} 507 508static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 509{ 510 tcg_out_opc_sext_h(s, ret, arg); 511} 512 513static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 514{ 515 tcg_out_opc_addi_w(s, ret, arg, 0); 516} 517 518static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 519{ 520 if (ret != arg) { 521 tcg_out_ext32s(s, ret, arg); 522 } 523} 524 525static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 526{ 527 tcg_out_ext32u(s, ret, arg); 528} 529 530static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 531{ 532 tcg_out_ext32s(s, ret, arg); 533} 534 535static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 536 TCGReg a0, TCGReg a1, TCGReg a2, 537 bool c2, bool is_32bit) 538{ 539 if (c2) { 540 /* 541 * Fast path: semantics already satisfied due to constraint and 542 * insn behavior, single instruction is enough. 543 */ 544 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 545 /* all clz/ctz insns belong to DJ-format */ 546 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 547 return; 548 } 549 550 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 551 /* a0 = a1 ? REG_TMP0 : a2 */ 552 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 553 tcg_out_opc_masknez(s, a0, a2, a1); 554 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 555} 556 557#define SETCOND_INV TCG_TARGET_NB_REGS 558#define SETCOND_NEZ (SETCOND_INV << 1) 559#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 560 561static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 562 TCGReg arg1, tcg_target_long arg2, bool c2) 563{ 564 int flags = 0; 565 566 switch (cond) { 567 case TCG_COND_EQ: /* -> NE */ 568 case TCG_COND_GE: /* -> LT */ 569 case TCG_COND_GEU: /* -> LTU */ 570 case TCG_COND_GT: /* -> LE */ 571 case TCG_COND_GTU: /* -> LEU */ 572 cond = tcg_invert_cond(cond); 573 flags ^= SETCOND_INV; 574 break; 575 default: 576 break; 577 } 578 579 switch (cond) { 580 case TCG_COND_LE: 581 case TCG_COND_LEU: 582 /* 583 * If we have a constant input, the most efficient way to implement 584 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 585 * We don't need to care for this for LE because the constant input 586 * is still constrained to int32_t, and INT32_MAX+1 is representable 587 * in the 64-bit temporary register. 588 */ 589 if (c2) { 590 if (cond == TCG_COND_LEU) { 591 /* unsigned <= -1 is true */ 592 if (arg2 == -1) { 593 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 594 return ret; 595 } 596 cond = TCG_COND_LTU; 597 } else { 598 cond = TCG_COND_LT; 599 } 600 arg2 += 1; 601 } else { 602 TCGReg tmp = arg2; 603 arg2 = arg1; 604 arg1 = tmp; 605 cond = tcg_swap_cond(cond); /* LE -> GE */ 606 cond = tcg_invert_cond(cond); /* GE -> LT */ 607 flags ^= SETCOND_INV; 608 } 609 break; 610 default: 611 break; 612 } 613 614 switch (cond) { 615 case TCG_COND_NE: 616 flags |= SETCOND_NEZ; 617 if (!c2) { 618 tcg_out_opc_xor(s, ret, arg1, arg2); 619 } else if (arg2 == 0) { 620 ret = arg1; 621 } else if (arg2 >= 0 && arg2 <= 0xfff) { 622 tcg_out_opc_xori(s, ret, arg1, arg2); 623 } else { 624 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 625 } 626 break; 627 628 case TCG_COND_LT: 629 case TCG_COND_LTU: 630 if (c2) { 631 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 632 if (cond == TCG_COND_LT) { 633 tcg_out_opc_slti(s, ret, arg1, arg2); 634 } else { 635 tcg_out_opc_sltui(s, ret, arg1, arg2); 636 } 637 break; 638 } 639 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 640 arg2 = TCG_REG_TMP0; 641 } 642 if (cond == TCG_COND_LT) { 643 tcg_out_opc_slt(s, ret, arg1, arg2); 644 } else { 645 tcg_out_opc_sltu(s, ret, arg1, arg2); 646 } 647 break; 648 649 default: 650 g_assert_not_reached(); 651 break; 652 } 653 654 return ret | flags; 655} 656 657static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 658 TCGReg arg1, tcg_target_long arg2, bool c2) 659{ 660 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 661 662 if (tmpflags != ret) { 663 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 664 665 switch (tmpflags & SETCOND_FLAGS) { 666 case SETCOND_INV: 667 /* Intermediate result is boolean: simply invert. */ 668 tcg_out_opc_xori(s, ret, tmp, 1); 669 break; 670 case SETCOND_NEZ: 671 /* Intermediate result is zero/non-zero: test != 0. */ 672 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 673 break; 674 case SETCOND_NEZ | SETCOND_INV: 675 /* Intermediate result is zero/non-zero: test == 0. */ 676 tcg_out_opc_sltui(s, ret, tmp, 1); 677 break; 678 default: 679 g_assert_not_reached(); 680 } 681 } 682} 683 684static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 685 TCGReg c1, tcg_target_long c2, bool const2, 686 TCGReg v1, TCGReg v2) 687{ 688 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 689 TCGReg t; 690 691 /* Standardize the test below to t != 0. */ 692 if (tmpflags & SETCOND_INV) { 693 t = v1, v1 = v2, v2 = t; 694 } 695 696 t = tmpflags & ~SETCOND_FLAGS; 697 if (v1 == TCG_REG_ZERO) { 698 tcg_out_opc_masknez(s, ret, v2, t); 699 } else if (v2 == TCG_REG_ZERO) { 700 tcg_out_opc_maskeqz(s, ret, v1, t); 701 } else { 702 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 703 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 704 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 705 } 706} 707 708/* 709 * Branch helpers 710 */ 711 712static const struct { 713 LoongArchInsn op; 714 bool swap; 715} tcg_brcond_to_loongarch[] = { 716 [TCG_COND_EQ] = { OPC_BEQ, false }, 717 [TCG_COND_NE] = { OPC_BNE, false }, 718 [TCG_COND_LT] = { OPC_BGT, true }, 719 [TCG_COND_GE] = { OPC_BLE, true }, 720 [TCG_COND_LE] = { OPC_BLE, false }, 721 [TCG_COND_GT] = { OPC_BGT, false }, 722 [TCG_COND_LTU] = { OPC_BGTU, true }, 723 [TCG_COND_GEU] = { OPC_BLEU, true }, 724 [TCG_COND_LEU] = { OPC_BLEU, false }, 725 [TCG_COND_GTU] = { OPC_BGTU, false } 726}; 727 728static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 729 TCGReg arg2, TCGLabel *l) 730{ 731 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 732 733 tcg_debug_assert(op != 0); 734 735 if (tcg_brcond_to_loongarch[cond].swap) { 736 TCGReg t = arg1; 737 arg1 = arg2; 738 arg2 = t; 739 } 740 741 /* all conditional branch insns belong to DJSk16-format */ 742 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 743 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 744} 745 746static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 747{ 748 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 749 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 750 751 tcg_debug_assert((offset & 3) == 0); 752 if (offset == sextreg(offset, 0, 28)) { 753 /* short jump: +/- 256MiB */ 754 if (tail) { 755 tcg_out_opc_b(s, offset >> 2); 756 } else { 757 tcg_out_opc_bl(s, offset >> 2); 758 } 759 } else if (offset == sextreg(offset, 0, 38)) { 760 /* long jump: +/- 256GiB */ 761 tcg_target_long lo = sextreg(offset, 0, 18); 762 tcg_target_long hi = offset - lo; 763 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 764 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 765 } else { 766 /* far jump: 64-bit */ 767 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 768 tcg_target_long hi = (tcg_target_long)arg - lo; 769 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 770 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 771 } 772} 773 774static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 775 const TCGHelperInfo *info) 776{ 777 tcg_out_call_int(s, arg, false); 778} 779 780/* 781 * Load/store helpers 782 */ 783 784static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 785 TCGReg addr, intptr_t offset) 786{ 787 intptr_t imm12 = sextreg(offset, 0, 12); 788 789 if (offset != imm12) { 790 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 791 792 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 793 imm12 = sextreg(diff, 0, 12); 794 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 795 } else { 796 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 797 if (addr != TCG_REG_ZERO) { 798 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 799 } 800 } 801 addr = TCG_REG_TMP2; 802 } 803 804 switch (opc) { 805 case OPC_LD_B: 806 case OPC_LD_BU: 807 case OPC_LD_H: 808 case OPC_LD_HU: 809 case OPC_LD_W: 810 case OPC_LD_WU: 811 case OPC_LD_D: 812 case OPC_ST_B: 813 case OPC_ST_H: 814 case OPC_ST_W: 815 case OPC_ST_D: 816 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 817 break; 818 case OPC_FLD_S: 819 case OPC_FLD_D: 820 case OPC_FST_S: 821 case OPC_FST_D: 822 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 823 break; 824 default: 825 g_assert_not_reached(); 826 } 827} 828 829static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 830 TCGReg base, intptr_t offset) 831{ 832 switch (type) { 833 case TCG_TYPE_I32: 834 if (dest < TCG_REG_V0) { 835 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 836 } else { 837 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 838 } 839 break; 840 case TCG_TYPE_I64: 841 if (dest < TCG_REG_V0) { 842 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 843 } else { 844 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 845 } 846 break; 847 case TCG_TYPE_V128: 848 if (-0x800 <= offset && offset <= 0x7ff) { 849 tcg_out_opc_vld(s, dest, base, offset); 850 } else { 851 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 852 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 853 } 854 break; 855 default: 856 g_assert_not_reached(); 857 } 858} 859 860static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 861 TCGReg base, intptr_t offset) 862{ 863 switch (type) { 864 case TCG_TYPE_I32: 865 if (src < TCG_REG_V0) { 866 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 867 } else { 868 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 869 } 870 break; 871 case TCG_TYPE_I64: 872 if (src < TCG_REG_V0) { 873 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 874 } else { 875 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 876 } 877 break; 878 case TCG_TYPE_V128: 879 if (-0x800 <= offset && offset <= 0x7ff) { 880 tcg_out_opc_vst(s, src, base, offset); 881 } else { 882 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 883 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 884 } 885 break; 886 default: 887 g_assert_not_reached(); 888 } 889} 890 891static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 892 TCGReg base, intptr_t ofs) 893{ 894 if (val == 0) { 895 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 896 return true; 897 } 898 return false; 899} 900 901/* 902 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 903 */ 904 905static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 906{ 907 tcg_out_opc_b(s, 0); 908 return reloc_br_sd10k16(s->code_ptr - 1, target); 909} 910 911static const TCGLdstHelperParam ldst_helper_param = { 912 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 913}; 914 915static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 916{ 917 MemOp opc = get_memop(l->oi); 918 919 /* resolve label address */ 920 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 921 return false; 922 } 923 924 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 925 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 926 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 927 return tcg_out_goto(s, l->raddr); 928} 929 930static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 931{ 932 MemOp opc = get_memop(l->oi); 933 934 /* resolve label address */ 935 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 936 return false; 937 } 938 939 tcg_out_st_helper_args(s, l, &ldst_helper_param); 940 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 941 return tcg_out_goto(s, l->raddr); 942} 943 944typedef struct { 945 TCGReg base; 946 TCGReg index; 947 TCGAtomAlign aa; 948} HostAddress; 949 950bool tcg_target_has_memory_bswap(MemOp memop) 951{ 952 return false; 953} 954 955/* We expect to use a 12-bit negative offset from ENV. */ 956#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 957 958/* 959 * For system-mode, perform the TLB load and compare. 960 * For user-mode, perform any required alignment tests. 961 * In both cases, return a TCGLabelQemuLdst structure if the slow path 962 * is required and fill in @h with the host address for the fast path. 963 */ 964static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 965 TCGReg addr_reg, MemOpIdx oi, 966 bool is_ld) 967{ 968 TCGType addr_type = s->addr_type; 969 TCGLabelQemuLdst *ldst = NULL; 970 MemOp opc = get_memop(oi); 971 MemOp a_bits; 972 973 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 974 a_bits = h->aa.align; 975 976 if (tcg_use_softmmu) { 977 unsigned s_bits = opc & MO_SIZE; 978 int mem_index = get_mmuidx(oi); 979 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 980 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 981 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 982 983 ldst = new_ldst_label(s); 984 ldst->is_ld = is_ld; 985 ldst->oi = oi; 986 ldst->addrlo_reg = addr_reg; 987 988 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 989 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 990 991 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 992 s->page_bits - CPU_TLB_ENTRY_BITS); 993 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 994 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 995 996 /* Load the tlb comparator and the addend. */ 997 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 998 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 999 is_ld ? offsetof(CPUTLBEntry, addr_read) 1000 : offsetof(CPUTLBEntry, addr_write)); 1001 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1002 offsetof(CPUTLBEntry, addend)); 1003 1004 /* 1005 * For aligned accesses, we check the first byte and include the 1006 * alignment bits within the address. For unaligned access, we 1007 * check that we don't cross pages using the address of the last 1008 * byte of the access. 1009 */ 1010 if (a_bits < s_bits) { 1011 unsigned a_mask = (1u << a_bits) - 1; 1012 unsigned s_mask = (1u << s_bits) - 1; 1013 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1014 } else { 1015 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1016 } 1017 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1018 a_bits, s->page_bits - 1); 1019 1020 /* Compare masked address with the TLB entry. */ 1021 ldst->label_ptr[0] = s->code_ptr; 1022 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1023 1024 h->index = TCG_REG_TMP2; 1025 } else { 1026 if (a_bits) { 1027 ldst = new_ldst_label(s); 1028 1029 ldst->is_ld = is_ld; 1030 ldst->oi = oi; 1031 ldst->addrlo_reg = addr_reg; 1032 1033 /* 1034 * Without micro-architecture details, we don't know which of 1035 * bstrpick or andi is faster, so use bstrpick as it's not 1036 * constrained by imm field width. Not to say alignments >= 2^12 1037 * are going to happen any time soon. 1038 */ 1039 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1040 1041 ldst->label_ptr[0] = s->code_ptr; 1042 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1043 } 1044 1045 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1046 } 1047 1048 if (addr_type == TCG_TYPE_I32) { 1049 h->base = TCG_REG_TMP0; 1050 tcg_out_ext32u(s, h->base, addr_reg); 1051 } else { 1052 h->base = addr_reg; 1053 } 1054 1055 return ldst; 1056} 1057 1058static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1059 TCGReg rd, HostAddress h) 1060{ 1061 /* Byte swapping is left to middle-end expansion. */ 1062 tcg_debug_assert((opc & MO_BSWAP) == 0); 1063 1064 switch (opc & MO_SSIZE) { 1065 case MO_UB: 1066 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1067 break; 1068 case MO_SB: 1069 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1070 break; 1071 case MO_UW: 1072 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1073 break; 1074 case MO_SW: 1075 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1076 break; 1077 case MO_UL: 1078 if (type == TCG_TYPE_I64) { 1079 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1080 break; 1081 } 1082 /* fallthrough */ 1083 case MO_SL: 1084 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1085 break; 1086 case MO_UQ: 1087 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1088 break; 1089 default: 1090 g_assert_not_reached(); 1091 } 1092} 1093 1094static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1095 MemOpIdx oi, TCGType data_type) 1096{ 1097 TCGLabelQemuLdst *ldst; 1098 HostAddress h; 1099 1100 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1101 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1102 1103 if (ldst) { 1104 ldst->type = data_type; 1105 ldst->datalo_reg = data_reg; 1106 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1107 } 1108} 1109 1110static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1111 TCGReg rd, HostAddress h) 1112{ 1113 /* Byte swapping is left to middle-end expansion. */ 1114 tcg_debug_assert((opc & MO_BSWAP) == 0); 1115 1116 switch (opc & MO_SIZE) { 1117 case MO_8: 1118 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1119 break; 1120 case MO_16: 1121 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1122 break; 1123 case MO_32: 1124 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1125 break; 1126 case MO_64: 1127 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1128 break; 1129 default: 1130 g_assert_not_reached(); 1131 } 1132} 1133 1134static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1135 MemOpIdx oi, TCGType data_type) 1136{ 1137 TCGLabelQemuLdst *ldst; 1138 HostAddress h; 1139 1140 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1141 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1142 1143 if (ldst) { 1144 ldst->type = data_type; 1145 ldst->datalo_reg = data_reg; 1146 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1147 } 1148} 1149 1150static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1151 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1152{ 1153 TCGLabelQemuLdst *ldst; 1154 HostAddress h; 1155 1156 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1157 1158 if (h.aa.atom == MO_128) { 1159 /* 1160 * Use VLDX/VSTX when 128-bit atomicity is required. 1161 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1162 */ 1163 if (is_ld) { 1164 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1165 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1166 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1167 } else { 1168 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1169 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1170 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1171 } 1172 } else { 1173 /* Otherwise use a pair of LD/ST. */ 1174 TCGReg base = h.base; 1175 if (h.index != TCG_REG_ZERO) { 1176 base = TCG_REG_TMP0; 1177 tcg_out_opc_add_d(s, base, h.base, h.index); 1178 } 1179 if (is_ld) { 1180 tcg_debug_assert(base != data_lo); 1181 tcg_out_opc_ld_d(s, data_lo, base, 0); 1182 tcg_out_opc_ld_d(s, data_hi, base, 8); 1183 } else { 1184 tcg_out_opc_st_d(s, data_lo, base, 0); 1185 tcg_out_opc_st_d(s, data_hi, base, 8); 1186 } 1187 } 1188 1189 if (ldst) { 1190 ldst->type = TCG_TYPE_I128; 1191 ldst->datalo_reg = data_lo; 1192 ldst->datahi_reg = data_hi; 1193 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1194 } 1195} 1196 1197/* 1198 * Entry-points 1199 */ 1200 1201static const tcg_insn_unit *tb_ret_addr; 1202 1203static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1204{ 1205 /* Reuse the zeroing that exists for goto_ptr. */ 1206 if (a0 == 0) { 1207 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1208 } else { 1209 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1210 tcg_out_call_int(s, tb_ret_addr, true); 1211 } 1212} 1213 1214static void tcg_out_goto_tb(TCGContext *s, int which) 1215{ 1216 /* 1217 * Direct branch, or load indirect address, to be patched 1218 * by tb_target_set_jmp_target. Check indirect load offset 1219 * in range early, regardless of direct branch distance, 1220 * via assert within tcg_out_opc_pcaddu2i. 1221 */ 1222 uintptr_t i_addr = get_jmp_target_addr(s, which); 1223 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1224 1225 set_jmp_insn_offset(s, which); 1226 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1227 1228 /* Finish the load and indirect branch. */ 1229 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1230 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1231 set_jmp_reset_offset(s, which); 1232} 1233 1234void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1235 uintptr_t jmp_rx, uintptr_t jmp_rw) 1236{ 1237 uintptr_t d_addr = tb->jmp_target_addr[n]; 1238 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1239 tcg_insn_unit insn; 1240 1241 /* Either directly branch, or load slot address for indirect branch. */ 1242 if (d_disp == sextreg(d_disp, 0, 26)) { 1243 insn = encode_sd10k16_insn(OPC_B, d_disp); 1244 } else { 1245 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1246 intptr_t i_disp = i_addr - jmp_rx; 1247 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1248 } 1249 1250 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1251 flush_idcache_range(jmp_rx, jmp_rw, 4); 1252} 1253 1254static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1255 const TCGArg args[TCG_MAX_OP_ARGS], 1256 const int const_args[TCG_MAX_OP_ARGS]) 1257{ 1258 TCGArg a0 = args[0]; 1259 TCGArg a1 = args[1]; 1260 TCGArg a2 = args[2]; 1261 TCGArg a3 = args[3]; 1262 int c2 = const_args[2]; 1263 1264 switch (opc) { 1265 case INDEX_op_mb: 1266 tcg_out_mb(s, a0); 1267 break; 1268 1269 case INDEX_op_goto_ptr: 1270 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1271 break; 1272 1273 case INDEX_op_br: 1274 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1275 0); 1276 tcg_out_opc_b(s, 0); 1277 break; 1278 1279 case INDEX_op_brcond_i32: 1280 case INDEX_op_brcond_i64: 1281 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1282 break; 1283 1284 case INDEX_op_extrh_i64_i32: 1285 tcg_out_opc_srai_d(s, a0, a1, 32); 1286 break; 1287 1288 case INDEX_op_not_i32: 1289 case INDEX_op_not_i64: 1290 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1291 break; 1292 1293 case INDEX_op_nor_i32: 1294 case INDEX_op_nor_i64: 1295 if (c2) { 1296 tcg_out_opc_ori(s, a0, a1, a2); 1297 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1298 } else { 1299 tcg_out_opc_nor(s, a0, a1, a2); 1300 } 1301 break; 1302 1303 case INDEX_op_andc_i32: 1304 case INDEX_op_andc_i64: 1305 if (c2) { 1306 /* guaranteed to fit due to constraint */ 1307 tcg_out_opc_andi(s, a0, a1, ~a2); 1308 } else { 1309 tcg_out_opc_andn(s, a0, a1, a2); 1310 } 1311 break; 1312 1313 case INDEX_op_orc_i32: 1314 case INDEX_op_orc_i64: 1315 if (c2) { 1316 /* guaranteed to fit due to constraint */ 1317 tcg_out_opc_ori(s, a0, a1, ~a2); 1318 } else { 1319 tcg_out_opc_orn(s, a0, a1, a2); 1320 } 1321 break; 1322 1323 case INDEX_op_and_i32: 1324 case INDEX_op_and_i64: 1325 if (c2) { 1326 tcg_out_opc_andi(s, a0, a1, a2); 1327 } else { 1328 tcg_out_opc_and(s, a0, a1, a2); 1329 } 1330 break; 1331 1332 case INDEX_op_or_i32: 1333 case INDEX_op_or_i64: 1334 if (c2) { 1335 tcg_out_opc_ori(s, a0, a1, a2); 1336 } else { 1337 tcg_out_opc_or(s, a0, a1, a2); 1338 } 1339 break; 1340 1341 case INDEX_op_xor_i32: 1342 case INDEX_op_xor_i64: 1343 if (c2) { 1344 tcg_out_opc_xori(s, a0, a1, a2); 1345 } else { 1346 tcg_out_opc_xor(s, a0, a1, a2); 1347 } 1348 break; 1349 1350 case INDEX_op_extract_i32: 1351 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1352 break; 1353 case INDEX_op_extract_i64: 1354 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1355 break; 1356 1357 case INDEX_op_deposit_i32: 1358 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1359 break; 1360 case INDEX_op_deposit_i64: 1361 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1362 break; 1363 1364 case INDEX_op_bswap16_i32: 1365 case INDEX_op_bswap16_i64: 1366 tcg_out_opc_revb_2h(s, a0, a1); 1367 if (a2 & TCG_BSWAP_OS) { 1368 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1369 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1370 tcg_out_ext16u(s, a0, a0); 1371 } 1372 break; 1373 1374 case INDEX_op_bswap32_i32: 1375 /* All 32-bit values are computed sign-extended in the register. */ 1376 a2 = TCG_BSWAP_OS; 1377 /* fallthrough */ 1378 case INDEX_op_bswap32_i64: 1379 tcg_out_opc_revb_2w(s, a0, a1); 1380 if (a2 & TCG_BSWAP_OS) { 1381 tcg_out_ext32s(s, a0, a0); 1382 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1383 tcg_out_ext32u(s, a0, a0); 1384 } 1385 break; 1386 1387 case INDEX_op_bswap64_i64: 1388 tcg_out_opc_revb_d(s, a0, a1); 1389 break; 1390 1391 case INDEX_op_clz_i32: 1392 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1393 break; 1394 case INDEX_op_clz_i64: 1395 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1396 break; 1397 1398 case INDEX_op_ctz_i32: 1399 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1400 break; 1401 case INDEX_op_ctz_i64: 1402 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1403 break; 1404 1405 case INDEX_op_shl_i32: 1406 if (c2) { 1407 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1408 } else { 1409 tcg_out_opc_sll_w(s, a0, a1, a2); 1410 } 1411 break; 1412 case INDEX_op_shl_i64: 1413 if (c2) { 1414 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1415 } else { 1416 tcg_out_opc_sll_d(s, a0, a1, a2); 1417 } 1418 break; 1419 1420 case INDEX_op_shr_i32: 1421 if (c2) { 1422 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1423 } else { 1424 tcg_out_opc_srl_w(s, a0, a1, a2); 1425 } 1426 break; 1427 case INDEX_op_shr_i64: 1428 if (c2) { 1429 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1430 } else { 1431 tcg_out_opc_srl_d(s, a0, a1, a2); 1432 } 1433 break; 1434 1435 case INDEX_op_sar_i32: 1436 if (c2) { 1437 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1438 } else { 1439 tcg_out_opc_sra_w(s, a0, a1, a2); 1440 } 1441 break; 1442 case INDEX_op_sar_i64: 1443 if (c2) { 1444 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1445 } else { 1446 tcg_out_opc_sra_d(s, a0, a1, a2); 1447 } 1448 break; 1449 1450 case INDEX_op_rotl_i32: 1451 /* transform into equivalent rotr/rotri */ 1452 if (c2) { 1453 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1454 } else { 1455 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1456 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1457 } 1458 break; 1459 case INDEX_op_rotl_i64: 1460 /* transform into equivalent rotr/rotri */ 1461 if (c2) { 1462 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1463 } else { 1464 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1465 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1466 } 1467 break; 1468 1469 case INDEX_op_rotr_i32: 1470 if (c2) { 1471 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1472 } else { 1473 tcg_out_opc_rotr_w(s, a0, a1, a2); 1474 } 1475 break; 1476 case INDEX_op_rotr_i64: 1477 if (c2) { 1478 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1479 } else { 1480 tcg_out_opc_rotr_d(s, a0, a1, a2); 1481 } 1482 break; 1483 1484 case INDEX_op_add_i32: 1485 if (c2) { 1486 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); 1487 } else { 1488 tcg_out_opc_add_w(s, a0, a1, a2); 1489 } 1490 break; 1491 case INDEX_op_add_i64: 1492 if (c2) { 1493 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); 1494 } else { 1495 tcg_out_opc_add_d(s, a0, a1, a2); 1496 } 1497 break; 1498 1499 case INDEX_op_sub_i32: 1500 if (c2) { 1501 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); 1502 } else { 1503 tcg_out_opc_sub_w(s, a0, a1, a2); 1504 } 1505 break; 1506 case INDEX_op_sub_i64: 1507 if (c2) { 1508 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); 1509 } else { 1510 tcg_out_opc_sub_d(s, a0, a1, a2); 1511 } 1512 break; 1513 1514 case INDEX_op_neg_i32: 1515 tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); 1516 break; 1517 case INDEX_op_neg_i64: 1518 tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); 1519 break; 1520 1521 case INDEX_op_mul_i32: 1522 tcg_out_opc_mul_w(s, a0, a1, a2); 1523 break; 1524 case INDEX_op_mul_i64: 1525 tcg_out_opc_mul_d(s, a0, a1, a2); 1526 break; 1527 1528 case INDEX_op_mulsh_i32: 1529 tcg_out_opc_mulh_w(s, a0, a1, a2); 1530 break; 1531 case INDEX_op_mulsh_i64: 1532 tcg_out_opc_mulh_d(s, a0, a1, a2); 1533 break; 1534 1535 case INDEX_op_muluh_i32: 1536 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1537 break; 1538 case INDEX_op_muluh_i64: 1539 tcg_out_opc_mulh_du(s, a0, a1, a2); 1540 break; 1541 1542 case INDEX_op_div_i32: 1543 tcg_out_opc_div_w(s, a0, a1, a2); 1544 break; 1545 case INDEX_op_div_i64: 1546 tcg_out_opc_div_d(s, a0, a1, a2); 1547 break; 1548 1549 case INDEX_op_divu_i32: 1550 tcg_out_opc_div_wu(s, a0, a1, a2); 1551 break; 1552 case INDEX_op_divu_i64: 1553 tcg_out_opc_div_du(s, a0, a1, a2); 1554 break; 1555 1556 case INDEX_op_rem_i32: 1557 tcg_out_opc_mod_w(s, a0, a1, a2); 1558 break; 1559 case INDEX_op_rem_i64: 1560 tcg_out_opc_mod_d(s, a0, a1, a2); 1561 break; 1562 1563 case INDEX_op_remu_i32: 1564 tcg_out_opc_mod_wu(s, a0, a1, a2); 1565 break; 1566 case INDEX_op_remu_i64: 1567 tcg_out_opc_mod_du(s, a0, a1, a2); 1568 break; 1569 1570 case INDEX_op_setcond_i32: 1571 case INDEX_op_setcond_i64: 1572 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1573 break; 1574 1575 case INDEX_op_movcond_i32: 1576 case INDEX_op_movcond_i64: 1577 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1578 break; 1579 1580 case INDEX_op_ld8s_i32: 1581 case INDEX_op_ld8s_i64: 1582 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1583 break; 1584 case INDEX_op_ld8u_i32: 1585 case INDEX_op_ld8u_i64: 1586 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1587 break; 1588 case INDEX_op_ld16s_i32: 1589 case INDEX_op_ld16s_i64: 1590 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1591 break; 1592 case INDEX_op_ld16u_i32: 1593 case INDEX_op_ld16u_i64: 1594 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1595 break; 1596 case INDEX_op_ld_i32: 1597 case INDEX_op_ld32s_i64: 1598 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1599 break; 1600 case INDEX_op_ld32u_i64: 1601 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1602 break; 1603 case INDEX_op_ld_i64: 1604 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1605 break; 1606 1607 case INDEX_op_st8_i32: 1608 case INDEX_op_st8_i64: 1609 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1610 break; 1611 case INDEX_op_st16_i32: 1612 case INDEX_op_st16_i64: 1613 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1614 break; 1615 case INDEX_op_st_i32: 1616 case INDEX_op_st32_i64: 1617 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1618 break; 1619 case INDEX_op_st_i64: 1620 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1621 break; 1622 1623 case INDEX_op_qemu_ld_a32_i32: 1624 case INDEX_op_qemu_ld_a64_i32: 1625 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1626 break; 1627 case INDEX_op_qemu_ld_a32_i64: 1628 case INDEX_op_qemu_ld_a64_i64: 1629 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1630 break; 1631 case INDEX_op_qemu_ld_a32_i128: 1632 case INDEX_op_qemu_ld_a64_i128: 1633 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1634 break; 1635 case INDEX_op_qemu_st_a32_i32: 1636 case INDEX_op_qemu_st_a64_i32: 1637 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1638 break; 1639 case INDEX_op_qemu_st_a32_i64: 1640 case INDEX_op_qemu_st_a64_i64: 1641 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1642 break; 1643 case INDEX_op_qemu_st_a32_i128: 1644 case INDEX_op_qemu_st_a64_i128: 1645 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1646 break; 1647 1648 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1649 case INDEX_op_mov_i64: 1650 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1651 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1652 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1653 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1654 case INDEX_op_ext8s_i64: 1655 case INDEX_op_ext8u_i32: 1656 case INDEX_op_ext8u_i64: 1657 case INDEX_op_ext16s_i32: 1658 case INDEX_op_ext16s_i64: 1659 case INDEX_op_ext16u_i32: 1660 case INDEX_op_ext16u_i64: 1661 case INDEX_op_ext32s_i64: 1662 case INDEX_op_ext32u_i64: 1663 case INDEX_op_ext_i32_i64: 1664 case INDEX_op_extu_i32_i64: 1665 case INDEX_op_extrl_i64_i32: 1666 default: 1667 g_assert_not_reached(); 1668 } 1669} 1670 1671static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1672 TCGReg rd, TCGReg rs) 1673{ 1674 switch (vece) { 1675 case MO_8: 1676 tcg_out_opc_vreplgr2vr_b(s, rd, rs); 1677 break; 1678 case MO_16: 1679 tcg_out_opc_vreplgr2vr_h(s, rd, rs); 1680 break; 1681 case MO_32: 1682 tcg_out_opc_vreplgr2vr_w(s, rd, rs); 1683 break; 1684 case MO_64: 1685 tcg_out_opc_vreplgr2vr_d(s, rd, rs); 1686 break; 1687 default: 1688 g_assert_not_reached(); 1689 } 1690 return true; 1691} 1692 1693static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1694 TCGReg r, TCGReg base, intptr_t offset) 1695{ 1696 /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */ 1697 if (offset < -0x800 || offset > 0x7ff || \ 1698 (offset & ((1 << vece) - 1)) != 0) { 1699 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1700 base = TCG_REG_TMP0; 1701 offset = 0; 1702 } 1703 offset >>= vece; 1704 1705 switch (vece) { 1706 case MO_8: 1707 tcg_out_opc_vldrepl_b(s, r, base, offset); 1708 break; 1709 case MO_16: 1710 tcg_out_opc_vldrepl_h(s, r, base, offset); 1711 break; 1712 case MO_32: 1713 tcg_out_opc_vldrepl_w(s, r, base, offset); 1714 break; 1715 case MO_64: 1716 tcg_out_opc_vldrepl_d(s, r, base, offset); 1717 break; 1718 default: 1719 g_assert_not_reached(); 1720 } 1721 return true; 1722} 1723 1724static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1725 TCGReg rd, int64_t v64) 1726{ 1727 /* Try vldi if imm can fit */ 1728 int64_t value = sextract64(v64, 0, 8 << vece); 1729 if (-0x200 <= value && value <= 0x1FF) { 1730 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 1731 tcg_out_opc_vldi(s, rd, imm); 1732 return; 1733 } 1734 1735 /* TODO: vldi patterns when imm 12 is set */ 1736 1737 /* Fallback to vreplgr2vr */ 1738 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 1739 switch (vece) { 1740 case MO_8: 1741 tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0); 1742 break; 1743 case MO_16: 1744 tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0); 1745 break; 1746 case MO_32: 1747 tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0); 1748 break; 1749 case MO_64: 1750 tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0); 1751 break; 1752 default: 1753 g_assert_not_reached(); 1754 } 1755} 1756 1757static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0, 1758 const TCGArg a1, const TCGArg a2, 1759 bool a2_is_const, bool is_add) 1760{ 1761 static const LoongArchInsn add_vec_insn[4] = { 1762 OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D 1763 }; 1764 static const LoongArchInsn add_vec_imm_insn[4] = { 1765 OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU 1766 }; 1767 static const LoongArchInsn sub_vec_insn[4] = { 1768 OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D 1769 }; 1770 static const LoongArchInsn sub_vec_imm_insn[4] = { 1771 OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU 1772 }; 1773 1774 if (a2_is_const) { 1775 int64_t value = sextract64(a2, 0, 8 << vece); 1776 if (!is_add) { 1777 value = -value; 1778 } 1779 1780 /* Try vaddi/vsubi */ 1781 if (0 <= value && value <= 0x1f) { 1782 tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \ 1783 a1, value)); 1784 return; 1785 } else if (-0x1f <= value && value < 0) { 1786 tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \ 1787 a1, -value)); 1788 return; 1789 } 1790 1791 /* constraint TCG_CT_CONST_VADD ensures unreachable */ 1792 g_assert_not_reached(); 1793 } 1794 1795 if (is_add) { 1796 tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2)); 1797 } else { 1798 tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2)); 1799 } 1800} 1801 1802static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 1803 unsigned vecl, unsigned vece, 1804 const TCGArg args[TCG_MAX_OP_ARGS], 1805 const int const_args[TCG_MAX_OP_ARGS]) 1806{ 1807 TCGType type = vecl + TCG_TYPE_V64; 1808 TCGArg a0, a1, a2, a3; 1809 TCGReg temp_vec = TCG_VEC_TMP0; 1810 1811 static const LoongArchInsn cmp_vec_insn[16][4] = { 1812 [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D}, 1813 [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D}, 1814 [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU}, 1815 [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D}, 1816 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU}, 1817 }; 1818 static const LoongArchInsn cmp_vec_imm_insn[16][4] = { 1819 [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D}, 1820 [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D}, 1821 [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU}, 1822 [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D}, 1823 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU}, 1824 }; 1825 LoongArchInsn insn; 1826 static const LoongArchInsn neg_vec_insn[4] = { 1827 OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D 1828 }; 1829 static const LoongArchInsn mul_vec_insn[4] = { 1830 OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D 1831 }; 1832 static const LoongArchInsn smin_vec_insn[4] = { 1833 OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D 1834 }; 1835 static const LoongArchInsn umin_vec_insn[4] = { 1836 OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU 1837 }; 1838 static const LoongArchInsn smax_vec_insn[4] = { 1839 OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D 1840 }; 1841 static const LoongArchInsn umax_vec_insn[4] = { 1842 OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU 1843 }; 1844 static const LoongArchInsn ssadd_vec_insn[4] = { 1845 OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D 1846 }; 1847 static const LoongArchInsn usadd_vec_insn[4] = { 1848 OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU 1849 }; 1850 static const LoongArchInsn sssub_vec_insn[4] = { 1851 OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D 1852 }; 1853 static const LoongArchInsn ussub_vec_insn[4] = { 1854 OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU 1855 }; 1856 static const LoongArchInsn shlv_vec_insn[4] = { 1857 OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D 1858 }; 1859 static const LoongArchInsn shrv_vec_insn[4] = { 1860 OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D 1861 }; 1862 static const LoongArchInsn sarv_vec_insn[4] = { 1863 OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D 1864 }; 1865 static const LoongArchInsn shli_vec_insn[4] = { 1866 OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D 1867 }; 1868 static const LoongArchInsn shri_vec_insn[4] = { 1869 OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D 1870 }; 1871 static const LoongArchInsn sari_vec_insn[4] = { 1872 OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D 1873 }; 1874 static const LoongArchInsn rotrv_vec_insn[4] = { 1875 OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D 1876 }; 1877 1878 a0 = args[0]; 1879 a1 = args[1]; 1880 a2 = args[2]; 1881 a3 = args[3]; 1882 1883 /* Currently only supports V128 */ 1884 tcg_debug_assert(type == TCG_TYPE_V128); 1885 1886 switch (opc) { 1887 case INDEX_op_st_vec: 1888 tcg_out_st(s, type, a0, a1, a2); 1889 break; 1890 case INDEX_op_ld_vec: 1891 tcg_out_ld(s, type, a0, a1, a2); 1892 break; 1893 case INDEX_op_and_vec: 1894 tcg_out_opc_vand_v(s, a0, a1, a2); 1895 break; 1896 case INDEX_op_andc_vec: 1897 /* 1898 * vandn vd, vj, vk: vd = vk & ~vj 1899 * andc_vec vd, vj, vk: vd = vj & ~vk 1900 * vk and vk are swapped 1901 */ 1902 tcg_out_opc_vandn_v(s, a0, a2, a1); 1903 break; 1904 case INDEX_op_or_vec: 1905 tcg_out_opc_vor_v(s, a0, a1, a2); 1906 break; 1907 case INDEX_op_orc_vec: 1908 tcg_out_opc_vorn_v(s, a0, a1, a2); 1909 break; 1910 case INDEX_op_xor_vec: 1911 tcg_out_opc_vxor_v(s, a0, a1, a2); 1912 break; 1913 case INDEX_op_nor_vec: 1914 tcg_out_opc_vnor_v(s, a0, a1, a2); 1915 break; 1916 case INDEX_op_not_vec: 1917 tcg_out_opc_vnor_v(s, a0, a1, a1); 1918 break; 1919 case INDEX_op_cmp_vec: 1920 { 1921 TCGCond cond = args[3]; 1922 if (const_args[2]) { 1923 /* 1924 * cmp_vec dest, src, value 1925 * Try vseqi/vslei/vslti 1926 */ 1927 int64_t value = sextract64(a2, 0, 8 << vece); 1928 if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \ 1929 cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) { 1930 tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \ 1931 a0, a1, value)); 1932 break; 1933 } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) && 1934 (0x00 <= value && value <= 0x1f)) { 1935 tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \ 1936 a0, a1, value)); 1937 break; 1938 } 1939 1940 /* 1941 * Fallback to: 1942 * dupi_vec temp, a2 1943 * cmp_vec a0, a1, temp, cond 1944 */ 1945 tcg_out_dupi_vec(s, type, vece, temp_vec, a2); 1946 a2 = temp_vec; 1947 } 1948 1949 insn = cmp_vec_insn[cond][vece]; 1950 if (insn == 0) { 1951 TCGArg t; 1952 t = a1, a1 = a2, a2 = t; 1953 cond = tcg_swap_cond(cond); 1954 insn = cmp_vec_insn[cond][vece]; 1955 tcg_debug_assert(insn != 0); 1956 } 1957 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 1958 } 1959 break; 1960 case INDEX_op_add_vec: 1961 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true); 1962 break; 1963 case INDEX_op_sub_vec: 1964 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false); 1965 break; 1966 case INDEX_op_neg_vec: 1967 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1)); 1968 break; 1969 case INDEX_op_mul_vec: 1970 tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2)); 1971 break; 1972 case INDEX_op_smin_vec: 1973 tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2)); 1974 break; 1975 case INDEX_op_smax_vec: 1976 tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2)); 1977 break; 1978 case INDEX_op_umin_vec: 1979 tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2)); 1980 break; 1981 case INDEX_op_umax_vec: 1982 tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2)); 1983 break; 1984 case INDEX_op_ssadd_vec: 1985 tcg_out32(s, encode_vdvjvk_insn(ssadd_vec_insn[vece], a0, a1, a2)); 1986 break; 1987 case INDEX_op_usadd_vec: 1988 tcg_out32(s, encode_vdvjvk_insn(usadd_vec_insn[vece], a0, a1, a2)); 1989 break; 1990 case INDEX_op_sssub_vec: 1991 tcg_out32(s, encode_vdvjvk_insn(sssub_vec_insn[vece], a0, a1, a2)); 1992 break; 1993 case INDEX_op_ussub_vec: 1994 tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2)); 1995 break; 1996 case INDEX_op_shlv_vec: 1997 tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2)); 1998 break; 1999 case INDEX_op_shrv_vec: 2000 tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2)); 2001 break; 2002 case INDEX_op_sarv_vec: 2003 tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2)); 2004 break; 2005 case INDEX_op_shli_vec: 2006 tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2)); 2007 break; 2008 case INDEX_op_shri_vec: 2009 tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2)); 2010 break; 2011 case INDEX_op_sari_vec: 2012 tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2)); 2013 break; 2014 case INDEX_op_rotrv_vec: 2015 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2)); 2016 break; 2017 case INDEX_op_rotlv_vec: 2018 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2019 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2)); 2020 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, 2021 temp_vec)); 2022 break; 2023 case INDEX_op_rotli_vec: 2024 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2025 a2 = extract32(-a2, 0, 3 + vece); 2026 switch (vece) { 2027 case MO_8: 2028 tcg_out_opc_vrotri_b(s, a0, a1, a2); 2029 break; 2030 case MO_16: 2031 tcg_out_opc_vrotri_h(s, a0, a1, a2); 2032 break; 2033 case MO_32: 2034 tcg_out_opc_vrotri_w(s, a0, a1, a2); 2035 break; 2036 case MO_64: 2037 tcg_out_opc_vrotri_d(s, a0, a1, a2); 2038 break; 2039 default: 2040 g_assert_not_reached(); 2041 } 2042 break; 2043 case INDEX_op_bitsel_vec: 2044 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2045 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2046 break; 2047 case INDEX_op_dupm_vec: 2048 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2049 break; 2050 default: 2051 g_assert_not_reached(); 2052 } 2053} 2054 2055int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2056{ 2057 switch (opc) { 2058 case INDEX_op_ld_vec: 2059 case INDEX_op_st_vec: 2060 case INDEX_op_dup_vec: 2061 case INDEX_op_dupm_vec: 2062 case INDEX_op_cmp_vec: 2063 case INDEX_op_add_vec: 2064 case INDEX_op_sub_vec: 2065 case INDEX_op_and_vec: 2066 case INDEX_op_andc_vec: 2067 case INDEX_op_or_vec: 2068 case INDEX_op_orc_vec: 2069 case INDEX_op_xor_vec: 2070 case INDEX_op_nor_vec: 2071 case INDEX_op_not_vec: 2072 case INDEX_op_neg_vec: 2073 case INDEX_op_mul_vec: 2074 case INDEX_op_smin_vec: 2075 case INDEX_op_smax_vec: 2076 case INDEX_op_umin_vec: 2077 case INDEX_op_umax_vec: 2078 case INDEX_op_ssadd_vec: 2079 case INDEX_op_usadd_vec: 2080 case INDEX_op_sssub_vec: 2081 case INDEX_op_ussub_vec: 2082 case INDEX_op_shlv_vec: 2083 case INDEX_op_shrv_vec: 2084 case INDEX_op_sarv_vec: 2085 case INDEX_op_bitsel_vec: 2086 return 1; 2087 default: 2088 return 0; 2089 } 2090} 2091 2092void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2093 TCGArg a0, ...) 2094{ 2095 g_assert_not_reached(); 2096} 2097 2098static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2099{ 2100 switch (op) { 2101 case INDEX_op_goto_ptr: 2102 return C_O0_I1(r); 2103 2104 case INDEX_op_st8_i32: 2105 case INDEX_op_st8_i64: 2106 case INDEX_op_st16_i32: 2107 case INDEX_op_st16_i64: 2108 case INDEX_op_st32_i64: 2109 case INDEX_op_st_i32: 2110 case INDEX_op_st_i64: 2111 case INDEX_op_qemu_st_a32_i32: 2112 case INDEX_op_qemu_st_a64_i32: 2113 case INDEX_op_qemu_st_a32_i64: 2114 case INDEX_op_qemu_st_a64_i64: 2115 return C_O0_I2(rZ, r); 2116 2117 case INDEX_op_qemu_ld_a32_i128: 2118 case INDEX_op_qemu_ld_a64_i128: 2119 return C_N2_I1(r, r, r); 2120 2121 case INDEX_op_qemu_st_a32_i128: 2122 case INDEX_op_qemu_st_a64_i128: 2123 return C_O0_I3(r, r, r); 2124 2125 case INDEX_op_brcond_i32: 2126 case INDEX_op_brcond_i64: 2127 return C_O0_I2(rZ, rZ); 2128 2129 case INDEX_op_ext8s_i32: 2130 case INDEX_op_ext8s_i64: 2131 case INDEX_op_ext8u_i32: 2132 case INDEX_op_ext8u_i64: 2133 case INDEX_op_ext16s_i32: 2134 case INDEX_op_ext16s_i64: 2135 case INDEX_op_ext16u_i32: 2136 case INDEX_op_ext16u_i64: 2137 case INDEX_op_ext32s_i64: 2138 case INDEX_op_ext32u_i64: 2139 case INDEX_op_extu_i32_i64: 2140 case INDEX_op_extrl_i64_i32: 2141 case INDEX_op_extrh_i64_i32: 2142 case INDEX_op_ext_i32_i64: 2143 case INDEX_op_neg_i32: 2144 case INDEX_op_neg_i64: 2145 case INDEX_op_not_i32: 2146 case INDEX_op_not_i64: 2147 case INDEX_op_extract_i32: 2148 case INDEX_op_extract_i64: 2149 case INDEX_op_bswap16_i32: 2150 case INDEX_op_bswap16_i64: 2151 case INDEX_op_bswap32_i32: 2152 case INDEX_op_bswap32_i64: 2153 case INDEX_op_bswap64_i64: 2154 case INDEX_op_ld8s_i32: 2155 case INDEX_op_ld8s_i64: 2156 case INDEX_op_ld8u_i32: 2157 case INDEX_op_ld8u_i64: 2158 case INDEX_op_ld16s_i32: 2159 case INDEX_op_ld16s_i64: 2160 case INDEX_op_ld16u_i32: 2161 case INDEX_op_ld16u_i64: 2162 case INDEX_op_ld32s_i64: 2163 case INDEX_op_ld32u_i64: 2164 case INDEX_op_ld_i32: 2165 case INDEX_op_ld_i64: 2166 case INDEX_op_qemu_ld_a32_i32: 2167 case INDEX_op_qemu_ld_a64_i32: 2168 case INDEX_op_qemu_ld_a32_i64: 2169 case INDEX_op_qemu_ld_a64_i64: 2170 return C_O1_I1(r, r); 2171 2172 case INDEX_op_andc_i32: 2173 case INDEX_op_andc_i64: 2174 case INDEX_op_orc_i32: 2175 case INDEX_op_orc_i64: 2176 /* 2177 * LoongArch insns for these ops don't have reg-imm forms, but we 2178 * can express using andi/ori if ~constant satisfies 2179 * TCG_CT_CONST_U12. 2180 */ 2181 return C_O1_I2(r, r, rC); 2182 2183 case INDEX_op_shl_i32: 2184 case INDEX_op_shl_i64: 2185 case INDEX_op_shr_i32: 2186 case INDEX_op_shr_i64: 2187 case INDEX_op_sar_i32: 2188 case INDEX_op_sar_i64: 2189 case INDEX_op_rotl_i32: 2190 case INDEX_op_rotl_i64: 2191 case INDEX_op_rotr_i32: 2192 case INDEX_op_rotr_i64: 2193 return C_O1_I2(r, r, ri); 2194 2195 case INDEX_op_add_i32: 2196 return C_O1_I2(r, r, ri); 2197 case INDEX_op_add_i64: 2198 return C_O1_I2(r, r, rJ); 2199 2200 case INDEX_op_and_i32: 2201 case INDEX_op_and_i64: 2202 case INDEX_op_nor_i32: 2203 case INDEX_op_nor_i64: 2204 case INDEX_op_or_i32: 2205 case INDEX_op_or_i64: 2206 case INDEX_op_xor_i32: 2207 case INDEX_op_xor_i64: 2208 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 2209 return C_O1_I2(r, r, rU); 2210 2211 case INDEX_op_clz_i32: 2212 case INDEX_op_clz_i64: 2213 case INDEX_op_ctz_i32: 2214 case INDEX_op_ctz_i64: 2215 return C_O1_I2(r, r, rW); 2216 2217 case INDEX_op_deposit_i32: 2218 case INDEX_op_deposit_i64: 2219 /* Must deposit into the same register as input */ 2220 return C_O1_I2(r, 0, rZ); 2221 2222 case INDEX_op_sub_i32: 2223 case INDEX_op_setcond_i32: 2224 return C_O1_I2(r, rZ, ri); 2225 case INDEX_op_sub_i64: 2226 case INDEX_op_setcond_i64: 2227 return C_O1_I2(r, rZ, rJ); 2228 2229 case INDEX_op_mul_i32: 2230 case INDEX_op_mul_i64: 2231 case INDEX_op_mulsh_i32: 2232 case INDEX_op_mulsh_i64: 2233 case INDEX_op_muluh_i32: 2234 case INDEX_op_muluh_i64: 2235 case INDEX_op_div_i32: 2236 case INDEX_op_div_i64: 2237 case INDEX_op_divu_i32: 2238 case INDEX_op_divu_i64: 2239 case INDEX_op_rem_i32: 2240 case INDEX_op_rem_i64: 2241 case INDEX_op_remu_i32: 2242 case INDEX_op_remu_i64: 2243 return C_O1_I2(r, rZ, rZ); 2244 2245 case INDEX_op_movcond_i32: 2246 case INDEX_op_movcond_i64: 2247 return C_O1_I4(r, rZ, rJ, rZ, rZ); 2248 2249 case INDEX_op_ld_vec: 2250 case INDEX_op_dupm_vec: 2251 case INDEX_op_dup_vec: 2252 return C_O1_I1(w, r); 2253 2254 case INDEX_op_st_vec: 2255 return C_O0_I2(w, r); 2256 2257 case INDEX_op_cmp_vec: 2258 return C_O1_I2(w, w, wM); 2259 2260 case INDEX_op_add_vec: 2261 case INDEX_op_sub_vec: 2262 return C_O1_I2(w, w, wA); 2263 2264 case INDEX_op_and_vec: 2265 case INDEX_op_andc_vec: 2266 case INDEX_op_or_vec: 2267 case INDEX_op_orc_vec: 2268 case INDEX_op_xor_vec: 2269 case INDEX_op_nor_vec: 2270 case INDEX_op_mul_vec: 2271 case INDEX_op_smin_vec: 2272 case INDEX_op_smax_vec: 2273 case INDEX_op_umin_vec: 2274 case INDEX_op_umax_vec: 2275 case INDEX_op_ssadd_vec: 2276 case INDEX_op_usadd_vec: 2277 case INDEX_op_sssub_vec: 2278 case INDEX_op_ussub_vec: 2279 case INDEX_op_shlv_vec: 2280 case INDEX_op_shrv_vec: 2281 case INDEX_op_sarv_vec: 2282 case INDEX_op_rotrv_vec: 2283 case INDEX_op_rotlv_vec: 2284 return C_O1_I2(w, w, w); 2285 2286 case INDEX_op_not_vec: 2287 case INDEX_op_neg_vec: 2288 case INDEX_op_shli_vec: 2289 case INDEX_op_shri_vec: 2290 case INDEX_op_sari_vec: 2291 case INDEX_op_rotli_vec: 2292 return C_O1_I1(w, w); 2293 2294 case INDEX_op_bitsel_vec: 2295 return C_O1_I3(w, w, w, w); 2296 2297 default: 2298 g_assert_not_reached(); 2299 } 2300} 2301 2302static const int tcg_target_callee_save_regs[] = { 2303 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2304 TCG_REG_S1, 2305 TCG_REG_S2, 2306 TCG_REG_S3, 2307 TCG_REG_S4, 2308 TCG_REG_S5, 2309 TCG_REG_S6, 2310 TCG_REG_S7, 2311 TCG_REG_S8, 2312 TCG_REG_S9, 2313 TCG_REG_RA, /* should be last for ABI compliance */ 2314}; 2315 2316/* Stack frame parameters. */ 2317#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2318#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2319#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2320#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2321 + TCG_TARGET_STACK_ALIGN - 1) \ 2322 & -TCG_TARGET_STACK_ALIGN) 2323#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2324 2325/* We're expecting to be able to use an immediate for frame allocation. */ 2326QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2327 2328/* Generate global QEMU prologue and epilogue code */ 2329static void tcg_target_qemu_prologue(TCGContext *s) 2330{ 2331 int i; 2332 2333 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2334 2335 /* TB prologue */ 2336 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2337 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2338 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2339 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2340 } 2341 2342 if (!tcg_use_softmmu && guest_base) { 2343 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2344 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2345 } 2346 2347 /* Call generated code */ 2348 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2349 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2350 2351 /* Return path for goto_ptr. Set return value to 0 */ 2352 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2353 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2354 2355 /* TB epilogue */ 2356 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2357 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2358 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2359 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2360 } 2361 2362 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2363 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2364} 2365 2366static void tcg_out_tb_start(TCGContext *s) 2367{ 2368 /* nothing to do */ 2369} 2370 2371static void tcg_target_init(TCGContext *s) 2372{ 2373 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2374 2375 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2376 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2377 error_report("TCG: unaligned access support required; exiting"); 2378 exit(EXIT_FAILURE); 2379 } 2380 2381 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2382 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2383 2384 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2385 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2386 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2387 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2388 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2389 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2390 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2391 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2392 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2393 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2394 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2395 2396 if (cpuinfo & CPUINFO_LSX) { 2397 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2398 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2399 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2400 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2401 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2402 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2403 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2404 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2405 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2406 } 2407 2408 s->reserved_regs = 0; 2409 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2410 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2411 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2412 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2413 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2414 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2415 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2416 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2417} 2418 2419typedef struct { 2420 DebugFrameHeader h; 2421 uint8_t fde_def_cfa[4]; 2422 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2423} DebugFrame; 2424 2425#define ELF_HOST_MACHINE EM_LOONGARCH 2426 2427static const DebugFrame debug_frame = { 2428 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2429 .h.cie.id = -1, 2430 .h.cie.version = 1, 2431 .h.cie.code_align = 1, 2432 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2433 .h.cie.return_column = TCG_REG_RA, 2434 2435 /* Total FDE size does not include the "len" member. */ 2436 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2437 2438 .fde_def_cfa = { 2439 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2440 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2441 (FRAME_SIZE >> 7) 2442 }, 2443 .fde_reg_ofs = { 2444 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2445 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2446 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2447 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2448 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2449 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2450 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2451 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2452 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2453 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2454 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2455 } 2456}; 2457 2458void tcg_register_jit(const void *buf, size_t buf_size) 2459{ 2460 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2461} 2462