1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth SPARC translation 3fcf5ef2aSThomas Huth 4fcf5ef2aSThomas Huth Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> 5fcf5ef2aSThomas Huth Copyright (C) 2003-2005 Fabrice Bellard 6fcf5ef2aSThomas Huth 7fcf5ef2aSThomas Huth This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth License as published by the Free Software Foundation; either 105650b549SChetan Pant version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth Lesser General Public License for more details. 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth 23fcf5ef2aSThomas Huth #include "cpu.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 26fcf5ef2aSThomas Huth #include "exec/exec-all.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 28fcf5ef2aSThomas Huth 29fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 30fcf5ef2aSThomas Huth 31c5e6ccdfSEmilio G. Cota #include "exec/translator.h" 32fcf5ef2aSThomas Huth #include "exec/log.h" 33fcf5ef2aSThomas Huth #include "asi.h" 34fcf5ef2aSThomas Huth 35d53106c9SRichard Henderson #define HELPER_H "helper.h" 36d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 37d53106c9SRichard Henderson #undef HELPER_H 38fcf5ef2aSThomas Huth 39633c4283SRichard Henderson /* Dynamic PC, must exit to main loop. */ 40633c4283SRichard Henderson #define DYNAMIC_PC 1 41633c4283SRichard Henderson /* Dynamic PC, one of two values according to jump_pc[T2]. */ 42633c4283SRichard Henderson #define JUMP_PC 2 43633c4283SRichard Henderson /* Dynamic PC, may lookup next TB. */ 44633c4283SRichard Henderson #define DYNAMIC_PC_LOOKUP 3 45fcf5ef2aSThomas Huth 4646bb0137SMark Cave-Ayland #define DISAS_EXIT DISAS_TARGET_0 4746bb0137SMark Cave-Ayland 48fcf5ef2aSThomas Huth /* global register indexes */ 49fcf5ef2aSThomas Huth static TCGv_ptr cpu_regwptr; 50fcf5ef2aSThomas Huth static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; 51fcf5ef2aSThomas Huth static TCGv_i32 cpu_cc_op; 52fcf5ef2aSThomas Huth static TCGv_i32 cpu_psr; 53fcf5ef2aSThomas Huth static TCGv cpu_fsr, cpu_pc, cpu_npc; 54fcf5ef2aSThomas Huth static TCGv cpu_regs[32]; 55fcf5ef2aSThomas Huth static TCGv cpu_y; 56fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 57fcf5ef2aSThomas Huth static TCGv cpu_tbr; 58fcf5ef2aSThomas Huth #endif 59fcf5ef2aSThomas Huth static TCGv cpu_cond; 60fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 61fcf5ef2aSThomas Huth static TCGv_i32 cpu_xcc, cpu_fprs; 62fcf5ef2aSThomas Huth static TCGv cpu_gsr; 63fcf5ef2aSThomas Huth static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; 64fcf5ef2aSThomas Huth static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; 65fcf5ef2aSThomas Huth #else 66fcf5ef2aSThomas Huth static TCGv cpu_wim; 67fcf5ef2aSThomas Huth #endif 68fcf5ef2aSThomas Huth /* Floating point registers */ 69fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[TARGET_DPREGS]; 70fcf5ef2aSThomas Huth 71186e7890SRichard Henderson typedef struct DisasDelayException { 72186e7890SRichard Henderson struct DisasDelayException *next; 73186e7890SRichard Henderson TCGLabel *lab; 74186e7890SRichard Henderson TCGv_i32 excp; 75186e7890SRichard Henderson /* Saved state at parent insn. */ 76186e7890SRichard Henderson target_ulong pc; 77186e7890SRichard Henderson target_ulong npc; 78186e7890SRichard Henderson } DisasDelayException; 79186e7890SRichard Henderson 80fcf5ef2aSThomas Huth typedef struct DisasContext { 81af00be49SEmilio G. Cota DisasContextBase base; 82fcf5ef2aSThomas Huth target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ 83fcf5ef2aSThomas Huth target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ 84fcf5ef2aSThomas Huth target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ 85fcf5ef2aSThomas Huth int mem_idx; 86c9b459aaSArtyom Tarasenko bool fpu_enabled; 87c9b459aaSArtyom Tarasenko bool address_mask_32bit; 88c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY 89c9b459aaSArtyom Tarasenko bool supervisor; 90c9b459aaSArtyom Tarasenko #ifdef TARGET_SPARC64 91c9b459aaSArtyom Tarasenko bool hypervisor; 92c9b459aaSArtyom Tarasenko #endif 93c9b459aaSArtyom Tarasenko #endif 94c9b459aaSArtyom Tarasenko 95fcf5ef2aSThomas Huth uint32_t cc_op; /* current CC operation */ 96fcf5ef2aSThomas Huth sparc_def_t *def; 97fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 98fcf5ef2aSThomas Huth int fprs_dirty; 99fcf5ef2aSThomas Huth int asi; 100fcf5ef2aSThomas Huth #endif 101186e7890SRichard Henderson DisasDelayException *delay_excp_list; 102fcf5ef2aSThomas Huth } DisasContext; 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth typedef struct { 105fcf5ef2aSThomas Huth TCGCond cond; 106fcf5ef2aSThomas Huth bool is_bool; 107fcf5ef2aSThomas Huth TCGv c1, c2; 108fcf5ef2aSThomas Huth } DisasCompare; 109fcf5ef2aSThomas Huth 110fcf5ef2aSThomas Huth // This function uses non-native bit order 111fcf5ef2aSThomas Huth #define GET_FIELD(X, FROM, TO) \ 112fcf5ef2aSThomas Huth ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth // This function uses the order in the manuals, i.e. bit 0 is 2^0 115fcf5ef2aSThomas Huth #define GET_FIELD_SP(X, FROM, TO) \ 116fcf5ef2aSThomas Huth GET_FIELD(X, 31 - (TO), 31 - (FROM)) 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) 119fcf5ef2aSThomas Huth #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 122fcf5ef2aSThomas Huth #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) 123fcf5ef2aSThomas Huth #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) 124fcf5ef2aSThomas Huth #else 125fcf5ef2aSThomas Huth #define DFPREG(r) (r & 0x1e) 126fcf5ef2aSThomas Huth #define QFPREG(r) (r & 0x1c) 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth #define UA2005_HTRAP_MASK 0xff 130fcf5ef2aSThomas Huth #define V8_TRAP_MASK 0x7f 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth static int sign_extend(int x, int len) 133fcf5ef2aSThomas Huth { 134fcf5ef2aSThomas Huth len = 32 - len; 135fcf5ef2aSThomas Huth return (x << len) >> len; 136fcf5ef2aSThomas Huth } 137fcf5ef2aSThomas Huth 138fcf5ef2aSThomas Huth #define IS_IMM (insn & (1<<13)) 139fcf5ef2aSThomas Huth 1400c2e96c1SRichard Henderson static void gen_update_fprs_dirty(DisasContext *dc, int rd) 141fcf5ef2aSThomas Huth { 142fcf5ef2aSThomas Huth #if defined(TARGET_SPARC64) 143fcf5ef2aSThomas Huth int bit = (rd < 32) ? 1 : 2; 144fcf5ef2aSThomas Huth /* If we know we've already set this bit within the TB, 145fcf5ef2aSThomas Huth we can avoid setting it again. */ 146fcf5ef2aSThomas Huth if (!(dc->fprs_dirty & bit)) { 147fcf5ef2aSThomas Huth dc->fprs_dirty |= bit; 148fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit); 149fcf5ef2aSThomas Huth } 150fcf5ef2aSThomas Huth #endif 151fcf5ef2aSThomas Huth } 152fcf5ef2aSThomas Huth 153fcf5ef2aSThomas Huth /* floating point registers moves */ 154fcf5ef2aSThomas Huth static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) 155fcf5ef2aSThomas Huth { 15636ab4623SRichard Henderson TCGv_i32 ret = tcg_temp_new_i32(); 157dc41aa7dSRichard Henderson if (src & 1) { 158dc41aa7dSRichard Henderson tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); 159dc41aa7dSRichard Henderson } else { 160dc41aa7dSRichard Henderson tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]); 161fcf5ef2aSThomas Huth } 162dc41aa7dSRichard Henderson return ret; 163fcf5ef2aSThomas Huth } 164fcf5ef2aSThomas Huth 165fcf5ef2aSThomas Huth static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) 166fcf5ef2aSThomas Huth { 1678e7bbc75SRichard Henderson TCGv_i64 t = tcg_temp_new_i64(); 1688e7bbc75SRichard Henderson 1698e7bbc75SRichard Henderson tcg_gen_extu_i32_i64(t, v); 170fcf5ef2aSThomas Huth tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, 171fcf5ef2aSThomas Huth (dst & 1 ? 0 : 32), 32); 172fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, dst); 173fcf5ef2aSThomas Huth } 174fcf5ef2aSThomas Huth 175fcf5ef2aSThomas Huth static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) 176fcf5ef2aSThomas Huth { 17736ab4623SRichard Henderson return tcg_temp_new_i32(); 178fcf5ef2aSThomas Huth } 179fcf5ef2aSThomas Huth 180fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) 181fcf5ef2aSThomas Huth { 182fcf5ef2aSThomas Huth src = DFPREG(src); 183fcf5ef2aSThomas Huth return cpu_fpr[src / 2]; 184fcf5ef2aSThomas Huth } 185fcf5ef2aSThomas Huth 186fcf5ef2aSThomas Huth static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) 187fcf5ef2aSThomas Huth { 188fcf5ef2aSThomas Huth dst = DFPREG(dst); 189fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[dst / 2], v); 190fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, dst); 191fcf5ef2aSThomas Huth } 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) 194fcf5ef2aSThomas Huth { 195fcf5ef2aSThomas Huth return cpu_fpr[DFPREG(dst) / 2]; 196fcf5ef2aSThomas Huth } 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth static void gen_op_load_fpr_QT0(unsigned int src) 199fcf5ef2aSThomas Huth { 200ad75a51eSRichard Henderson tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0) + 201fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.upper)); 202ad75a51eSRichard Henderson tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) + 203fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.lower)); 204fcf5ef2aSThomas Huth } 205fcf5ef2aSThomas Huth 206fcf5ef2aSThomas Huth static void gen_op_load_fpr_QT1(unsigned int src) 207fcf5ef2aSThomas Huth { 208ad75a51eSRichard Henderson tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1) + 209fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.upper)); 210ad75a51eSRichard Henderson tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt1) + 211fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.lower)); 212fcf5ef2aSThomas Huth } 213fcf5ef2aSThomas Huth 214fcf5ef2aSThomas Huth static void gen_op_store_QT0_fpr(unsigned int dst) 215fcf5ef2aSThomas Huth { 216ad75a51eSRichard Henderson tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) + 217fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.upper)); 218ad75a51eSRichard Henderson tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) + 219fcf5ef2aSThomas Huth offsetof(CPU_QuadU, ll.lower)); 220fcf5ef2aSThomas Huth } 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, 223fcf5ef2aSThomas Huth TCGv_i64 v1, TCGv_i64 v2) 224fcf5ef2aSThomas Huth { 225fcf5ef2aSThomas Huth dst = QFPREG(dst); 226fcf5ef2aSThomas Huth 227fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[dst / 2], v1); 228fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2); 229fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, dst); 230fcf5ef2aSThomas Huth } 231fcf5ef2aSThomas Huth 232fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 233fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src) 234fcf5ef2aSThomas Huth { 235fcf5ef2aSThomas Huth src = QFPREG(src); 236fcf5ef2aSThomas Huth return cpu_fpr[src / 2]; 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth 239fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src) 240fcf5ef2aSThomas Huth { 241fcf5ef2aSThomas Huth src = QFPREG(src); 242fcf5ef2aSThomas Huth return cpu_fpr[src / 2 + 1]; 243fcf5ef2aSThomas Huth } 244fcf5ef2aSThomas Huth 245fcf5ef2aSThomas Huth static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) 246fcf5ef2aSThomas Huth { 247fcf5ef2aSThomas Huth rd = QFPREG(rd); 248fcf5ef2aSThomas Huth rs = QFPREG(rs); 249fcf5ef2aSThomas Huth 250fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); 251fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); 252fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, rd); 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth #endif 255fcf5ef2aSThomas Huth 256fcf5ef2aSThomas Huth /* moves */ 257fcf5ef2aSThomas Huth #ifdef CONFIG_USER_ONLY 258fcf5ef2aSThomas Huth #define supervisor(dc) 0 259fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 260fcf5ef2aSThomas Huth #define hypervisor(dc) 0 261fcf5ef2aSThomas Huth #endif 262fcf5ef2aSThomas Huth #else 263fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 264c9b459aaSArtyom Tarasenko #define hypervisor(dc) (dc->hypervisor) 265c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor | dc->hypervisor) 266fcf5ef2aSThomas Huth #else 267c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor) 268fcf5ef2aSThomas Huth #endif 269fcf5ef2aSThomas Huth #endif 270fcf5ef2aSThomas Huth 271b1bc09eaSRichard Henderson #if !defined(TARGET_SPARC64) 272b1bc09eaSRichard Henderson # define AM_CHECK(dc) false 273b1bc09eaSRichard Henderson #elif defined(TARGET_ABI32) 274b1bc09eaSRichard Henderson # define AM_CHECK(dc) true 275b1bc09eaSRichard Henderson #elif defined(CONFIG_USER_ONLY) 276b1bc09eaSRichard Henderson # define AM_CHECK(dc) false 277fcf5ef2aSThomas Huth #else 278b1bc09eaSRichard Henderson # define AM_CHECK(dc) ((dc)->address_mask_32bit) 279fcf5ef2aSThomas Huth #endif 280fcf5ef2aSThomas Huth 2810c2e96c1SRichard Henderson static void gen_address_mask(DisasContext *dc, TCGv addr) 282fcf5ef2aSThomas Huth { 283b1bc09eaSRichard Henderson if (AM_CHECK(dc)) { 284fcf5ef2aSThomas Huth tcg_gen_andi_tl(addr, addr, 0xffffffffULL); 285b1bc09eaSRichard Henderson } 286fcf5ef2aSThomas Huth } 287fcf5ef2aSThomas Huth 28823ada1b1SRichard Henderson static target_ulong address_mask_i(DisasContext *dc, target_ulong addr) 28923ada1b1SRichard Henderson { 29023ada1b1SRichard Henderson return AM_CHECK(dc) ? (uint32_t)addr : addr; 29123ada1b1SRichard Henderson } 29223ada1b1SRichard Henderson 2930c2e96c1SRichard Henderson static TCGv gen_load_gpr(DisasContext *dc, int reg) 294fcf5ef2aSThomas Huth { 295fcf5ef2aSThomas Huth if (reg > 0) { 296fcf5ef2aSThomas Huth assert(reg < 32); 297fcf5ef2aSThomas Huth return cpu_regs[reg]; 298fcf5ef2aSThomas Huth } else { 29952123f14SRichard Henderson TCGv t = tcg_temp_new(); 300fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, 0); 301fcf5ef2aSThomas Huth return t; 302fcf5ef2aSThomas Huth } 303fcf5ef2aSThomas Huth } 304fcf5ef2aSThomas Huth 3050c2e96c1SRichard Henderson static void gen_store_gpr(DisasContext *dc, int reg, TCGv v) 306fcf5ef2aSThomas Huth { 307fcf5ef2aSThomas Huth if (reg > 0) { 308fcf5ef2aSThomas Huth assert(reg < 32); 309fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_regs[reg], v); 310fcf5ef2aSThomas Huth } 311fcf5ef2aSThomas Huth } 312fcf5ef2aSThomas Huth 3130c2e96c1SRichard Henderson static TCGv gen_dest_gpr(DisasContext *dc, int reg) 314fcf5ef2aSThomas Huth { 315fcf5ef2aSThomas Huth if (reg > 0) { 316fcf5ef2aSThomas Huth assert(reg < 32); 317fcf5ef2aSThomas Huth return cpu_regs[reg]; 318fcf5ef2aSThomas Huth } else { 31952123f14SRichard Henderson return tcg_temp_new(); 320fcf5ef2aSThomas Huth } 321fcf5ef2aSThomas Huth } 322fcf5ef2aSThomas Huth 3235645aa2eSRichard Henderson static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc) 324fcf5ef2aSThomas Huth { 3255645aa2eSRichard Henderson return translator_use_goto_tb(&s->base, pc) && 3265645aa2eSRichard Henderson translator_use_goto_tb(&s->base, npc); 327fcf5ef2aSThomas Huth } 328fcf5ef2aSThomas Huth 3295645aa2eSRichard Henderson static void gen_goto_tb(DisasContext *s, int tb_num, 330fcf5ef2aSThomas Huth target_ulong pc, target_ulong npc) 331fcf5ef2aSThomas Huth { 332fcf5ef2aSThomas Huth if (use_goto_tb(s, pc, npc)) { 333fcf5ef2aSThomas Huth /* jump to same page: we can use a direct jump */ 334fcf5ef2aSThomas Huth tcg_gen_goto_tb(tb_num); 335fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_pc, pc); 336fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_npc, npc); 33707ea28b4SRichard Henderson tcg_gen_exit_tb(s->base.tb, tb_num); 338fcf5ef2aSThomas Huth } else { 339f67ccb2fSRichard Henderson /* jump to another page: we can use an indirect jump */ 340fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_pc, pc); 341fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_npc, npc); 342f67ccb2fSRichard Henderson tcg_gen_lookup_and_goto_ptr(); 343fcf5ef2aSThomas Huth } 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth // XXX suboptimal 3470c2e96c1SRichard Henderson static void gen_mov_reg_N(TCGv reg, TCGv_i32 src) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(reg, src); 3500b1183e3SPhilippe Mathieu-Daudé tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 3530c2e96c1SRichard Henderson static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(reg, src); 3560b1183e3SPhilippe Mathieu-Daudé tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 3590c2e96c1SRichard Henderson static void gen_mov_reg_V(TCGv reg, TCGv_i32 src) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(reg, src); 3620b1183e3SPhilippe Mathieu-Daudé tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth 3650c2e96c1SRichard Henderson static void gen_mov_reg_C(TCGv reg, TCGv_i32 src) 366fcf5ef2aSThomas Huth { 367fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(reg, src); 3680b1183e3SPhilippe Mathieu-Daudé tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); 369fcf5ef2aSThomas Huth } 370fcf5ef2aSThomas Huth 3710c2e96c1SRichard Henderson static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) 372fcf5ef2aSThomas Huth { 373fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src, src1); 374fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src2, src2); 375fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 376fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_cc_dst); 377fcf5ef2aSThomas Huth } 378fcf5ef2aSThomas Huth 379fcf5ef2aSThomas Huth static TCGv_i32 gen_add32_carry32(void) 380fcf5ef2aSThomas Huth { 381fcf5ef2aSThomas Huth TCGv_i32 carry_32, cc_src1_32, cc_src2_32; 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth /* Carry is computed from a previous add: (dst < src) */ 384fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64 385fcf5ef2aSThomas Huth cc_src1_32 = tcg_temp_new_i32(); 386fcf5ef2aSThomas Huth cc_src2_32 = tcg_temp_new_i32(); 387fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst); 388fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src); 389fcf5ef2aSThomas Huth #else 390fcf5ef2aSThomas Huth cc_src1_32 = cpu_cc_dst; 391fcf5ef2aSThomas Huth cc_src2_32 = cpu_cc_src; 392fcf5ef2aSThomas Huth #endif 393fcf5ef2aSThomas Huth 394fcf5ef2aSThomas Huth carry_32 = tcg_temp_new_i32(); 395fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); 396fcf5ef2aSThomas Huth 397fcf5ef2aSThomas Huth return carry_32; 398fcf5ef2aSThomas Huth } 399fcf5ef2aSThomas Huth 400fcf5ef2aSThomas Huth static TCGv_i32 gen_sub32_carry32(void) 401fcf5ef2aSThomas Huth { 402fcf5ef2aSThomas Huth TCGv_i32 carry_32, cc_src1_32, cc_src2_32; 403fcf5ef2aSThomas Huth 404fcf5ef2aSThomas Huth /* Carry is computed from a previous borrow: (src1 < src2) */ 405fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64 406fcf5ef2aSThomas Huth cc_src1_32 = tcg_temp_new_i32(); 407fcf5ef2aSThomas Huth cc_src2_32 = tcg_temp_new_i32(); 408fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src); 409fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2); 410fcf5ef2aSThomas Huth #else 411fcf5ef2aSThomas Huth cc_src1_32 = cpu_cc_src; 412fcf5ef2aSThomas Huth cc_src2_32 = cpu_cc_src2; 413fcf5ef2aSThomas Huth #endif 414fcf5ef2aSThomas Huth 415fcf5ef2aSThomas Huth carry_32 = tcg_temp_new_i32(); 416fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); 417fcf5ef2aSThomas Huth 418fcf5ef2aSThomas Huth return carry_32; 419fcf5ef2aSThomas Huth } 420fcf5ef2aSThomas Huth 421fcf5ef2aSThomas Huth static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, 422fcf5ef2aSThomas Huth TCGv src2, int update_cc) 423fcf5ef2aSThomas Huth { 424fcf5ef2aSThomas Huth TCGv_i32 carry_32; 425fcf5ef2aSThomas Huth TCGv carry; 426fcf5ef2aSThomas Huth 427fcf5ef2aSThomas Huth switch (dc->cc_op) { 428fcf5ef2aSThomas Huth case CC_OP_DIV: 429fcf5ef2aSThomas Huth case CC_OP_LOGIC: 430fcf5ef2aSThomas Huth /* Carry is known to be zero. Fall back to plain ADD. */ 431fcf5ef2aSThomas Huth if (update_cc) { 432fcf5ef2aSThomas Huth gen_op_add_cc(dst, src1, src2); 433fcf5ef2aSThomas Huth } else { 434fcf5ef2aSThomas Huth tcg_gen_add_tl(dst, src1, src2); 435fcf5ef2aSThomas Huth } 436fcf5ef2aSThomas Huth return; 437fcf5ef2aSThomas Huth 438fcf5ef2aSThomas Huth case CC_OP_ADD: 439fcf5ef2aSThomas Huth case CC_OP_TADD: 440fcf5ef2aSThomas Huth case CC_OP_TADDTV: 441fcf5ef2aSThomas Huth if (TARGET_LONG_BITS == 32) { 442fcf5ef2aSThomas Huth /* We can re-use the host's hardware carry generation by using 443fcf5ef2aSThomas Huth an ADD2 opcode. We discard the low part of the output. 444fcf5ef2aSThomas Huth Ideally we'd combine this operation with the add that 445fcf5ef2aSThomas Huth generated the carry in the first place. */ 446fcf5ef2aSThomas Huth carry = tcg_temp_new(); 447fcf5ef2aSThomas Huth tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2); 448fcf5ef2aSThomas Huth goto add_done; 449fcf5ef2aSThomas Huth } 450fcf5ef2aSThomas Huth carry_32 = gen_add32_carry32(); 451fcf5ef2aSThomas Huth break; 452fcf5ef2aSThomas Huth 453fcf5ef2aSThomas Huth case CC_OP_SUB: 454fcf5ef2aSThomas Huth case CC_OP_TSUB: 455fcf5ef2aSThomas Huth case CC_OP_TSUBTV: 456fcf5ef2aSThomas Huth carry_32 = gen_sub32_carry32(); 457fcf5ef2aSThomas Huth break; 458fcf5ef2aSThomas Huth 459fcf5ef2aSThomas Huth default: 460fcf5ef2aSThomas Huth /* We need external help to produce the carry. */ 461fcf5ef2aSThomas Huth carry_32 = tcg_temp_new_i32(); 462ad75a51eSRichard Henderson gen_helper_compute_C_icc(carry_32, tcg_env); 463fcf5ef2aSThomas Huth break; 464fcf5ef2aSThomas Huth } 465fcf5ef2aSThomas Huth 466fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64 467fcf5ef2aSThomas Huth carry = tcg_temp_new(); 468fcf5ef2aSThomas Huth tcg_gen_extu_i32_i64(carry, carry_32); 469fcf5ef2aSThomas Huth #else 470fcf5ef2aSThomas Huth carry = carry_32; 471fcf5ef2aSThomas Huth #endif 472fcf5ef2aSThomas Huth 473fcf5ef2aSThomas Huth tcg_gen_add_tl(dst, src1, src2); 474fcf5ef2aSThomas Huth tcg_gen_add_tl(dst, dst, carry); 475fcf5ef2aSThomas Huth 476fcf5ef2aSThomas Huth add_done: 477fcf5ef2aSThomas Huth if (update_cc) { 478fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src, src1); 479fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src2, src2); 480fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, dst); 481fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); 482fcf5ef2aSThomas Huth dc->cc_op = CC_OP_ADDX; 483fcf5ef2aSThomas Huth } 484fcf5ef2aSThomas Huth } 485fcf5ef2aSThomas Huth 4860c2e96c1SRichard Henderson static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) 487fcf5ef2aSThomas Huth { 488fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src, src1); 489fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src2, src2); 490fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 491fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_cc_dst); 492fcf5ef2aSThomas Huth } 493fcf5ef2aSThomas Huth 494fcf5ef2aSThomas Huth static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, 495fcf5ef2aSThomas Huth TCGv src2, int update_cc) 496fcf5ef2aSThomas Huth { 497fcf5ef2aSThomas Huth TCGv_i32 carry_32; 498fcf5ef2aSThomas Huth TCGv carry; 499fcf5ef2aSThomas Huth 500fcf5ef2aSThomas Huth switch (dc->cc_op) { 501fcf5ef2aSThomas Huth case CC_OP_DIV: 502fcf5ef2aSThomas Huth case CC_OP_LOGIC: 503fcf5ef2aSThomas Huth /* Carry is known to be zero. Fall back to plain SUB. */ 504fcf5ef2aSThomas Huth if (update_cc) { 505fcf5ef2aSThomas Huth gen_op_sub_cc(dst, src1, src2); 506fcf5ef2aSThomas Huth } else { 507fcf5ef2aSThomas Huth tcg_gen_sub_tl(dst, src1, src2); 508fcf5ef2aSThomas Huth } 509fcf5ef2aSThomas Huth return; 510fcf5ef2aSThomas Huth 511fcf5ef2aSThomas Huth case CC_OP_ADD: 512fcf5ef2aSThomas Huth case CC_OP_TADD: 513fcf5ef2aSThomas Huth case CC_OP_TADDTV: 514fcf5ef2aSThomas Huth carry_32 = gen_add32_carry32(); 515fcf5ef2aSThomas Huth break; 516fcf5ef2aSThomas Huth 517fcf5ef2aSThomas Huth case CC_OP_SUB: 518fcf5ef2aSThomas Huth case CC_OP_TSUB: 519fcf5ef2aSThomas Huth case CC_OP_TSUBTV: 520fcf5ef2aSThomas Huth if (TARGET_LONG_BITS == 32) { 521fcf5ef2aSThomas Huth /* We can re-use the host's hardware carry generation by using 522fcf5ef2aSThomas Huth a SUB2 opcode. We discard the low part of the output. 523fcf5ef2aSThomas Huth Ideally we'd combine this operation with the add that 524fcf5ef2aSThomas Huth generated the carry in the first place. */ 525fcf5ef2aSThomas Huth carry = tcg_temp_new(); 526fcf5ef2aSThomas Huth tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2); 527fcf5ef2aSThomas Huth goto sub_done; 528fcf5ef2aSThomas Huth } 529fcf5ef2aSThomas Huth carry_32 = gen_sub32_carry32(); 530fcf5ef2aSThomas Huth break; 531fcf5ef2aSThomas Huth 532fcf5ef2aSThomas Huth default: 533fcf5ef2aSThomas Huth /* We need external help to produce the carry. */ 534fcf5ef2aSThomas Huth carry_32 = tcg_temp_new_i32(); 535ad75a51eSRichard Henderson gen_helper_compute_C_icc(carry_32, tcg_env); 536fcf5ef2aSThomas Huth break; 537fcf5ef2aSThomas Huth } 538fcf5ef2aSThomas Huth 539fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64 540fcf5ef2aSThomas Huth carry = tcg_temp_new(); 541fcf5ef2aSThomas Huth tcg_gen_extu_i32_i64(carry, carry_32); 542fcf5ef2aSThomas Huth #else 543fcf5ef2aSThomas Huth carry = carry_32; 544fcf5ef2aSThomas Huth #endif 545fcf5ef2aSThomas Huth 546fcf5ef2aSThomas Huth tcg_gen_sub_tl(dst, src1, src2); 547fcf5ef2aSThomas Huth tcg_gen_sub_tl(dst, dst, carry); 548fcf5ef2aSThomas Huth 549fcf5ef2aSThomas Huth sub_done: 550fcf5ef2aSThomas Huth if (update_cc) { 551fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src, src1); 552fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src2, src2); 553fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, dst); 554fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); 555fcf5ef2aSThomas Huth dc->cc_op = CC_OP_SUBX; 556fcf5ef2aSThomas Huth } 557fcf5ef2aSThomas Huth } 558fcf5ef2aSThomas Huth 5590c2e96c1SRichard Henderson static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) 560fcf5ef2aSThomas Huth { 561fcf5ef2aSThomas Huth TCGv r_temp, zero, t0; 562fcf5ef2aSThomas Huth 563fcf5ef2aSThomas Huth r_temp = tcg_temp_new(); 564fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 565fcf5ef2aSThomas Huth 566fcf5ef2aSThomas Huth /* old op: 567fcf5ef2aSThomas Huth if (!(env->y & 1)) 568fcf5ef2aSThomas Huth T1 = 0; 569fcf5ef2aSThomas Huth */ 57000ab7e61SRichard Henderson zero = tcg_constant_tl(0); 571fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); 572fcf5ef2aSThomas Huth tcg_gen_andi_tl(r_temp, cpu_y, 0x1); 573fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); 574fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero, 575fcf5ef2aSThomas Huth zero, cpu_cc_src2); 576fcf5ef2aSThomas Huth 577fcf5ef2aSThomas Huth // b2 = T0 & 1; 578fcf5ef2aSThomas Huth // env->y = (b2 << 31) | (env->y >> 1); 5790b1183e3SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_y, 1, 31); 58008d64e0dSPhilippe Mathieu-Daudé tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); 581fcf5ef2aSThomas Huth 582fcf5ef2aSThomas Huth // b1 = N ^ V; 583fcf5ef2aSThomas Huth gen_mov_reg_N(t0, cpu_psr); 584fcf5ef2aSThomas Huth gen_mov_reg_V(r_temp, cpu_psr); 585fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, t0, r_temp); 586fcf5ef2aSThomas Huth 587fcf5ef2aSThomas Huth // T0 = (b1 << 31) | (T0 >> 1); 588fcf5ef2aSThomas Huth // src1 = T0; 589fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, t0, 31); 590fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); 591fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); 592fcf5ef2aSThomas Huth 593fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 594fcf5ef2aSThomas Huth 595fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_cc_dst); 596fcf5ef2aSThomas Huth } 597fcf5ef2aSThomas Huth 5980c2e96c1SRichard Henderson static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) 599fcf5ef2aSThomas Huth { 600fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 32 601fcf5ef2aSThomas Huth if (sign_ext) { 602fcf5ef2aSThomas Huth tcg_gen_muls2_tl(dst, cpu_y, src1, src2); 603fcf5ef2aSThomas Huth } else { 604fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(dst, cpu_y, src1, src2); 605fcf5ef2aSThomas Huth } 606fcf5ef2aSThomas Huth #else 607fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new_i64(); 608fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new_i64(); 609fcf5ef2aSThomas Huth 610fcf5ef2aSThomas Huth if (sign_ext) { 611fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t0, src1); 612fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, src2); 613fcf5ef2aSThomas Huth } else { 614fcf5ef2aSThomas Huth tcg_gen_ext32u_i64(t0, src1); 615fcf5ef2aSThomas Huth tcg_gen_ext32u_i64(t1, src2); 616fcf5ef2aSThomas Huth } 617fcf5ef2aSThomas Huth 618fcf5ef2aSThomas Huth tcg_gen_mul_i64(dst, t0, t1); 619fcf5ef2aSThomas Huth tcg_gen_shri_i64(cpu_y, dst, 32); 620fcf5ef2aSThomas Huth #endif 621fcf5ef2aSThomas Huth } 622fcf5ef2aSThomas Huth 6230c2e96c1SRichard Henderson static void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) 624fcf5ef2aSThomas Huth { 625fcf5ef2aSThomas Huth /* zero-extend truncated operands before multiplication */ 626fcf5ef2aSThomas Huth gen_op_multiply(dst, src1, src2, 0); 627fcf5ef2aSThomas Huth } 628fcf5ef2aSThomas Huth 6290c2e96c1SRichard Henderson static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) 630fcf5ef2aSThomas Huth { 631fcf5ef2aSThomas Huth /* sign-extend truncated operands before multiplication */ 632fcf5ef2aSThomas Huth gen_op_multiply(dst, src1, src2, 1); 633fcf5ef2aSThomas Huth } 634fcf5ef2aSThomas Huth 635fcf5ef2aSThomas Huth // 1 6360c2e96c1SRichard Henderson static void gen_op_eval_ba(TCGv dst) 637fcf5ef2aSThomas Huth { 638fcf5ef2aSThomas Huth tcg_gen_movi_tl(dst, 1); 639fcf5ef2aSThomas Huth } 640fcf5ef2aSThomas Huth 641fcf5ef2aSThomas Huth // Z 6420c2e96c1SRichard Henderson static void gen_op_eval_be(TCGv dst, TCGv_i32 src) 643fcf5ef2aSThomas Huth { 644fcf5ef2aSThomas Huth gen_mov_reg_Z(dst, src); 645fcf5ef2aSThomas Huth } 646fcf5ef2aSThomas Huth 647fcf5ef2aSThomas Huth // Z | (N ^ V) 6480c2e96c1SRichard Henderson static void gen_op_eval_ble(TCGv dst, TCGv_i32 src) 649fcf5ef2aSThomas Huth { 650fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 651fcf5ef2aSThomas Huth gen_mov_reg_N(t0, src); 652fcf5ef2aSThomas Huth gen_mov_reg_V(dst, src); 653fcf5ef2aSThomas Huth tcg_gen_xor_tl(dst, dst, t0); 654fcf5ef2aSThomas Huth gen_mov_reg_Z(t0, src); 655fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 656fcf5ef2aSThomas Huth } 657fcf5ef2aSThomas Huth 658fcf5ef2aSThomas Huth // N ^ V 6590c2e96c1SRichard Henderson static void gen_op_eval_bl(TCGv dst, TCGv_i32 src) 660fcf5ef2aSThomas Huth { 661fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 662fcf5ef2aSThomas Huth gen_mov_reg_V(t0, src); 663fcf5ef2aSThomas Huth gen_mov_reg_N(dst, src); 664fcf5ef2aSThomas Huth tcg_gen_xor_tl(dst, dst, t0); 665fcf5ef2aSThomas Huth } 666fcf5ef2aSThomas Huth 667fcf5ef2aSThomas Huth // C | Z 6680c2e96c1SRichard Henderson static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) 669fcf5ef2aSThomas Huth { 670fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 671fcf5ef2aSThomas Huth gen_mov_reg_Z(t0, src); 672fcf5ef2aSThomas Huth gen_mov_reg_C(dst, src); 673fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth 676fcf5ef2aSThomas Huth // C 6770c2e96c1SRichard Henderson static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) 678fcf5ef2aSThomas Huth { 679fcf5ef2aSThomas Huth gen_mov_reg_C(dst, src); 680fcf5ef2aSThomas Huth } 681fcf5ef2aSThomas Huth 682fcf5ef2aSThomas Huth // V 6830c2e96c1SRichard Henderson static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) 684fcf5ef2aSThomas Huth { 685fcf5ef2aSThomas Huth gen_mov_reg_V(dst, src); 686fcf5ef2aSThomas Huth } 687fcf5ef2aSThomas Huth 688fcf5ef2aSThomas Huth // 0 6890c2e96c1SRichard Henderson static void gen_op_eval_bn(TCGv dst) 690fcf5ef2aSThomas Huth { 691fcf5ef2aSThomas Huth tcg_gen_movi_tl(dst, 0); 692fcf5ef2aSThomas Huth } 693fcf5ef2aSThomas Huth 694fcf5ef2aSThomas Huth // N 6950c2e96c1SRichard Henderson static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) 696fcf5ef2aSThomas Huth { 697fcf5ef2aSThomas Huth gen_mov_reg_N(dst, src); 698fcf5ef2aSThomas Huth } 699fcf5ef2aSThomas Huth 700fcf5ef2aSThomas Huth // !Z 7010c2e96c1SRichard Henderson static void gen_op_eval_bne(TCGv dst, TCGv_i32 src) 702fcf5ef2aSThomas Huth { 703fcf5ef2aSThomas Huth gen_mov_reg_Z(dst, src); 704fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 705fcf5ef2aSThomas Huth } 706fcf5ef2aSThomas Huth 707fcf5ef2aSThomas Huth // !(Z | (N ^ V)) 7080c2e96c1SRichard Henderson static void gen_op_eval_bg(TCGv dst, TCGv_i32 src) 709fcf5ef2aSThomas Huth { 710fcf5ef2aSThomas Huth gen_op_eval_ble(dst, src); 711fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 712fcf5ef2aSThomas Huth } 713fcf5ef2aSThomas Huth 714fcf5ef2aSThomas Huth // !(N ^ V) 7150c2e96c1SRichard Henderson static void gen_op_eval_bge(TCGv dst, TCGv_i32 src) 716fcf5ef2aSThomas Huth { 717fcf5ef2aSThomas Huth gen_op_eval_bl(dst, src); 718fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 719fcf5ef2aSThomas Huth } 720fcf5ef2aSThomas Huth 721fcf5ef2aSThomas Huth // !(C | Z) 7220c2e96c1SRichard Henderson static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) 723fcf5ef2aSThomas Huth { 724fcf5ef2aSThomas Huth gen_op_eval_bleu(dst, src); 725fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 726fcf5ef2aSThomas Huth } 727fcf5ef2aSThomas Huth 728fcf5ef2aSThomas Huth // !C 7290c2e96c1SRichard Henderson static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) 730fcf5ef2aSThomas Huth { 731fcf5ef2aSThomas Huth gen_mov_reg_C(dst, src); 732fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 733fcf5ef2aSThomas Huth } 734fcf5ef2aSThomas Huth 735fcf5ef2aSThomas Huth // !N 7360c2e96c1SRichard Henderson static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) 737fcf5ef2aSThomas Huth { 738fcf5ef2aSThomas Huth gen_mov_reg_N(dst, src); 739fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 740fcf5ef2aSThomas Huth } 741fcf5ef2aSThomas Huth 742fcf5ef2aSThomas Huth // !V 7430c2e96c1SRichard Henderson static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) 744fcf5ef2aSThomas Huth { 745fcf5ef2aSThomas Huth gen_mov_reg_V(dst, src); 746fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 747fcf5ef2aSThomas Huth } 748fcf5ef2aSThomas Huth 749fcf5ef2aSThomas Huth /* 750fcf5ef2aSThomas Huth FPSR bit field FCC1 | FCC0: 751fcf5ef2aSThomas Huth 0 = 752fcf5ef2aSThomas Huth 1 < 753fcf5ef2aSThomas Huth 2 > 754fcf5ef2aSThomas Huth 3 unordered 755fcf5ef2aSThomas Huth */ 7560c2e96c1SRichard Henderson static void gen_mov_reg_FCC0(TCGv reg, TCGv src, 757fcf5ef2aSThomas Huth unsigned int fcc_offset) 758fcf5ef2aSThomas Huth { 759fcf5ef2aSThomas Huth tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); 760fcf5ef2aSThomas Huth tcg_gen_andi_tl(reg, reg, 0x1); 761fcf5ef2aSThomas Huth } 762fcf5ef2aSThomas Huth 7630c2e96c1SRichard Henderson static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) 764fcf5ef2aSThomas Huth { 765fcf5ef2aSThomas Huth tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); 766fcf5ef2aSThomas Huth tcg_gen_andi_tl(reg, reg, 0x1); 767fcf5ef2aSThomas Huth } 768fcf5ef2aSThomas Huth 769fcf5ef2aSThomas Huth // !0: FCC0 | FCC1 7700c2e96c1SRichard Henderson static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset) 771fcf5ef2aSThomas Huth { 772fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 773fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 774fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 775fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 776fcf5ef2aSThomas Huth } 777fcf5ef2aSThomas Huth 778fcf5ef2aSThomas Huth // 1 or 2: FCC0 ^ FCC1 7790c2e96c1SRichard Henderson static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset) 780fcf5ef2aSThomas Huth { 781fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 782fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 783fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 784fcf5ef2aSThomas Huth tcg_gen_xor_tl(dst, dst, t0); 785fcf5ef2aSThomas Huth } 786fcf5ef2aSThomas Huth 787fcf5ef2aSThomas Huth // 1 or 3: FCC0 7880c2e96c1SRichard Henderson static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset) 789fcf5ef2aSThomas Huth { 790fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 791fcf5ef2aSThomas Huth } 792fcf5ef2aSThomas Huth 793fcf5ef2aSThomas Huth // 1: FCC0 & !FCC1 7940c2e96c1SRichard Henderson static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset) 795fcf5ef2aSThomas Huth { 796fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 797fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 798fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 799fcf5ef2aSThomas Huth tcg_gen_andc_tl(dst, dst, t0); 800fcf5ef2aSThomas Huth } 801fcf5ef2aSThomas Huth 802fcf5ef2aSThomas Huth // 2 or 3: FCC1 8030c2e96c1SRichard Henderson static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset) 804fcf5ef2aSThomas Huth { 805fcf5ef2aSThomas Huth gen_mov_reg_FCC1(dst, src, fcc_offset); 806fcf5ef2aSThomas Huth } 807fcf5ef2aSThomas Huth 808fcf5ef2aSThomas Huth // 2: !FCC0 & FCC1 8090c2e96c1SRichard Henderson static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset) 810fcf5ef2aSThomas Huth { 811fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 812fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 813fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 814fcf5ef2aSThomas Huth tcg_gen_andc_tl(dst, t0, dst); 815fcf5ef2aSThomas Huth } 816fcf5ef2aSThomas Huth 817fcf5ef2aSThomas Huth // 3: FCC0 & FCC1 8180c2e96c1SRichard Henderson static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset) 819fcf5ef2aSThomas Huth { 820fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 821fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 822fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 823fcf5ef2aSThomas Huth tcg_gen_and_tl(dst, dst, t0); 824fcf5ef2aSThomas Huth } 825fcf5ef2aSThomas Huth 826fcf5ef2aSThomas Huth // 0: !(FCC0 | FCC1) 8270c2e96c1SRichard Henderson static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset) 828fcf5ef2aSThomas Huth { 829fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 830fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 831fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 832fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 833fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 834fcf5ef2aSThomas Huth } 835fcf5ef2aSThomas Huth 836fcf5ef2aSThomas Huth // 0 or 3: !(FCC0 ^ FCC1) 8370c2e96c1SRichard Henderson static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset) 838fcf5ef2aSThomas Huth { 839fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 840fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 841fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 842fcf5ef2aSThomas Huth tcg_gen_xor_tl(dst, dst, t0); 843fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 844fcf5ef2aSThomas Huth } 845fcf5ef2aSThomas Huth 846fcf5ef2aSThomas Huth // 0 or 2: !FCC0 8470c2e96c1SRichard Henderson static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset) 848fcf5ef2aSThomas Huth { 849fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 850fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 851fcf5ef2aSThomas Huth } 852fcf5ef2aSThomas Huth 853fcf5ef2aSThomas Huth // !1: !(FCC0 & !FCC1) 8540c2e96c1SRichard Henderson static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset) 855fcf5ef2aSThomas Huth { 856fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 857fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 858fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 859fcf5ef2aSThomas Huth tcg_gen_andc_tl(dst, dst, t0); 860fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 861fcf5ef2aSThomas Huth } 862fcf5ef2aSThomas Huth 863fcf5ef2aSThomas Huth // 0 or 1: !FCC1 8640c2e96c1SRichard Henderson static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset) 865fcf5ef2aSThomas Huth { 866fcf5ef2aSThomas Huth gen_mov_reg_FCC1(dst, src, fcc_offset); 867fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 868fcf5ef2aSThomas Huth } 869fcf5ef2aSThomas Huth 870fcf5ef2aSThomas Huth // !2: !(!FCC0 & FCC1) 8710c2e96c1SRichard Henderson static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset) 872fcf5ef2aSThomas Huth { 873fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 874fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 875fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 876fcf5ef2aSThomas Huth tcg_gen_andc_tl(dst, t0, dst); 877fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 878fcf5ef2aSThomas Huth } 879fcf5ef2aSThomas Huth 880fcf5ef2aSThomas Huth // !3: !(FCC0 & FCC1) 8810c2e96c1SRichard Henderson static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset) 882fcf5ef2aSThomas Huth { 883fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 884fcf5ef2aSThomas Huth gen_mov_reg_FCC0(dst, src, fcc_offset); 885fcf5ef2aSThomas Huth gen_mov_reg_FCC1(t0, src, fcc_offset); 886fcf5ef2aSThomas Huth tcg_gen_and_tl(dst, dst, t0); 887fcf5ef2aSThomas Huth tcg_gen_xori_tl(dst, dst, 0x1); 888fcf5ef2aSThomas Huth } 889fcf5ef2aSThomas Huth 8900c2e96c1SRichard Henderson static void gen_branch2(DisasContext *dc, target_ulong pc1, 891fcf5ef2aSThomas Huth target_ulong pc2, TCGv r_cond) 892fcf5ef2aSThomas Huth { 893fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 894fcf5ef2aSThomas Huth 895fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); 896fcf5ef2aSThomas Huth 897fcf5ef2aSThomas Huth gen_goto_tb(dc, 0, pc1, pc1 + 4); 898fcf5ef2aSThomas Huth 899fcf5ef2aSThomas Huth gen_set_label(l1); 900fcf5ef2aSThomas Huth gen_goto_tb(dc, 1, pc2, pc2 + 4); 901fcf5ef2aSThomas Huth } 902fcf5ef2aSThomas Huth 903fcf5ef2aSThomas Huth static void gen_branch_a(DisasContext *dc, target_ulong pc1) 904fcf5ef2aSThomas Huth { 905fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 906fcf5ef2aSThomas Huth target_ulong npc = dc->npc; 907fcf5ef2aSThomas Huth 908fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); 909fcf5ef2aSThomas Huth 910fcf5ef2aSThomas Huth gen_goto_tb(dc, 0, npc, pc1); 911fcf5ef2aSThomas Huth 912fcf5ef2aSThomas Huth gen_set_label(l1); 913fcf5ef2aSThomas Huth gen_goto_tb(dc, 1, npc + 4, npc + 8); 914fcf5ef2aSThomas Huth 915af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth 918fcf5ef2aSThomas Huth static void gen_branch_n(DisasContext *dc, target_ulong pc1) 919fcf5ef2aSThomas Huth { 920fcf5ef2aSThomas Huth target_ulong npc = dc->npc; 921fcf5ef2aSThomas Huth 922633c4283SRichard Henderson if (npc & 3) { 923633c4283SRichard Henderson switch (npc) { 924633c4283SRichard Henderson case DYNAMIC_PC: 925633c4283SRichard Henderson case DYNAMIC_PC_LOOKUP: 926633c4283SRichard Henderson tcg_gen_mov_tl(cpu_pc, cpu_npc); 927633c4283SRichard Henderson tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); 928633c4283SRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, 929633c4283SRichard Henderson cpu_cond, tcg_constant_tl(0), 930633c4283SRichard Henderson tcg_constant_tl(pc1), cpu_npc); 931633c4283SRichard Henderson dc->pc = npc; 932633c4283SRichard Henderson break; 933633c4283SRichard Henderson default: 934633c4283SRichard Henderson g_assert_not_reached(); 935633c4283SRichard Henderson } 936633c4283SRichard Henderson } else { 937fcf5ef2aSThomas Huth dc->pc = npc; 938fcf5ef2aSThomas Huth dc->jump_pc[0] = pc1; 939fcf5ef2aSThomas Huth dc->jump_pc[1] = npc + 4; 940fcf5ef2aSThomas Huth dc->npc = JUMP_PC; 941fcf5ef2aSThomas Huth } 942fcf5ef2aSThomas Huth } 943fcf5ef2aSThomas Huth 9440c2e96c1SRichard Henderson static void gen_generic_branch(DisasContext *dc) 945fcf5ef2aSThomas Huth { 94600ab7e61SRichard Henderson TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]); 94700ab7e61SRichard Henderson TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]); 94800ab7e61SRichard Henderson TCGv zero = tcg_constant_tl(0); 949fcf5ef2aSThomas Huth 950fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); 951fcf5ef2aSThomas Huth } 952fcf5ef2aSThomas Huth 953fcf5ef2aSThomas Huth /* call this function before using the condition register as it may 954fcf5ef2aSThomas Huth have been set for a jump */ 9550c2e96c1SRichard Henderson static void flush_cond(DisasContext *dc) 956fcf5ef2aSThomas Huth { 957fcf5ef2aSThomas Huth if (dc->npc == JUMP_PC) { 958fcf5ef2aSThomas Huth gen_generic_branch(dc); 95999c82c47SRichard Henderson dc->npc = DYNAMIC_PC_LOOKUP; 960fcf5ef2aSThomas Huth } 961fcf5ef2aSThomas Huth } 962fcf5ef2aSThomas Huth 9630c2e96c1SRichard Henderson static void save_npc(DisasContext *dc) 964fcf5ef2aSThomas Huth { 965633c4283SRichard Henderson if (dc->npc & 3) { 966633c4283SRichard Henderson switch (dc->npc) { 967633c4283SRichard Henderson case JUMP_PC: 968fcf5ef2aSThomas Huth gen_generic_branch(dc); 96999c82c47SRichard Henderson dc->npc = DYNAMIC_PC_LOOKUP; 970633c4283SRichard Henderson break; 971633c4283SRichard Henderson case DYNAMIC_PC: 972633c4283SRichard Henderson case DYNAMIC_PC_LOOKUP: 973633c4283SRichard Henderson break; 974633c4283SRichard Henderson default: 975633c4283SRichard Henderson g_assert_not_reached(); 976633c4283SRichard Henderson } 977633c4283SRichard Henderson } else { 978fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_npc, dc->npc); 979fcf5ef2aSThomas Huth } 980fcf5ef2aSThomas Huth } 981fcf5ef2aSThomas Huth 9820c2e96c1SRichard Henderson static void update_psr(DisasContext *dc) 983fcf5ef2aSThomas Huth { 984fcf5ef2aSThomas Huth if (dc->cc_op != CC_OP_FLAGS) { 985fcf5ef2aSThomas Huth dc->cc_op = CC_OP_FLAGS; 986ad75a51eSRichard Henderson gen_helper_compute_psr(tcg_env); 987fcf5ef2aSThomas Huth } 988fcf5ef2aSThomas Huth } 989fcf5ef2aSThomas Huth 9900c2e96c1SRichard Henderson static void save_state(DisasContext *dc) 991fcf5ef2aSThomas Huth { 992fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_pc, dc->pc); 993fcf5ef2aSThomas Huth save_npc(dc); 994fcf5ef2aSThomas Huth } 995fcf5ef2aSThomas Huth 996fcf5ef2aSThomas Huth static void gen_exception(DisasContext *dc, int which) 997fcf5ef2aSThomas Huth { 998fcf5ef2aSThomas Huth save_state(dc); 999ad75a51eSRichard Henderson gen_helper_raise_exception(tcg_env, tcg_constant_i32(which)); 1000af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 1001fcf5ef2aSThomas Huth } 1002fcf5ef2aSThomas Huth 1003186e7890SRichard Henderson static TCGLabel *delay_exceptionv(DisasContext *dc, TCGv_i32 excp) 1004fcf5ef2aSThomas Huth { 1005186e7890SRichard Henderson DisasDelayException *e = g_new0(DisasDelayException, 1); 1006186e7890SRichard Henderson 1007186e7890SRichard Henderson e->next = dc->delay_excp_list; 1008186e7890SRichard Henderson dc->delay_excp_list = e; 1009186e7890SRichard Henderson 1010186e7890SRichard Henderson e->lab = gen_new_label(); 1011186e7890SRichard Henderson e->excp = excp; 1012186e7890SRichard Henderson e->pc = dc->pc; 1013186e7890SRichard Henderson /* Caller must have used flush_cond before branch. */ 1014186e7890SRichard Henderson assert(e->npc != JUMP_PC); 1015186e7890SRichard Henderson e->npc = dc->npc; 1016186e7890SRichard Henderson 1017186e7890SRichard Henderson return e->lab; 1018186e7890SRichard Henderson } 1019186e7890SRichard Henderson 1020186e7890SRichard Henderson static TCGLabel *delay_exception(DisasContext *dc, int excp) 1021186e7890SRichard Henderson { 1022186e7890SRichard Henderson return delay_exceptionv(dc, tcg_constant_i32(excp)); 1023186e7890SRichard Henderson } 1024186e7890SRichard Henderson 1025186e7890SRichard Henderson static void gen_check_align(DisasContext *dc, TCGv addr, int mask) 1026186e7890SRichard Henderson { 1027186e7890SRichard Henderson TCGv t = tcg_temp_new(); 1028186e7890SRichard Henderson TCGLabel *lab; 1029186e7890SRichard Henderson 1030186e7890SRichard Henderson tcg_gen_andi_tl(t, addr, mask); 1031186e7890SRichard Henderson 1032186e7890SRichard Henderson flush_cond(dc); 1033186e7890SRichard Henderson lab = delay_exception(dc, TT_UNALIGNED); 1034186e7890SRichard Henderson tcg_gen_brcondi_tl(TCG_COND_NE, t, 0, lab); 1035fcf5ef2aSThomas Huth } 1036fcf5ef2aSThomas Huth 10370c2e96c1SRichard Henderson static void gen_mov_pc_npc(DisasContext *dc) 1038fcf5ef2aSThomas Huth { 1039633c4283SRichard Henderson if (dc->npc & 3) { 1040633c4283SRichard Henderson switch (dc->npc) { 1041633c4283SRichard Henderson case JUMP_PC: 1042fcf5ef2aSThomas Huth gen_generic_branch(dc); 1043fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_pc, cpu_npc); 104499c82c47SRichard Henderson dc->pc = DYNAMIC_PC_LOOKUP; 1045633c4283SRichard Henderson break; 1046633c4283SRichard Henderson case DYNAMIC_PC: 1047633c4283SRichard Henderson case DYNAMIC_PC_LOOKUP: 1048fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_pc, cpu_npc); 1049633c4283SRichard Henderson dc->pc = dc->npc; 1050633c4283SRichard Henderson break; 1051633c4283SRichard Henderson default: 1052633c4283SRichard Henderson g_assert_not_reached(); 1053633c4283SRichard Henderson } 1054fcf5ef2aSThomas Huth } else { 1055fcf5ef2aSThomas Huth dc->pc = dc->npc; 1056fcf5ef2aSThomas Huth } 1057fcf5ef2aSThomas Huth } 1058fcf5ef2aSThomas Huth 10590c2e96c1SRichard Henderson static void gen_op_next_insn(void) 1060fcf5ef2aSThomas Huth { 1061fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_pc, cpu_npc); 1062fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); 1063fcf5ef2aSThomas Huth } 1064fcf5ef2aSThomas Huth 1065fcf5ef2aSThomas Huth static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, 1066fcf5ef2aSThomas Huth DisasContext *dc) 1067fcf5ef2aSThomas Huth { 1068fcf5ef2aSThomas Huth static int subcc_cond[16] = { 1069fcf5ef2aSThomas Huth TCG_COND_NEVER, 1070fcf5ef2aSThomas Huth TCG_COND_EQ, 1071fcf5ef2aSThomas Huth TCG_COND_LE, 1072fcf5ef2aSThomas Huth TCG_COND_LT, 1073fcf5ef2aSThomas Huth TCG_COND_LEU, 1074fcf5ef2aSThomas Huth TCG_COND_LTU, 1075fcf5ef2aSThomas Huth -1, /* neg */ 1076fcf5ef2aSThomas Huth -1, /* overflow */ 1077fcf5ef2aSThomas Huth TCG_COND_ALWAYS, 1078fcf5ef2aSThomas Huth TCG_COND_NE, 1079fcf5ef2aSThomas Huth TCG_COND_GT, 1080fcf5ef2aSThomas Huth TCG_COND_GE, 1081fcf5ef2aSThomas Huth TCG_COND_GTU, 1082fcf5ef2aSThomas Huth TCG_COND_GEU, 1083fcf5ef2aSThomas Huth -1, /* pos */ 1084fcf5ef2aSThomas Huth -1, /* no overflow */ 1085fcf5ef2aSThomas Huth }; 1086fcf5ef2aSThomas Huth 1087fcf5ef2aSThomas Huth static int logic_cond[16] = { 1088fcf5ef2aSThomas Huth TCG_COND_NEVER, 1089fcf5ef2aSThomas Huth TCG_COND_EQ, /* eq: Z */ 1090fcf5ef2aSThomas Huth TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */ 1091fcf5ef2aSThomas Huth TCG_COND_LT, /* lt: N ^ V -> N */ 1092fcf5ef2aSThomas Huth TCG_COND_EQ, /* leu: C | Z -> Z */ 1093fcf5ef2aSThomas Huth TCG_COND_NEVER, /* ltu: C -> 0 */ 1094fcf5ef2aSThomas Huth TCG_COND_LT, /* neg: N */ 1095fcf5ef2aSThomas Huth TCG_COND_NEVER, /* vs: V -> 0 */ 1096fcf5ef2aSThomas Huth TCG_COND_ALWAYS, 1097fcf5ef2aSThomas Huth TCG_COND_NE, /* ne: !Z */ 1098fcf5ef2aSThomas Huth TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */ 1099fcf5ef2aSThomas Huth TCG_COND_GE, /* ge: !(N ^ V) -> !N */ 1100fcf5ef2aSThomas Huth TCG_COND_NE, /* gtu: !(C | Z) -> !Z */ 1101fcf5ef2aSThomas Huth TCG_COND_ALWAYS, /* geu: !C -> 1 */ 1102fcf5ef2aSThomas Huth TCG_COND_GE, /* pos: !N */ 1103fcf5ef2aSThomas Huth TCG_COND_ALWAYS, /* vc: !V -> 1 */ 1104fcf5ef2aSThomas Huth }; 1105fcf5ef2aSThomas Huth 1106fcf5ef2aSThomas Huth TCGv_i32 r_src; 1107fcf5ef2aSThomas Huth TCGv r_dst; 1108fcf5ef2aSThomas Huth 1109fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 1110fcf5ef2aSThomas Huth if (xcc) { 1111fcf5ef2aSThomas Huth r_src = cpu_xcc; 1112fcf5ef2aSThomas Huth } else { 1113fcf5ef2aSThomas Huth r_src = cpu_psr; 1114fcf5ef2aSThomas Huth } 1115fcf5ef2aSThomas Huth #else 1116fcf5ef2aSThomas Huth r_src = cpu_psr; 1117fcf5ef2aSThomas Huth #endif 1118fcf5ef2aSThomas Huth 1119fcf5ef2aSThomas Huth switch (dc->cc_op) { 1120fcf5ef2aSThomas Huth case CC_OP_LOGIC: 1121fcf5ef2aSThomas Huth cmp->cond = logic_cond[cond]; 1122fcf5ef2aSThomas Huth do_compare_dst_0: 1123fcf5ef2aSThomas Huth cmp->is_bool = false; 112400ab7e61SRichard Henderson cmp->c2 = tcg_constant_tl(0); 1125fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 1126fcf5ef2aSThomas Huth if (!xcc) { 1127fcf5ef2aSThomas Huth cmp->c1 = tcg_temp_new(); 1128fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); 1129fcf5ef2aSThomas Huth break; 1130fcf5ef2aSThomas Huth } 1131fcf5ef2aSThomas Huth #endif 1132fcf5ef2aSThomas Huth cmp->c1 = cpu_cc_dst; 1133fcf5ef2aSThomas Huth break; 1134fcf5ef2aSThomas Huth 1135fcf5ef2aSThomas Huth case CC_OP_SUB: 1136fcf5ef2aSThomas Huth switch (cond) { 1137fcf5ef2aSThomas Huth case 6: /* neg */ 1138fcf5ef2aSThomas Huth case 14: /* pos */ 1139fcf5ef2aSThomas Huth cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE); 1140fcf5ef2aSThomas Huth goto do_compare_dst_0; 1141fcf5ef2aSThomas Huth 1142fcf5ef2aSThomas Huth case 7: /* overflow */ 1143fcf5ef2aSThomas Huth case 15: /* !overflow */ 1144fcf5ef2aSThomas Huth goto do_dynamic; 1145fcf5ef2aSThomas Huth 1146fcf5ef2aSThomas Huth default: 1147fcf5ef2aSThomas Huth cmp->cond = subcc_cond[cond]; 1148fcf5ef2aSThomas Huth cmp->is_bool = false; 1149fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 1150fcf5ef2aSThomas Huth if (!xcc) { 1151fcf5ef2aSThomas Huth /* Note that sign-extension works for unsigned compares as 1152fcf5ef2aSThomas Huth long as both operands are sign-extended. */ 1153fcf5ef2aSThomas Huth cmp->c1 = tcg_temp_new(); 1154fcf5ef2aSThomas Huth cmp->c2 = tcg_temp_new(); 1155fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); 1156fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2); 1157fcf5ef2aSThomas Huth break; 1158fcf5ef2aSThomas Huth } 1159fcf5ef2aSThomas Huth #endif 1160fcf5ef2aSThomas Huth cmp->c1 = cpu_cc_src; 1161fcf5ef2aSThomas Huth cmp->c2 = cpu_cc_src2; 1162fcf5ef2aSThomas Huth break; 1163fcf5ef2aSThomas Huth } 1164fcf5ef2aSThomas Huth break; 1165fcf5ef2aSThomas Huth 1166fcf5ef2aSThomas Huth default: 1167fcf5ef2aSThomas Huth do_dynamic: 1168ad75a51eSRichard Henderson gen_helper_compute_psr(tcg_env); 1169fcf5ef2aSThomas Huth dc->cc_op = CC_OP_FLAGS; 1170fcf5ef2aSThomas Huth /* FALLTHRU */ 1171fcf5ef2aSThomas Huth 1172fcf5ef2aSThomas Huth case CC_OP_FLAGS: 1173fcf5ef2aSThomas Huth /* We're going to generate a boolean result. */ 1174fcf5ef2aSThomas Huth cmp->cond = TCG_COND_NE; 1175fcf5ef2aSThomas Huth cmp->is_bool = true; 1176fcf5ef2aSThomas Huth cmp->c1 = r_dst = tcg_temp_new(); 117700ab7e61SRichard Henderson cmp->c2 = tcg_constant_tl(0); 1178fcf5ef2aSThomas Huth 1179fcf5ef2aSThomas Huth switch (cond) { 1180fcf5ef2aSThomas Huth case 0x0: 1181fcf5ef2aSThomas Huth gen_op_eval_bn(r_dst); 1182fcf5ef2aSThomas Huth break; 1183fcf5ef2aSThomas Huth case 0x1: 1184fcf5ef2aSThomas Huth gen_op_eval_be(r_dst, r_src); 1185fcf5ef2aSThomas Huth break; 1186fcf5ef2aSThomas Huth case 0x2: 1187fcf5ef2aSThomas Huth gen_op_eval_ble(r_dst, r_src); 1188fcf5ef2aSThomas Huth break; 1189fcf5ef2aSThomas Huth case 0x3: 1190fcf5ef2aSThomas Huth gen_op_eval_bl(r_dst, r_src); 1191fcf5ef2aSThomas Huth break; 1192fcf5ef2aSThomas Huth case 0x4: 1193fcf5ef2aSThomas Huth gen_op_eval_bleu(r_dst, r_src); 1194fcf5ef2aSThomas Huth break; 1195fcf5ef2aSThomas Huth case 0x5: 1196fcf5ef2aSThomas Huth gen_op_eval_bcs(r_dst, r_src); 1197fcf5ef2aSThomas Huth break; 1198fcf5ef2aSThomas Huth case 0x6: 1199fcf5ef2aSThomas Huth gen_op_eval_bneg(r_dst, r_src); 1200fcf5ef2aSThomas Huth break; 1201fcf5ef2aSThomas Huth case 0x7: 1202fcf5ef2aSThomas Huth gen_op_eval_bvs(r_dst, r_src); 1203fcf5ef2aSThomas Huth break; 1204fcf5ef2aSThomas Huth case 0x8: 1205fcf5ef2aSThomas Huth gen_op_eval_ba(r_dst); 1206fcf5ef2aSThomas Huth break; 1207fcf5ef2aSThomas Huth case 0x9: 1208fcf5ef2aSThomas Huth gen_op_eval_bne(r_dst, r_src); 1209fcf5ef2aSThomas Huth break; 1210fcf5ef2aSThomas Huth case 0xa: 1211fcf5ef2aSThomas Huth gen_op_eval_bg(r_dst, r_src); 1212fcf5ef2aSThomas Huth break; 1213fcf5ef2aSThomas Huth case 0xb: 1214fcf5ef2aSThomas Huth gen_op_eval_bge(r_dst, r_src); 1215fcf5ef2aSThomas Huth break; 1216fcf5ef2aSThomas Huth case 0xc: 1217fcf5ef2aSThomas Huth gen_op_eval_bgu(r_dst, r_src); 1218fcf5ef2aSThomas Huth break; 1219fcf5ef2aSThomas Huth case 0xd: 1220fcf5ef2aSThomas Huth gen_op_eval_bcc(r_dst, r_src); 1221fcf5ef2aSThomas Huth break; 1222fcf5ef2aSThomas Huth case 0xe: 1223fcf5ef2aSThomas Huth gen_op_eval_bpos(r_dst, r_src); 1224fcf5ef2aSThomas Huth break; 1225fcf5ef2aSThomas Huth case 0xf: 1226fcf5ef2aSThomas Huth gen_op_eval_bvc(r_dst, r_src); 1227fcf5ef2aSThomas Huth break; 1228fcf5ef2aSThomas Huth } 1229fcf5ef2aSThomas Huth break; 1230fcf5ef2aSThomas Huth } 1231fcf5ef2aSThomas Huth } 1232fcf5ef2aSThomas Huth 1233fcf5ef2aSThomas Huth static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) 1234fcf5ef2aSThomas Huth { 1235fcf5ef2aSThomas Huth unsigned int offset; 1236fcf5ef2aSThomas Huth TCGv r_dst; 1237fcf5ef2aSThomas Huth 1238fcf5ef2aSThomas Huth /* For now we still generate a straight boolean result. */ 1239fcf5ef2aSThomas Huth cmp->cond = TCG_COND_NE; 1240fcf5ef2aSThomas Huth cmp->is_bool = true; 1241fcf5ef2aSThomas Huth cmp->c1 = r_dst = tcg_temp_new(); 124200ab7e61SRichard Henderson cmp->c2 = tcg_constant_tl(0); 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth switch (cc) { 1245fcf5ef2aSThomas Huth default: 1246fcf5ef2aSThomas Huth case 0x0: 1247fcf5ef2aSThomas Huth offset = 0; 1248fcf5ef2aSThomas Huth break; 1249fcf5ef2aSThomas Huth case 0x1: 1250fcf5ef2aSThomas Huth offset = 32 - 10; 1251fcf5ef2aSThomas Huth break; 1252fcf5ef2aSThomas Huth case 0x2: 1253fcf5ef2aSThomas Huth offset = 34 - 10; 1254fcf5ef2aSThomas Huth break; 1255fcf5ef2aSThomas Huth case 0x3: 1256fcf5ef2aSThomas Huth offset = 36 - 10; 1257fcf5ef2aSThomas Huth break; 1258fcf5ef2aSThomas Huth } 1259fcf5ef2aSThomas Huth 1260fcf5ef2aSThomas Huth switch (cond) { 1261fcf5ef2aSThomas Huth case 0x0: 1262fcf5ef2aSThomas Huth gen_op_eval_bn(r_dst); 1263fcf5ef2aSThomas Huth break; 1264fcf5ef2aSThomas Huth case 0x1: 1265fcf5ef2aSThomas Huth gen_op_eval_fbne(r_dst, cpu_fsr, offset); 1266fcf5ef2aSThomas Huth break; 1267fcf5ef2aSThomas Huth case 0x2: 1268fcf5ef2aSThomas Huth gen_op_eval_fblg(r_dst, cpu_fsr, offset); 1269fcf5ef2aSThomas Huth break; 1270fcf5ef2aSThomas Huth case 0x3: 1271fcf5ef2aSThomas Huth gen_op_eval_fbul(r_dst, cpu_fsr, offset); 1272fcf5ef2aSThomas Huth break; 1273fcf5ef2aSThomas Huth case 0x4: 1274fcf5ef2aSThomas Huth gen_op_eval_fbl(r_dst, cpu_fsr, offset); 1275fcf5ef2aSThomas Huth break; 1276fcf5ef2aSThomas Huth case 0x5: 1277fcf5ef2aSThomas Huth gen_op_eval_fbug(r_dst, cpu_fsr, offset); 1278fcf5ef2aSThomas Huth break; 1279fcf5ef2aSThomas Huth case 0x6: 1280fcf5ef2aSThomas Huth gen_op_eval_fbg(r_dst, cpu_fsr, offset); 1281fcf5ef2aSThomas Huth break; 1282fcf5ef2aSThomas Huth case 0x7: 1283fcf5ef2aSThomas Huth gen_op_eval_fbu(r_dst, cpu_fsr, offset); 1284fcf5ef2aSThomas Huth break; 1285fcf5ef2aSThomas Huth case 0x8: 1286fcf5ef2aSThomas Huth gen_op_eval_ba(r_dst); 1287fcf5ef2aSThomas Huth break; 1288fcf5ef2aSThomas Huth case 0x9: 1289fcf5ef2aSThomas Huth gen_op_eval_fbe(r_dst, cpu_fsr, offset); 1290fcf5ef2aSThomas Huth break; 1291fcf5ef2aSThomas Huth case 0xa: 1292fcf5ef2aSThomas Huth gen_op_eval_fbue(r_dst, cpu_fsr, offset); 1293fcf5ef2aSThomas Huth break; 1294fcf5ef2aSThomas Huth case 0xb: 1295fcf5ef2aSThomas Huth gen_op_eval_fbge(r_dst, cpu_fsr, offset); 1296fcf5ef2aSThomas Huth break; 1297fcf5ef2aSThomas Huth case 0xc: 1298fcf5ef2aSThomas Huth gen_op_eval_fbuge(r_dst, cpu_fsr, offset); 1299fcf5ef2aSThomas Huth break; 1300fcf5ef2aSThomas Huth case 0xd: 1301fcf5ef2aSThomas Huth gen_op_eval_fble(r_dst, cpu_fsr, offset); 1302fcf5ef2aSThomas Huth break; 1303fcf5ef2aSThomas Huth case 0xe: 1304fcf5ef2aSThomas Huth gen_op_eval_fbule(r_dst, cpu_fsr, offset); 1305fcf5ef2aSThomas Huth break; 1306fcf5ef2aSThomas Huth case 0xf: 1307fcf5ef2aSThomas Huth gen_op_eval_fbo(r_dst, cpu_fsr, offset); 1308fcf5ef2aSThomas Huth break; 1309fcf5ef2aSThomas Huth } 1310fcf5ef2aSThomas Huth } 1311fcf5ef2aSThomas Huth 1312fcf5ef2aSThomas Huth static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, 1313fcf5ef2aSThomas Huth DisasContext *dc) 1314fcf5ef2aSThomas Huth { 1315fcf5ef2aSThomas Huth DisasCompare cmp; 1316fcf5ef2aSThomas Huth gen_compare(&cmp, cc, cond, dc); 1317fcf5ef2aSThomas Huth 1318fcf5ef2aSThomas Huth /* The interface is to return a boolean in r_dst. */ 1319fcf5ef2aSThomas Huth if (cmp.is_bool) { 1320fcf5ef2aSThomas Huth tcg_gen_mov_tl(r_dst, cmp.c1); 1321fcf5ef2aSThomas Huth } else { 1322fcf5ef2aSThomas Huth tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); 1323fcf5ef2aSThomas Huth } 1324fcf5ef2aSThomas Huth } 1325fcf5ef2aSThomas Huth 1326fcf5ef2aSThomas Huth static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) 1327fcf5ef2aSThomas Huth { 1328fcf5ef2aSThomas Huth DisasCompare cmp; 1329fcf5ef2aSThomas Huth gen_fcompare(&cmp, cc, cond); 1330fcf5ef2aSThomas Huth 1331fcf5ef2aSThomas Huth /* The interface is to return a boolean in r_dst. */ 1332fcf5ef2aSThomas Huth if (cmp.is_bool) { 1333fcf5ef2aSThomas Huth tcg_gen_mov_tl(r_dst, cmp.c1); 1334fcf5ef2aSThomas Huth } else { 1335fcf5ef2aSThomas Huth tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); 1336fcf5ef2aSThomas Huth } 1337fcf5ef2aSThomas Huth } 1338fcf5ef2aSThomas Huth 1339fcf5ef2aSThomas Huth // Inverted logic 1340*ab9ffe98SRichard Henderson static const TCGCond gen_tcg_cond_reg[8] = { 1341*ab9ffe98SRichard Henderson TCG_COND_NEVER, /* reserved */ 1342fcf5ef2aSThomas Huth TCG_COND_NE, 1343fcf5ef2aSThomas Huth TCG_COND_GT, 1344fcf5ef2aSThomas Huth TCG_COND_GE, 1345*ab9ffe98SRichard Henderson TCG_COND_NEVER, /* reserved */ 1346fcf5ef2aSThomas Huth TCG_COND_EQ, 1347fcf5ef2aSThomas Huth TCG_COND_LE, 1348fcf5ef2aSThomas Huth TCG_COND_LT, 1349fcf5ef2aSThomas Huth }; 1350fcf5ef2aSThomas Huth 1351fcf5ef2aSThomas Huth static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) 1352fcf5ef2aSThomas Huth { 1353fcf5ef2aSThomas Huth cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]); 1354fcf5ef2aSThomas Huth cmp->is_bool = false; 1355fcf5ef2aSThomas Huth cmp->c1 = r_src; 135600ab7e61SRichard Henderson cmp->c2 = tcg_constant_tl(0); 1357fcf5ef2aSThomas Huth } 1358fcf5ef2aSThomas Huth 1359fcf5ef2aSThomas Huth static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) 1360fcf5ef2aSThomas Huth { 1361fcf5ef2aSThomas Huth unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); 1362fcf5ef2aSThomas Huth target_ulong target = dc->pc + offset; 1363fcf5ef2aSThomas Huth 1364fcf5ef2aSThomas Huth if (unlikely(AM_CHECK(dc))) { 1365fcf5ef2aSThomas Huth target &= 0xffffffffULL; 1366fcf5ef2aSThomas Huth } 1367fcf5ef2aSThomas Huth if (cond == 0x0) { 1368fcf5ef2aSThomas Huth /* unconditional not taken */ 1369fcf5ef2aSThomas Huth if (a) { 1370fcf5ef2aSThomas Huth dc->pc = dc->npc + 4; 1371fcf5ef2aSThomas Huth dc->npc = dc->pc + 4; 1372fcf5ef2aSThomas Huth } else { 1373fcf5ef2aSThomas Huth dc->pc = dc->npc; 1374fcf5ef2aSThomas Huth dc->npc = dc->pc + 4; 1375fcf5ef2aSThomas Huth } 1376fcf5ef2aSThomas Huth } else if (cond == 0x8) { 1377fcf5ef2aSThomas Huth /* unconditional taken */ 1378fcf5ef2aSThomas Huth if (a) { 1379fcf5ef2aSThomas Huth dc->pc = target; 1380fcf5ef2aSThomas Huth dc->npc = dc->pc + 4; 1381fcf5ef2aSThomas Huth } else { 1382fcf5ef2aSThomas Huth dc->pc = dc->npc; 1383fcf5ef2aSThomas Huth dc->npc = target; 1384fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_pc, cpu_npc); 1385fcf5ef2aSThomas Huth } 1386fcf5ef2aSThomas Huth } else { 1387fcf5ef2aSThomas Huth flush_cond(dc); 1388fcf5ef2aSThomas Huth gen_fcond(cpu_cond, cc, cond); 1389fcf5ef2aSThomas Huth if (a) { 1390fcf5ef2aSThomas Huth gen_branch_a(dc, target); 1391fcf5ef2aSThomas Huth } else { 1392fcf5ef2aSThomas Huth gen_branch_n(dc, target); 1393fcf5ef2aSThomas Huth } 1394fcf5ef2aSThomas Huth } 1395fcf5ef2aSThomas Huth } 1396fcf5ef2aSThomas Huth 1397fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 13980c2e96c1SRichard Henderson static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) 1399fcf5ef2aSThomas Huth { 1400fcf5ef2aSThomas Huth switch (fccno) { 1401fcf5ef2aSThomas Huth case 0: 1402ad75a51eSRichard Henderson gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); 1403fcf5ef2aSThomas Huth break; 1404fcf5ef2aSThomas Huth case 1: 1405ad75a51eSRichard Henderson gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); 1406fcf5ef2aSThomas Huth break; 1407fcf5ef2aSThomas Huth case 2: 1408ad75a51eSRichard Henderson gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); 1409fcf5ef2aSThomas Huth break; 1410fcf5ef2aSThomas Huth case 3: 1411ad75a51eSRichard Henderson gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); 1412fcf5ef2aSThomas Huth break; 1413fcf5ef2aSThomas Huth } 1414fcf5ef2aSThomas Huth } 1415fcf5ef2aSThomas Huth 14160c2e96c1SRichard Henderson static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1417fcf5ef2aSThomas Huth { 1418fcf5ef2aSThomas Huth switch (fccno) { 1419fcf5ef2aSThomas Huth case 0: 1420ad75a51eSRichard Henderson gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); 1421fcf5ef2aSThomas Huth break; 1422fcf5ef2aSThomas Huth case 1: 1423ad75a51eSRichard Henderson gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); 1424fcf5ef2aSThomas Huth break; 1425fcf5ef2aSThomas Huth case 2: 1426ad75a51eSRichard Henderson gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); 1427fcf5ef2aSThomas Huth break; 1428fcf5ef2aSThomas Huth case 3: 1429ad75a51eSRichard Henderson gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); 1430fcf5ef2aSThomas Huth break; 1431fcf5ef2aSThomas Huth } 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth 14340c2e96c1SRichard Henderson static void gen_op_fcmpq(int fccno) 1435fcf5ef2aSThomas Huth { 1436fcf5ef2aSThomas Huth switch (fccno) { 1437fcf5ef2aSThomas Huth case 0: 1438ad75a51eSRichard Henderson gen_helper_fcmpq(cpu_fsr, tcg_env); 1439fcf5ef2aSThomas Huth break; 1440fcf5ef2aSThomas Huth case 1: 1441ad75a51eSRichard Henderson gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env); 1442fcf5ef2aSThomas Huth break; 1443fcf5ef2aSThomas Huth case 2: 1444ad75a51eSRichard Henderson gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env); 1445fcf5ef2aSThomas Huth break; 1446fcf5ef2aSThomas Huth case 3: 1447ad75a51eSRichard Henderson gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env); 1448fcf5ef2aSThomas Huth break; 1449fcf5ef2aSThomas Huth } 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth 14520c2e96c1SRichard Henderson static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) 1453fcf5ef2aSThomas Huth { 1454fcf5ef2aSThomas Huth switch (fccno) { 1455fcf5ef2aSThomas Huth case 0: 1456ad75a51eSRichard Henderson gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); 1457fcf5ef2aSThomas Huth break; 1458fcf5ef2aSThomas Huth case 1: 1459ad75a51eSRichard Henderson gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); 1460fcf5ef2aSThomas Huth break; 1461fcf5ef2aSThomas Huth case 2: 1462ad75a51eSRichard Henderson gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); 1463fcf5ef2aSThomas Huth break; 1464fcf5ef2aSThomas Huth case 3: 1465ad75a51eSRichard Henderson gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); 1466fcf5ef2aSThomas Huth break; 1467fcf5ef2aSThomas Huth } 1468fcf5ef2aSThomas Huth } 1469fcf5ef2aSThomas Huth 14700c2e96c1SRichard Henderson static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1471fcf5ef2aSThomas Huth { 1472fcf5ef2aSThomas Huth switch (fccno) { 1473fcf5ef2aSThomas Huth case 0: 1474ad75a51eSRichard Henderson gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); 1475fcf5ef2aSThomas Huth break; 1476fcf5ef2aSThomas Huth case 1: 1477ad75a51eSRichard Henderson gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); 1478fcf5ef2aSThomas Huth break; 1479fcf5ef2aSThomas Huth case 2: 1480ad75a51eSRichard Henderson gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); 1481fcf5ef2aSThomas Huth break; 1482fcf5ef2aSThomas Huth case 3: 1483ad75a51eSRichard Henderson gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); 1484fcf5ef2aSThomas Huth break; 1485fcf5ef2aSThomas Huth } 1486fcf5ef2aSThomas Huth } 1487fcf5ef2aSThomas Huth 14880c2e96c1SRichard Henderson static void gen_op_fcmpeq(int fccno) 1489fcf5ef2aSThomas Huth { 1490fcf5ef2aSThomas Huth switch (fccno) { 1491fcf5ef2aSThomas Huth case 0: 1492ad75a51eSRichard Henderson gen_helper_fcmpeq(cpu_fsr, tcg_env); 1493fcf5ef2aSThomas Huth break; 1494fcf5ef2aSThomas Huth case 1: 1495ad75a51eSRichard Henderson gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env); 1496fcf5ef2aSThomas Huth break; 1497fcf5ef2aSThomas Huth case 2: 1498ad75a51eSRichard Henderson gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env); 1499fcf5ef2aSThomas Huth break; 1500fcf5ef2aSThomas Huth case 3: 1501ad75a51eSRichard Henderson gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env); 1502fcf5ef2aSThomas Huth break; 1503fcf5ef2aSThomas Huth } 1504fcf5ef2aSThomas Huth } 1505fcf5ef2aSThomas Huth 1506fcf5ef2aSThomas Huth #else 1507fcf5ef2aSThomas Huth 15080c2e96c1SRichard Henderson static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) 1509fcf5ef2aSThomas Huth { 1510ad75a51eSRichard Henderson gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); 1511fcf5ef2aSThomas Huth } 1512fcf5ef2aSThomas Huth 15130c2e96c1SRichard Henderson static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1514fcf5ef2aSThomas Huth { 1515ad75a51eSRichard Henderson gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); 1516fcf5ef2aSThomas Huth } 1517fcf5ef2aSThomas Huth 15180c2e96c1SRichard Henderson static void gen_op_fcmpq(int fccno) 1519fcf5ef2aSThomas Huth { 1520ad75a51eSRichard Henderson gen_helper_fcmpq(cpu_fsr, tcg_env); 1521fcf5ef2aSThomas Huth } 1522fcf5ef2aSThomas Huth 15230c2e96c1SRichard Henderson static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) 1524fcf5ef2aSThomas Huth { 1525ad75a51eSRichard Henderson gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); 1526fcf5ef2aSThomas Huth } 1527fcf5ef2aSThomas Huth 15280c2e96c1SRichard Henderson static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1529fcf5ef2aSThomas Huth { 1530ad75a51eSRichard Henderson gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); 1531fcf5ef2aSThomas Huth } 1532fcf5ef2aSThomas Huth 15330c2e96c1SRichard Henderson static void gen_op_fcmpeq(int fccno) 1534fcf5ef2aSThomas Huth { 1535ad75a51eSRichard Henderson gen_helper_fcmpeq(cpu_fsr, tcg_env); 1536fcf5ef2aSThomas Huth } 1537fcf5ef2aSThomas Huth #endif 1538fcf5ef2aSThomas Huth 1539fcf5ef2aSThomas Huth static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags) 1540fcf5ef2aSThomas Huth { 1541fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); 1542fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); 1543fcf5ef2aSThomas Huth gen_exception(dc, TT_FP_EXCP); 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth static int gen_trap_ifnofpu(DisasContext *dc) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1549fcf5ef2aSThomas Huth if (!dc->fpu_enabled) { 1550fcf5ef2aSThomas Huth gen_exception(dc, TT_NFPU_INSN); 1551fcf5ef2aSThomas Huth return 1; 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth #endif 1554fcf5ef2aSThomas Huth return 0; 1555fcf5ef2aSThomas Huth } 1556fcf5ef2aSThomas Huth 15570c2e96c1SRichard Henderson static void gen_op_clear_ieee_excp_and_FTT(void) 1558fcf5ef2aSThomas Huth { 1559fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); 1560fcf5ef2aSThomas Huth } 1561fcf5ef2aSThomas Huth 15620c2e96c1SRichard Henderson static void gen_fop_FF(DisasContext *dc, int rd, int rs, 1563fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) 1564fcf5ef2aSThomas Huth { 1565fcf5ef2aSThomas Huth TCGv_i32 dst, src; 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth src = gen_load_fpr_F(dc, rs); 1568fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1569fcf5ef2aSThomas Huth 1570ad75a51eSRichard Henderson gen(dst, tcg_env, src); 1571ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1572fcf5ef2aSThomas Huth 1573fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1574fcf5ef2aSThomas Huth } 1575fcf5ef2aSThomas Huth 15760c2e96c1SRichard Henderson static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, 1577fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_i32)) 1578fcf5ef2aSThomas Huth { 1579fcf5ef2aSThomas Huth TCGv_i32 dst, src; 1580fcf5ef2aSThomas Huth 1581fcf5ef2aSThomas Huth src = gen_load_fpr_F(dc, rs); 1582fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1583fcf5ef2aSThomas Huth 1584fcf5ef2aSThomas Huth gen(dst, src); 1585fcf5ef2aSThomas Huth 1586fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1587fcf5ef2aSThomas Huth } 1588fcf5ef2aSThomas Huth 15890c2e96c1SRichard Henderson static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, 1590fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) 1591fcf5ef2aSThomas Huth { 1592fcf5ef2aSThomas Huth TCGv_i32 dst, src1, src2; 1593fcf5ef2aSThomas Huth 1594fcf5ef2aSThomas Huth src1 = gen_load_fpr_F(dc, rs1); 1595fcf5ef2aSThomas Huth src2 = gen_load_fpr_F(dc, rs2); 1596fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1597fcf5ef2aSThomas Huth 1598ad75a51eSRichard Henderson gen(dst, tcg_env, src1, src2); 1599ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1602fcf5ef2aSThomas Huth } 1603fcf5ef2aSThomas Huth 1604fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 16050c2e96c1SRichard Henderson static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, 1606fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) 1607fcf5ef2aSThomas Huth { 1608fcf5ef2aSThomas Huth TCGv_i32 dst, src1, src2; 1609fcf5ef2aSThomas Huth 1610fcf5ef2aSThomas Huth src1 = gen_load_fpr_F(dc, rs1); 1611fcf5ef2aSThomas Huth src2 = gen_load_fpr_F(dc, rs2); 1612fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1613fcf5ef2aSThomas Huth 1614fcf5ef2aSThomas Huth gen(dst, src1, src2); 1615fcf5ef2aSThomas Huth 1616fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1617fcf5ef2aSThomas Huth } 1618fcf5ef2aSThomas Huth #endif 1619fcf5ef2aSThomas Huth 16200c2e96c1SRichard Henderson static void gen_fop_DD(DisasContext *dc, int rd, int rs, 1621fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) 1622fcf5ef2aSThomas Huth { 1623fcf5ef2aSThomas Huth TCGv_i64 dst, src; 1624fcf5ef2aSThomas Huth 1625fcf5ef2aSThomas Huth src = gen_load_fpr_D(dc, rs); 1626fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1627fcf5ef2aSThomas Huth 1628ad75a51eSRichard Henderson gen(dst, tcg_env, src); 1629ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1630fcf5ef2aSThomas Huth 1631fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1632fcf5ef2aSThomas Huth } 1633fcf5ef2aSThomas Huth 1634fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 16350c2e96c1SRichard Henderson static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, 1636fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_i64)) 1637fcf5ef2aSThomas Huth { 1638fcf5ef2aSThomas Huth TCGv_i64 dst, src; 1639fcf5ef2aSThomas Huth 1640fcf5ef2aSThomas Huth src = gen_load_fpr_D(dc, rs); 1641fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth gen(dst, src); 1644fcf5ef2aSThomas Huth 1645fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1646fcf5ef2aSThomas Huth } 1647fcf5ef2aSThomas Huth #endif 1648fcf5ef2aSThomas Huth 16490c2e96c1SRichard Henderson static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1650fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) 1651fcf5ef2aSThomas Huth { 1652fcf5ef2aSThomas Huth TCGv_i64 dst, src1, src2; 1653fcf5ef2aSThomas Huth 1654fcf5ef2aSThomas Huth src1 = gen_load_fpr_D(dc, rs1); 1655fcf5ef2aSThomas Huth src2 = gen_load_fpr_D(dc, rs2); 1656fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1657fcf5ef2aSThomas Huth 1658ad75a51eSRichard Henderson gen(dst, tcg_env, src1, src2); 1659ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1660fcf5ef2aSThomas Huth 1661fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth 1664fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 16650c2e96c1SRichard Henderson static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1666fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) 1667fcf5ef2aSThomas Huth { 1668fcf5ef2aSThomas Huth TCGv_i64 dst, src1, src2; 1669fcf5ef2aSThomas Huth 1670fcf5ef2aSThomas Huth src1 = gen_load_fpr_D(dc, rs1); 1671fcf5ef2aSThomas Huth src2 = gen_load_fpr_D(dc, rs2); 1672fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1673fcf5ef2aSThomas Huth 1674fcf5ef2aSThomas Huth gen(dst, src1, src2); 1675fcf5ef2aSThomas Huth 1676fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 16790c2e96c1SRichard Henderson static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1680fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) 1681fcf5ef2aSThomas Huth { 1682fcf5ef2aSThomas Huth TCGv_i64 dst, src1, src2; 1683fcf5ef2aSThomas Huth 1684fcf5ef2aSThomas Huth src1 = gen_load_fpr_D(dc, rs1); 1685fcf5ef2aSThomas Huth src2 = gen_load_fpr_D(dc, rs2); 1686fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1687fcf5ef2aSThomas Huth 1688fcf5ef2aSThomas Huth gen(dst, cpu_gsr, src1, src2); 1689fcf5ef2aSThomas Huth 1690fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth 16930c2e96c1SRichard Henderson static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, 1694fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) 1695fcf5ef2aSThomas Huth { 1696fcf5ef2aSThomas Huth TCGv_i64 dst, src0, src1, src2; 1697fcf5ef2aSThomas Huth 1698fcf5ef2aSThomas Huth src1 = gen_load_fpr_D(dc, rs1); 1699fcf5ef2aSThomas Huth src2 = gen_load_fpr_D(dc, rs2); 1700fcf5ef2aSThomas Huth src0 = gen_load_fpr_D(dc, rd); 1701fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1702fcf5ef2aSThomas Huth 1703fcf5ef2aSThomas Huth gen(dst, src0, src1, src2); 1704fcf5ef2aSThomas Huth 1705fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1706fcf5ef2aSThomas Huth } 1707fcf5ef2aSThomas Huth #endif 1708fcf5ef2aSThomas Huth 17090c2e96c1SRichard Henderson static void gen_fop_QQ(DisasContext *dc, int rd, int rs, 1710fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr)) 1711fcf5ef2aSThomas Huth { 1712fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs)); 1713fcf5ef2aSThomas Huth 1714ad75a51eSRichard Henderson gen(tcg_env); 1715ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1716fcf5ef2aSThomas Huth 1717fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1718fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth 1721fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 17220c2e96c1SRichard Henderson static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, 1723fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr)) 1724fcf5ef2aSThomas Huth { 1725fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs)); 1726fcf5ef2aSThomas Huth 1727ad75a51eSRichard Henderson gen(tcg_env); 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1730fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1731fcf5ef2aSThomas Huth } 1732fcf5ef2aSThomas Huth #endif 1733fcf5ef2aSThomas Huth 17340c2e96c1SRichard Henderson static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, 1735fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr)) 1736fcf5ef2aSThomas Huth { 1737fcf5ef2aSThomas Huth gen_op_load_fpr_QT0(QFPREG(rs1)); 1738fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs2)); 1739fcf5ef2aSThomas Huth 1740ad75a51eSRichard Henderson gen(tcg_env); 1741ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1744fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 17470c2e96c1SRichard Henderson static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, 1748fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32)) 1749fcf5ef2aSThomas Huth { 1750fcf5ef2aSThomas Huth TCGv_i64 dst; 1751fcf5ef2aSThomas Huth TCGv_i32 src1, src2; 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth src1 = gen_load_fpr_F(dc, rs1); 1754fcf5ef2aSThomas Huth src2 = gen_load_fpr_F(dc, rs2); 1755fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1756fcf5ef2aSThomas Huth 1757ad75a51eSRichard Henderson gen(dst, tcg_env, src1, src2); 1758ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1759fcf5ef2aSThomas Huth 1760fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1761fcf5ef2aSThomas Huth } 1762fcf5ef2aSThomas Huth 17630c2e96c1SRichard Henderson static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, 1764fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) 1765fcf5ef2aSThomas Huth { 1766fcf5ef2aSThomas Huth TCGv_i64 src1, src2; 1767fcf5ef2aSThomas Huth 1768fcf5ef2aSThomas Huth src1 = gen_load_fpr_D(dc, rs1); 1769fcf5ef2aSThomas Huth src2 = gen_load_fpr_D(dc, rs2); 1770fcf5ef2aSThomas Huth 1771ad75a51eSRichard Henderson gen(tcg_env, src1, src2); 1772ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1773fcf5ef2aSThomas Huth 1774fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1775fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1776fcf5ef2aSThomas Huth } 1777fcf5ef2aSThomas Huth 1778fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 17790c2e96c1SRichard Henderson static void gen_fop_DF(DisasContext *dc, int rd, int rs, 1780fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) 1781fcf5ef2aSThomas Huth { 1782fcf5ef2aSThomas Huth TCGv_i64 dst; 1783fcf5ef2aSThomas Huth TCGv_i32 src; 1784fcf5ef2aSThomas Huth 1785fcf5ef2aSThomas Huth src = gen_load_fpr_F(dc, rs); 1786fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1787fcf5ef2aSThomas Huth 1788ad75a51eSRichard Henderson gen(dst, tcg_env, src); 1789ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1790fcf5ef2aSThomas Huth 1791fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1792fcf5ef2aSThomas Huth } 1793fcf5ef2aSThomas Huth #endif 1794fcf5ef2aSThomas Huth 17950c2e96c1SRichard Henderson static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, 1796fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) 1797fcf5ef2aSThomas Huth { 1798fcf5ef2aSThomas Huth TCGv_i64 dst; 1799fcf5ef2aSThomas Huth TCGv_i32 src; 1800fcf5ef2aSThomas Huth 1801fcf5ef2aSThomas Huth src = gen_load_fpr_F(dc, rs); 1802fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1803fcf5ef2aSThomas Huth 1804ad75a51eSRichard Henderson gen(dst, tcg_env, src); 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1807fcf5ef2aSThomas Huth } 1808fcf5ef2aSThomas Huth 18090c2e96c1SRichard Henderson static void gen_fop_FD(DisasContext *dc, int rd, int rs, 1810fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) 1811fcf5ef2aSThomas Huth { 1812fcf5ef2aSThomas Huth TCGv_i32 dst; 1813fcf5ef2aSThomas Huth TCGv_i64 src; 1814fcf5ef2aSThomas Huth 1815fcf5ef2aSThomas Huth src = gen_load_fpr_D(dc, rs); 1816fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1817fcf5ef2aSThomas Huth 1818ad75a51eSRichard Henderson gen(dst, tcg_env, src); 1819ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1820fcf5ef2aSThomas Huth 1821fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1822fcf5ef2aSThomas Huth } 1823fcf5ef2aSThomas Huth 18240c2e96c1SRichard Henderson static void gen_fop_FQ(DisasContext *dc, int rd, int rs, 1825fcf5ef2aSThomas Huth void (*gen)(TCGv_i32, TCGv_ptr)) 1826fcf5ef2aSThomas Huth { 1827fcf5ef2aSThomas Huth TCGv_i32 dst; 1828fcf5ef2aSThomas Huth 1829fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs)); 1830fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 1831fcf5ef2aSThomas Huth 1832ad75a51eSRichard Henderson gen(dst, tcg_env); 1833ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1834fcf5ef2aSThomas Huth 1835fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 1836fcf5ef2aSThomas Huth } 1837fcf5ef2aSThomas Huth 18380c2e96c1SRichard Henderson static void gen_fop_DQ(DisasContext *dc, int rd, int rs, 1839fcf5ef2aSThomas Huth void (*gen)(TCGv_i64, TCGv_ptr)) 1840fcf5ef2aSThomas Huth { 1841fcf5ef2aSThomas Huth TCGv_i64 dst; 1842fcf5ef2aSThomas Huth 1843fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs)); 1844fcf5ef2aSThomas Huth dst = gen_dest_fpr_D(dc, rd); 1845fcf5ef2aSThomas Huth 1846ad75a51eSRichard Henderson gen(dst, tcg_env); 1847ad75a51eSRichard Henderson gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 1848fcf5ef2aSThomas Huth 1849fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 1850fcf5ef2aSThomas Huth } 1851fcf5ef2aSThomas Huth 18520c2e96c1SRichard Henderson static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, 1853fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr, TCGv_i32)) 1854fcf5ef2aSThomas Huth { 1855fcf5ef2aSThomas Huth TCGv_i32 src; 1856fcf5ef2aSThomas Huth 1857fcf5ef2aSThomas Huth src = gen_load_fpr_F(dc, rs); 1858fcf5ef2aSThomas Huth 1859ad75a51eSRichard Henderson gen(tcg_env, src); 1860fcf5ef2aSThomas Huth 1861fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1862fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1863fcf5ef2aSThomas Huth } 1864fcf5ef2aSThomas Huth 18650c2e96c1SRichard Henderson static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, 1866fcf5ef2aSThomas Huth void (*gen)(TCGv_ptr, TCGv_i64)) 1867fcf5ef2aSThomas Huth { 1868fcf5ef2aSThomas Huth TCGv_i64 src; 1869fcf5ef2aSThomas Huth 1870fcf5ef2aSThomas Huth src = gen_load_fpr_D(dc, rs); 1871fcf5ef2aSThomas Huth 1872ad75a51eSRichard Henderson gen(tcg_env, src); 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth gen_op_store_QT0_fpr(QFPREG(rd)); 1875fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, 187914776ab5STony Nguyen TCGv addr, int mmu_idx, MemOp memop) 1880fcf5ef2aSThomas Huth { 1881fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 1882316b6783SRichard Henderson tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); 1883fcf5ef2aSThomas Huth } 1884fcf5ef2aSThomas Huth 1885fcf5ef2aSThomas Huth static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) 1886fcf5ef2aSThomas Huth { 188700ab7e61SRichard Henderson TCGv m1 = tcg_constant_tl(0xff); 1888fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 1889fcf5ef2aSThomas Huth tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); 1890fcf5ef2aSThomas Huth } 1891fcf5ef2aSThomas Huth 1892fcf5ef2aSThomas Huth /* asi moves */ 1893fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 1894fcf5ef2aSThomas Huth typedef enum { 1895fcf5ef2aSThomas Huth GET_ASI_HELPER, 1896fcf5ef2aSThomas Huth GET_ASI_EXCP, 1897fcf5ef2aSThomas Huth GET_ASI_DIRECT, 1898fcf5ef2aSThomas Huth GET_ASI_DTWINX, 1899fcf5ef2aSThomas Huth GET_ASI_BLOCK, 1900fcf5ef2aSThomas Huth GET_ASI_SHORT, 1901fcf5ef2aSThomas Huth GET_ASI_BCOPY, 1902fcf5ef2aSThomas Huth GET_ASI_BFILL, 1903fcf5ef2aSThomas Huth } ASIType; 1904fcf5ef2aSThomas Huth 1905fcf5ef2aSThomas Huth typedef struct { 1906fcf5ef2aSThomas Huth ASIType type; 1907fcf5ef2aSThomas Huth int asi; 1908fcf5ef2aSThomas Huth int mem_idx; 190914776ab5STony Nguyen MemOp memop; 1910fcf5ef2aSThomas Huth } DisasASI; 1911fcf5ef2aSThomas Huth 191214776ab5STony Nguyen static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) 1913fcf5ef2aSThomas Huth { 1914fcf5ef2aSThomas Huth int asi = GET_FIELD(insn, 19, 26); 1915fcf5ef2aSThomas Huth ASIType type = GET_ASI_HELPER; 1916fcf5ef2aSThomas Huth int mem_idx = dc->mem_idx; 1917fcf5ef2aSThomas Huth 1918fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 1919fcf5ef2aSThomas Huth /* Before v9, all asis are immediate and privileged. */ 1920fcf5ef2aSThomas Huth if (IS_IMM) { 1921fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 1922fcf5ef2aSThomas Huth type = GET_ASI_EXCP; 1923fcf5ef2aSThomas Huth } else if (supervisor(dc) 1924fcf5ef2aSThomas Huth /* Note that LEON accepts ASI_USERDATA in user mode, for 1925fcf5ef2aSThomas Huth use with CASA. Also note that previous versions of 1926fcf5ef2aSThomas Huth QEMU allowed (and old versions of gcc emitted) ASI_P 1927fcf5ef2aSThomas Huth for LEON, which is incorrect. */ 1928fcf5ef2aSThomas Huth || (asi == ASI_USERDATA 1929fcf5ef2aSThomas Huth && (dc->def->features & CPU_FEATURE_CASA))) { 1930fcf5ef2aSThomas Huth switch (asi) { 1931fcf5ef2aSThomas Huth case ASI_USERDATA: /* User data access */ 1932fcf5ef2aSThomas Huth mem_idx = MMU_USER_IDX; 1933fcf5ef2aSThomas Huth type = GET_ASI_DIRECT; 1934fcf5ef2aSThomas Huth break; 1935fcf5ef2aSThomas Huth case ASI_KERNELDATA: /* Supervisor data access */ 1936fcf5ef2aSThomas Huth mem_idx = MMU_KERNEL_IDX; 1937fcf5ef2aSThomas Huth type = GET_ASI_DIRECT; 1938fcf5ef2aSThomas Huth break; 1939fcf5ef2aSThomas Huth case ASI_M_BYPASS: /* MMU passthrough */ 1940fcf5ef2aSThomas Huth case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1941fcf5ef2aSThomas Huth mem_idx = MMU_PHYS_IDX; 1942fcf5ef2aSThomas Huth type = GET_ASI_DIRECT; 1943fcf5ef2aSThomas Huth break; 1944fcf5ef2aSThomas Huth case ASI_M_BCOPY: /* Block copy, sta access */ 1945fcf5ef2aSThomas Huth mem_idx = MMU_KERNEL_IDX; 1946fcf5ef2aSThomas Huth type = GET_ASI_BCOPY; 1947fcf5ef2aSThomas Huth break; 1948fcf5ef2aSThomas Huth case ASI_M_BFILL: /* Block fill, stda access */ 1949fcf5ef2aSThomas Huth mem_idx = MMU_KERNEL_IDX; 1950fcf5ef2aSThomas Huth type = GET_ASI_BFILL; 1951fcf5ef2aSThomas Huth break; 1952fcf5ef2aSThomas Huth } 19536e10f37cSKONRAD Frederic 19546e10f37cSKONRAD Frederic /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the 19556e10f37cSKONRAD Frederic * permissions check in get_physical_address(..). 19566e10f37cSKONRAD Frederic */ 19576e10f37cSKONRAD Frederic mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx; 1958fcf5ef2aSThomas Huth } else { 1959fcf5ef2aSThomas Huth gen_exception(dc, TT_PRIV_INSN); 1960fcf5ef2aSThomas Huth type = GET_ASI_EXCP; 1961fcf5ef2aSThomas Huth } 1962fcf5ef2aSThomas Huth #else 1963fcf5ef2aSThomas Huth if (IS_IMM) { 1964fcf5ef2aSThomas Huth asi = dc->asi; 1965fcf5ef2aSThomas Huth } 1966fcf5ef2aSThomas Huth /* With v9, all asis below 0x80 are privileged. */ 1967fcf5ef2aSThomas Huth /* ??? We ought to check cpu_has_hypervisor, but we didn't copy 1968fcf5ef2aSThomas Huth down that bit into DisasContext. For the moment that's ok, 1969fcf5ef2aSThomas Huth since the direct implementations below doesn't have any ASIs 1970fcf5ef2aSThomas Huth in the restricted [0x30, 0x7f] range, and the check will be 1971fcf5ef2aSThomas Huth done properly in the helper. */ 1972fcf5ef2aSThomas Huth if (!supervisor(dc) && asi < 0x80) { 1973fcf5ef2aSThomas Huth gen_exception(dc, TT_PRIV_ACT); 1974fcf5ef2aSThomas Huth type = GET_ASI_EXCP; 1975fcf5ef2aSThomas Huth } else { 1976fcf5ef2aSThomas Huth switch (asi) { 1977fcf5ef2aSThomas Huth case ASI_REAL: /* Bypass */ 1978fcf5ef2aSThomas Huth case ASI_REAL_IO: /* Bypass, non-cacheable */ 1979fcf5ef2aSThomas Huth case ASI_REAL_L: /* Bypass LE */ 1980fcf5ef2aSThomas Huth case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1981fcf5ef2aSThomas Huth case ASI_TWINX_REAL: /* Real address, twinx */ 1982fcf5ef2aSThomas Huth case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1983fcf5ef2aSThomas Huth case ASI_QUAD_LDD_PHYS: 1984fcf5ef2aSThomas Huth case ASI_QUAD_LDD_PHYS_L: 1985fcf5ef2aSThomas Huth mem_idx = MMU_PHYS_IDX; 1986fcf5ef2aSThomas Huth break; 1987fcf5ef2aSThomas Huth case ASI_N: /* Nucleus */ 1988fcf5ef2aSThomas Huth case ASI_NL: /* Nucleus LE */ 1989fcf5ef2aSThomas Huth case ASI_TWINX_N: 1990fcf5ef2aSThomas Huth case ASI_TWINX_NL: 1991fcf5ef2aSThomas Huth case ASI_NUCLEUS_QUAD_LDD: 1992fcf5ef2aSThomas Huth case ASI_NUCLEUS_QUAD_LDD_L: 19939a10756dSArtyom Tarasenko if (hypervisor(dc)) { 199484f8f587SArtyom Tarasenko mem_idx = MMU_PHYS_IDX; 19959a10756dSArtyom Tarasenko } else { 1996fcf5ef2aSThomas Huth mem_idx = MMU_NUCLEUS_IDX; 19979a10756dSArtyom Tarasenko } 1998fcf5ef2aSThomas Huth break; 1999fcf5ef2aSThomas Huth case ASI_AIUP: /* As if user primary */ 2000fcf5ef2aSThomas Huth case ASI_AIUPL: /* As if user primary LE */ 2001fcf5ef2aSThomas Huth case ASI_TWINX_AIUP: 2002fcf5ef2aSThomas Huth case ASI_TWINX_AIUP_L: 2003fcf5ef2aSThomas Huth case ASI_BLK_AIUP_4V: 2004fcf5ef2aSThomas Huth case ASI_BLK_AIUP_L_4V: 2005fcf5ef2aSThomas Huth case ASI_BLK_AIUP: 2006fcf5ef2aSThomas Huth case ASI_BLK_AIUPL: 2007fcf5ef2aSThomas Huth mem_idx = MMU_USER_IDX; 2008fcf5ef2aSThomas Huth break; 2009fcf5ef2aSThomas Huth case ASI_AIUS: /* As if user secondary */ 2010fcf5ef2aSThomas Huth case ASI_AIUSL: /* As if user secondary LE */ 2011fcf5ef2aSThomas Huth case ASI_TWINX_AIUS: 2012fcf5ef2aSThomas Huth case ASI_TWINX_AIUS_L: 2013fcf5ef2aSThomas Huth case ASI_BLK_AIUS_4V: 2014fcf5ef2aSThomas Huth case ASI_BLK_AIUS_L_4V: 2015fcf5ef2aSThomas Huth case ASI_BLK_AIUS: 2016fcf5ef2aSThomas Huth case ASI_BLK_AIUSL: 2017fcf5ef2aSThomas Huth mem_idx = MMU_USER_SECONDARY_IDX; 2018fcf5ef2aSThomas Huth break; 2019fcf5ef2aSThomas Huth case ASI_S: /* Secondary */ 2020fcf5ef2aSThomas Huth case ASI_SL: /* Secondary LE */ 2021fcf5ef2aSThomas Huth case ASI_TWINX_S: 2022fcf5ef2aSThomas Huth case ASI_TWINX_SL: 2023fcf5ef2aSThomas Huth case ASI_BLK_COMMIT_S: 2024fcf5ef2aSThomas Huth case ASI_BLK_S: 2025fcf5ef2aSThomas Huth case ASI_BLK_SL: 2026fcf5ef2aSThomas Huth case ASI_FL8_S: 2027fcf5ef2aSThomas Huth case ASI_FL8_SL: 2028fcf5ef2aSThomas Huth case ASI_FL16_S: 2029fcf5ef2aSThomas Huth case ASI_FL16_SL: 2030fcf5ef2aSThomas Huth if (mem_idx == MMU_USER_IDX) { 2031fcf5ef2aSThomas Huth mem_idx = MMU_USER_SECONDARY_IDX; 2032fcf5ef2aSThomas Huth } else if (mem_idx == MMU_KERNEL_IDX) { 2033fcf5ef2aSThomas Huth mem_idx = MMU_KERNEL_SECONDARY_IDX; 2034fcf5ef2aSThomas Huth } 2035fcf5ef2aSThomas Huth break; 2036fcf5ef2aSThomas Huth case ASI_P: /* Primary */ 2037fcf5ef2aSThomas Huth case ASI_PL: /* Primary LE */ 2038fcf5ef2aSThomas Huth case ASI_TWINX_P: 2039fcf5ef2aSThomas Huth case ASI_TWINX_PL: 2040fcf5ef2aSThomas Huth case ASI_BLK_COMMIT_P: 2041fcf5ef2aSThomas Huth case ASI_BLK_P: 2042fcf5ef2aSThomas Huth case ASI_BLK_PL: 2043fcf5ef2aSThomas Huth case ASI_FL8_P: 2044fcf5ef2aSThomas Huth case ASI_FL8_PL: 2045fcf5ef2aSThomas Huth case ASI_FL16_P: 2046fcf5ef2aSThomas Huth case ASI_FL16_PL: 2047fcf5ef2aSThomas Huth break; 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth switch (asi) { 2050fcf5ef2aSThomas Huth case ASI_REAL: 2051fcf5ef2aSThomas Huth case ASI_REAL_IO: 2052fcf5ef2aSThomas Huth case ASI_REAL_L: 2053fcf5ef2aSThomas Huth case ASI_REAL_IO_L: 2054fcf5ef2aSThomas Huth case ASI_N: 2055fcf5ef2aSThomas Huth case ASI_NL: 2056fcf5ef2aSThomas Huth case ASI_AIUP: 2057fcf5ef2aSThomas Huth case ASI_AIUPL: 2058fcf5ef2aSThomas Huth case ASI_AIUS: 2059fcf5ef2aSThomas Huth case ASI_AIUSL: 2060fcf5ef2aSThomas Huth case ASI_S: 2061fcf5ef2aSThomas Huth case ASI_SL: 2062fcf5ef2aSThomas Huth case ASI_P: 2063fcf5ef2aSThomas Huth case ASI_PL: 2064fcf5ef2aSThomas Huth type = GET_ASI_DIRECT; 2065fcf5ef2aSThomas Huth break; 2066fcf5ef2aSThomas Huth case ASI_TWINX_REAL: 2067fcf5ef2aSThomas Huth case ASI_TWINX_REAL_L: 2068fcf5ef2aSThomas Huth case ASI_TWINX_N: 2069fcf5ef2aSThomas Huth case ASI_TWINX_NL: 2070fcf5ef2aSThomas Huth case ASI_TWINX_AIUP: 2071fcf5ef2aSThomas Huth case ASI_TWINX_AIUP_L: 2072fcf5ef2aSThomas Huth case ASI_TWINX_AIUS: 2073fcf5ef2aSThomas Huth case ASI_TWINX_AIUS_L: 2074fcf5ef2aSThomas Huth case ASI_TWINX_P: 2075fcf5ef2aSThomas Huth case ASI_TWINX_PL: 2076fcf5ef2aSThomas Huth case ASI_TWINX_S: 2077fcf5ef2aSThomas Huth case ASI_TWINX_SL: 2078fcf5ef2aSThomas Huth case ASI_QUAD_LDD_PHYS: 2079fcf5ef2aSThomas Huth case ASI_QUAD_LDD_PHYS_L: 2080fcf5ef2aSThomas Huth case ASI_NUCLEUS_QUAD_LDD: 2081fcf5ef2aSThomas Huth case ASI_NUCLEUS_QUAD_LDD_L: 2082fcf5ef2aSThomas Huth type = GET_ASI_DTWINX; 2083fcf5ef2aSThomas Huth break; 2084fcf5ef2aSThomas Huth case ASI_BLK_COMMIT_P: 2085fcf5ef2aSThomas Huth case ASI_BLK_COMMIT_S: 2086fcf5ef2aSThomas Huth case ASI_BLK_AIUP_4V: 2087fcf5ef2aSThomas Huth case ASI_BLK_AIUP_L_4V: 2088fcf5ef2aSThomas Huth case ASI_BLK_AIUP: 2089fcf5ef2aSThomas Huth case ASI_BLK_AIUPL: 2090fcf5ef2aSThomas Huth case ASI_BLK_AIUS_4V: 2091fcf5ef2aSThomas Huth case ASI_BLK_AIUS_L_4V: 2092fcf5ef2aSThomas Huth case ASI_BLK_AIUS: 2093fcf5ef2aSThomas Huth case ASI_BLK_AIUSL: 2094fcf5ef2aSThomas Huth case ASI_BLK_S: 2095fcf5ef2aSThomas Huth case ASI_BLK_SL: 2096fcf5ef2aSThomas Huth case ASI_BLK_P: 2097fcf5ef2aSThomas Huth case ASI_BLK_PL: 2098fcf5ef2aSThomas Huth type = GET_ASI_BLOCK; 2099fcf5ef2aSThomas Huth break; 2100fcf5ef2aSThomas Huth case ASI_FL8_S: 2101fcf5ef2aSThomas Huth case ASI_FL8_SL: 2102fcf5ef2aSThomas Huth case ASI_FL8_P: 2103fcf5ef2aSThomas Huth case ASI_FL8_PL: 2104fcf5ef2aSThomas Huth memop = MO_UB; 2105fcf5ef2aSThomas Huth type = GET_ASI_SHORT; 2106fcf5ef2aSThomas Huth break; 2107fcf5ef2aSThomas Huth case ASI_FL16_S: 2108fcf5ef2aSThomas Huth case ASI_FL16_SL: 2109fcf5ef2aSThomas Huth case ASI_FL16_P: 2110fcf5ef2aSThomas Huth case ASI_FL16_PL: 2111fcf5ef2aSThomas Huth memop = MO_TEUW; 2112fcf5ef2aSThomas Huth type = GET_ASI_SHORT; 2113fcf5ef2aSThomas Huth break; 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth /* The little-endian asis all have bit 3 set. */ 2116fcf5ef2aSThomas Huth if (asi & 8) { 2117fcf5ef2aSThomas Huth memop ^= MO_BSWAP; 2118fcf5ef2aSThomas Huth } 2119fcf5ef2aSThomas Huth } 2120fcf5ef2aSThomas Huth #endif 2121fcf5ef2aSThomas Huth 2122fcf5ef2aSThomas Huth return (DisasASI){ type, asi, mem_idx, memop }; 2123fcf5ef2aSThomas Huth } 2124fcf5ef2aSThomas Huth 2125fcf5ef2aSThomas Huth static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, 212614776ab5STony Nguyen int insn, MemOp memop) 2127fcf5ef2aSThomas Huth { 2128fcf5ef2aSThomas Huth DisasASI da = get_asi(dc, insn, memop); 2129fcf5ef2aSThomas Huth 2130fcf5ef2aSThomas Huth switch (da.type) { 2131fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2132fcf5ef2aSThomas Huth break; 2133fcf5ef2aSThomas Huth case GET_ASI_DTWINX: /* Reserved for ldda. */ 2134fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2135fcf5ef2aSThomas Huth break; 2136fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2137fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2138316b6783SRichard Henderson tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN); 2139fcf5ef2aSThomas Huth break; 2140fcf5ef2aSThomas Huth default: 2141fcf5ef2aSThomas Huth { 214200ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 2143316b6783SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN); 2144fcf5ef2aSThomas Huth 2145fcf5ef2aSThomas Huth save_state(dc); 2146fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 2147ad75a51eSRichard Henderson gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop); 2148fcf5ef2aSThomas Huth #else 2149fcf5ef2aSThomas Huth { 2150fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2151ad75a51eSRichard Henderson gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); 2152fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(dst, t64); 2153fcf5ef2aSThomas Huth } 2154fcf5ef2aSThomas Huth #endif 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth break; 2157fcf5ef2aSThomas Huth } 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth 2160fcf5ef2aSThomas Huth static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, 216114776ab5STony Nguyen int insn, MemOp memop) 2162fcf5ef2aSThomas Huth { 2163fcf5ef2aSThomas Huth DisasASI da = get_asi(dc, insn, memop); 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth switch (da.type) { 2166fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2167fcf5ef2aSThomas Huth break; 2168fcf5ef2aSThomas Huth case GET_ASI_DTWINX: /* Reserved for stda. */ 21693390537bSArtyom Tarasenko #ifndef TARGET_SPARC64 2170fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2171fcf5ef2aSThomas Huth break; 21723390537bSArtyom Tarasenko #else 21733390537bSArtyom Tarasenko if (!(dc->def->features & CPU_FEATURE_HYPV)) { 21743390537bSArtyom Tarasenko /* Pre OpenSPARC CPUs don't have these */ 21753390537bSArtyom Tarasenko gen_exception(dc, TT_ILL_INSN); 21763390537bSArtyom Tarasenko return; 21773390537bSArtyom Tarasenko } 21783390537bSArtyom Tarasenko /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions 21793390537bSArtyom Tarasenko * are ST_BLKINIT_ ASIs */ 21803390537bSArtyom Tarasenko #endif 2181fc0cd867SChen Qun /* fall through */ 2182fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2183fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2184316b6783SRichard Henderson tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN); 2185fcf5ef2aSThomas Huth break; 2186fcf5ef2aSThomas Huth #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 2187fcf5ef2aSThomas Huth case GET_ASI_BCOPY: 2188fcf5ef2aSThomas Huth /* Copy 32 bytes from the address in SRC to ADDR. */ 2189fcf5ef2aSThomas Huth /* ??? The original qemu code suggests 4-byte alignment, dropping 2190fcf5ef2aSThomas Huth the low bits, but the only place I can see this used is in the 2191fcf5ef2aSThomas Huth Linux kernel with 32 byte alignment, which would make more sense 2192fcf5ef2aSThomas Huth as a cacheline-style operation. */ 2193fcf5ef2aSThomas Huth { 2194fcf5ef2aSThomas Huth TCGv saddr = tcg_temp_new(); 2195fcf5ef2aSThomas Huth TCGv daddr = tcg_temp_new(); 219600ab7e61SRichard Henderson TCGv four = tcg_constant_tl(4); 2197fcf5ef2aSThomas Huth TCGv_i32 tmp = tcg_temp_new_i32(); 2198fcf5ef2aSThomas Huth int i; 2199fcf5ef2aSThomas Huth 2200fcf5ef2aSThomas Huth tcg_gen_andi_tl(saddr, src, -4); 2201fcf5ef2aSThomas Huth tcg_gen_andi_tl(daddr, addr, -4); 2202fcf5ef2aSThomas Huth for (i = 0; i < 32; i += 4) { 2203fcf5ef2aSThomas Huth /* Since the loads and stores are paired, allow the 2204fcf5ef2aSThomas Huth copy to happen in the host endianness. */ 2205fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL); 2206fcf5ef2aSThomas Huth tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL); 2207fcf5ef2aSThomas Huth tcg_gen_add_tl(saddr, saddr, four); 2208fcf5ef2aSThomas Huth tcg_gen_add_tl(daddr, daddr, four); 2209fcf5ef2aSThomas Huth } 2210fcf5ef2aSThomas Huth } 2211fcf5ef2aSThomas Huth break; 2212fcf5ef2aSThomas Huth #endif 2213fcf5ef2aSThomas Huth default: 2214fcf5ef2aSThomas Huth { 221500ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 2216316b6783SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN); 2217fcf5ef2aSThomas Huth 2218fcf5ef2aSThomas Huth save_state(dc); 2219fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 2220ad75a51eSRichard Henderson gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop); 2221fcf5ef2aSThomas Huth #else 2222fcf5ef2aSThomas Huth { 2223fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2224fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t64, src); 2225ad75a51eSRichard Henderson gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); 2226fcf5ef2aSThomas Huth } 2227fcf5ef2aSThomas Huth #endif 2228fcf5ef2aSThomas Huth 2229fcf5ef2aSThomas Huth /* A write to a TLB register may alter page maps. End the TB. */ 2230fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 2231fcf5ef2aSThomas Huth } 2232fcf5ef2aSThomas Huth break; 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth 2236fcf5ef2aSThomas Huth static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, 2237fcf5ef2aSThomas Huth TCGv addr, int insn) 2238fcf5ef2aSThomas Huth { 2239fcf5ef2aSThomas Huth DisasASI da = get_asi(dc, insn, MO_TEUL); 2240fcf5ef2aSThomas Huth 2241fcf5ef2aSThomas Huth switch (da.type) { 2242fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2243fcf5ef2aSThomas Huth break; 2244fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2245fcf5ef2aSThomas Huth gen_swap(dc, dst, src, addr, da.mem_idx, da.memop); 2246fcf5ef2aSThomas Huth break; 2247fcf5ef2aSThomas Huth default: 2248fcf5ef2aSThomas Huth /* ??? Should be DAE_invalid_asi. */ 2249fcf5ef2aSThomas Huth gen_exception(dc, TT_DATA_ACCESS); 2250fcf5ef2aSThomas Huth break; 2251fcf5ef2aSThomas Huth } 2252fcf5ef2aSThomas Huth } 2253fcf5ef2aSThomas Huth 2254fcf5ef2aSThomas Huth static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, 2255fcf5ef2aSThomas Huth int insn, int rd) 2256fcf5ef2aSThomas Huth { 2257fcf5ef2aSThomas Huth DisasASI da = get_asi(dc, insn, MO_TEUL); 2258fcf5ef2aSThomas Huth TCGv oldv; 2259fcf5ef2aSThomas Huth 2260fcf5ef2aSThomas Huth switch (da.type) { 2261fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2262fcf5ef2aSThomas Huth return; 2263fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2264fcf5ef2aSThomas Huth oldv = tcg_temp_new(); 2265fcf5ef2aSThomas Huth tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), 2266316b6783SRichard Henderson da.mem_idx, da.memop | MO_ALIGN); 2267fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, oldv); 2268fcf5ef2aSThomas Huth break; 2269fcf5ef2aSThomas Huth default: 2270fcf5ef2aSThomas Huth /* ??? Should be DAE_invalid_asi. */ 2271fcf5ef2aSThomas Huth gen_exception(dc, TT_DATA_ACCESS); 2272fcf5ef2aSThomas Huth break; 2273fcf5ef2aSThomas Huth } 2274fcf5ef2aSThomas Huth } 2275fcf5ef2aSThomas Huth 2276fcf5ef2aSThomas Huth static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) 2277fcf5ef2aSThomas Huth { 2278fcf5ef2aSThomas Huth DisasASI da = get_asi(dc, insn, MO_UB); 2279fcf5ef2aSThomas Huth 2280fcf5ef2aSThomas Huth switch (da.type) { 2281fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2282fcf5ef2aSThomas Huth break; 2283fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2284fcf5ef2aSThomas Huth gen_ldstub(dc, dst, addr, da.mem_idx); 2285fcf5ef2aSThomas Huth break; 2286fcf5ef2aSThomas Huth default: 22873db010c3SRichard Henderson /* ??? In theory, this should be raise DAE_invalid_asi. 22883db010c3SRichard Henderson But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ 2289af00be49SEmilio G. Cota if (tb_cflags(dc->base.tb) & CF_PARALLEL) { 2290ad75a51eSRichard Henderson gen_helper_exit_atomic(tcg_env); 22913db010c3SRichard Henderson } else { 229200ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 229300ab7e61SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(MO_UB); 22943db010c3SRichard Henderson TCGv_i64 s64, t64; 22953db010c3SRichard Henderson 22963db010c3SRichard Henderson save_state(dc); 22973db010c3SRichard Henderson t64 = tcg_temp_new_i64(); 2298ad75a51eSRichard Henderson gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); 22993db010c3SRichard Henderson 230000ab7e61SRichard Henderson s64 = tcg_constant_i64(0xff); 2301ad75a51eSRichard Henderson gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop); 23023db010c3SRichard Henderson 23033db010c3SRichard Henderson tcg_gen_trunc_i64_tl(dst, t64); 23043db010c3SRichard Henderson 23053db010c3SRichard Henderson /* End the TB. */ 23063db010c3SRichard Henderson dc->npc = DYNAMIC_PC; 23073db010c3SRichard Henderson } 2308fcf5ef2aSThomas Huth break; 2309fcf5ef2aSThomas Huth } 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth #endif 2312fcf5ef2aSThomas Huth 2313fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 2314fcf5ef2aSThomas Huth static void gen_ldf_asi(DisasContext *dc, TCGv addr, 2315fcf5ef2aSThomas Huth int insn, int size, int rd) 2316fcf5ef2aSThomas Huth { 2317fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); 2318fcf5ef2aSThomas Huth TCGv_i32 d32; 2319fcf5ef2aSThomas Huth TCGv_i64 d64; 2320fcf5ef2aSThomas Huth 2321fcf5ef2aSThomas Huth switch (da.type) { 2322fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2323fcf5ef2aSThomas Huth break; 2324fcf5ef2aSThomas Huth 2325fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2326fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2327fcf5ef2aSThomas Huth switch (size) { 2328fcf5ef2aSThomas Huth case 4: 2329fcf5ef2aSThomas Huth d32 = gen_dest_fpr_F(dc); 2330316b6783SRichard Henderson tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN); 2331fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, d32); 2332fcf5ef2aSThomas Huth break; 2333fcf5ef2aSThomas Huth case 8: 2334fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2335fcf5ef2aSThomas Huth da.memop | MO_ALIGN_4); 2336fcf5ef2aSThomas Huth break; 2337fcf5ef2aSThomas Huth case 16: 2338fcf5ef2aSThomas Huth d64 = tcg_temp_new_i64(); 2339fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4); 2340fcf5ef2aSThomas Huth tcg_gen_addi_tl(addr, addr, 8); 2341fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, 2342fcf5ef2aSThomas Huth da.memop | MO_ALIGN_4); 2343fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); 2344fcf5ef2aSThomas Huth break; 2345fcf5ef2aSThomas Huth default: 2346fcf5ef2aSThomas Huth g_assert_not_reached(); 2347fcf5ef2aSThomas Huth } 2348fcf5ef2aSThomas Huth break; 2349fcf5ef2aSThomas Huth 2350fcf5ef2aSThomas Huth case GET_ASI_BLOCK: 2351fcf5ef2aSThomas Huth /* Valid for lddfa on aligned registers only. */ 2352fcf5ef2aSThomas Huth if (size == 8 && (rd & 7) == 0) { 235314776ab5STony Nguyen MemOp memop; 2354fcf5ef2aSThomas Huth TCGv eight; 2355fcf5ef2aSThomas Huth int i; 2356fcf5ef2aSThomas Huth 2357fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2358fcf5ef2aSThomas Huth 2359fcf5ef2aSThomas Huth /* The first operation checks required alignment. */ 2360fcf5ef2aSThomas Huth memop = da.memop | MO_ALIGN_64; 236100ab7e61SRichard Henderson eight = tcg_constant_tl(8); 2362fcf5ef2aSThomas Huth for (i = 0; ; ++i) { 2363fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, 2364fcf5ef2aSThomas Huth da.mem_idx, memop); 2365fcf5ef2aSThomas Huth if (i == 7) { 2366fcf5ef2aSThomas Huth break; 2367fcf5ef2aSThomas Huth } 2368fcf5ef2aSThomas Huth tcg_gen_add_tl(addr, addr, eight); 2369fcf5ef2aSThomas Huth memop = da.memop; 2370fcf5ef2aSThomas Huth } 2371fcf5ef2aSThomas Huth } else { 2372fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2373fcf5ef2aSThomas Huth } 2374fcf5ef2aSThomas Huth break; 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth case GET_ASI_SHORT: 2377fcf5ef2aSThomas Huth /* Valid for lddfa only. */ 2378fcf5ef2aSThomas Huth if (size == 8) { 2379fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2380316b6783SRichard Henderson tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2381316b6783SRichard Henderson da.memop | MO_ALIGN); 2382fcf5ef2aSThomas Huth } else { 2383fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth break; 2386fcf5ef2aSThomas Huth 2387fcf5ef2aSThomas Huth default: 2388fcf5ef2aSThomas Huth { 238900ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 2390316b6783SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN); 2391fcf5ef2aSThomas Huth 2392fcf5ef2aSThomas Huth save_state(dc); 2393fcf5ef2aSThomas Huth /* According to the table in the UA2011 manual, the only 2394fcf5ef2aSThomas Huth other asis that are valid for ldfa/lddfa/ldqfa are 2395fcf5ef2aSThomas Huth the NO_FAULT asis. We still need a helper for these, 2396fcf5ef2aSThomas Huth but we can just use the integer asi helper for them. */ 2397fcf5ef2aSThomas Huth switch (size) { 2398fcf5ef2aSThomas Huth case 4: 2399fcf5ef2aSThomas Huth d64 = tcg_temp_new_i64(); 2400ad75a51eSRichard Henderson gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); 2401fcf5ef2aSThomas Huth d32 = gen_dest_fpr_F(dc); 2402fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(d32, d64); 2403fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, d32); 2404fcf5ef2aSThomas Huth break; 2405fcf5ef2aSThomas Huth case 8: 2406ad75a51eSRichard Henderson gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop); 2407fcf5ef2aSThomas Huth break; 2408fcf5ef2aSThomas Huth case 16: 2409fcf5ef2aSThomas Huth d64 = tcg_temp_new_i64(); 2410ad75a51eSRichard Henderson gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); 2411fcf5ef2aSThomas Huth tcg_gen_addi_tl(addr, addr, 8); 2412ad75a51eSRichard Henderson gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop); 2413fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); 2414fcf5ef2aSThomas Huth break; 2415fcf5ef2aSThomas Huth default: 2416fcf5ef2aSThomas Huth g_assert_not_reached(); 2417fcf5ef2aSThomas Huth } 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth break; 2420fcf5ef2aSThomas Huth } 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth 2423fcf5ef2aSThomas Huth static void gen_stf_asi(DisasContext *dc, TCGv addr, 2424fcf5ef2aSThomas Huth int insn, int size, int rd) 2425fcf5ef2aSThomas Huth { 2426fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); 2427fcf5ef2aSThomas Huth TCGv_i32 d32; 2428fcf5ef2aSThomas Huth 2429fcf5ef2aSThomas Huth switch (da.type) { 2430fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2431fcf5ef2aSThomas Huth break; 2432fcf5ef2aSThomas Huth 2433fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2434fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2435fcf5ef2aSThomas Huth switch (size) { 2436fcf5ef2aSThomas Huth case 4: 2437fcf5ef2aSThomas Huth d32 = gen_load_fpr_F(dc, rd); 2438316b6783SRichard Henderson tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN); 2439fcf5ef2aSThomas Huth break; 2440fcf5ef2aSThomas Huth case 8: 2441fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2442fcf5ef2aSThomas Huth da.memop | MO_ALIGN_4); 2443fcf5ef2aSThomas Huth break; 2444fcf5ef2aSThomas Huth case 16: 2445fcf5ef2aSThomas Huth /* Only 4-byte alignment required. However, it is legal for the 2446fcf5ef2aSThomas Huth cpu to signal the alignment fault, and the OS trap handler is 2447fcf5ef2aSThomas Huth required to fix it up. Requiring 16-byte alignment here avoids 2448fcf5ef2aSThomas Huth having to probe the second page before performing the first 2449fcf5ef2aSThomas Huth write. */ 2450fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2451fcf5ef2aSThomas Huth da.memop | MO_ALIGN_16); 2452fcf5ef2aSThomas Huth tcg_gen_addi_tl(addr, addr, 8); 2453fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop); 2454fcf5ef2aSThomas Huth break; 2455fcf5ef2aSThomas Huth default: 2456fcf5ef2aSThomas Huth g_assert_not_reached(); 2457fcf5ef2aSThomas Huth } 2458fcf5ef2aSThomas Huth break; 2459fcf5ef2aSThomas Huth 2460fcf5ef2aSThomas Huth case GET_ASI_BLOCK: 2461fcf5ef2aSThomas Huth /* Valid for stdfa on aligned registers only. */ 2462fcf5ef2aSThomas Huth if (size == 8 && (rd & 7) == 0) { 246314776ab5STony Nguyen MemOp memop; 2464fcf5ef2aSThomas Huth TCGv eight; 2465fcf5ef2aSThomas Huth int i; 2466fcf5ef2aSThomas Huth 2467fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2468fcf5ef2aSThomas Huth 2469fcf5ef2aSThomas Huth /* The first operation checks required alignment. */ 2470fcf5ef2aSThomas Huth memop = da.memop | MO_ALIGN_64; 247100ab7e61SRichard Henderson eight = tcg_constant_tl(8); 2472fcf5ef2aSThomas Huth for (i = 0; ; ++i) { 2473fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, 2474fcf5ef2aSThomas Huth da.mem_idx, memop); 2475fcf5ef2aSThomas Huth if (i == 7) { 2476fcf5ef2aSThomas Huth break; 2477fcf5ef2aSThomas Huth } 2478fcf5ef2aSThomas Huth tcg_gen_add_tl(addr, addr, eight); 2479fcf5ef2aSThomas Huth memop = da.memop; 2480fcf5ef2aSThomas Huth } 2481fcf5ef2aSThomas Huth } else { 2482fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2483fcf5ef2aSThomas Huth } 2484fcf5ef2aSThomas Huth break; 2485fcf5ef2aSThomas Huth 2486fcf5ef2aSThomas Huth case GET_ASI_SHORT: 2487fcf5ef2aSThomas Huth /* Valid for stdfa only. */ 2488fcf5ef2aSThomas Huth if (size == 8) { 2489fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2490316b6783SRichard Henderson tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2491316b6783SRichard Henderson da.memop | MO_ALIGN); 2492fcf5ef2aSThomas Huth } else { 2493fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth break; 2496fcf5ef2aSThomas Huth 2497fcf5ef2aSThomas Huth default: 2498fcf5ef2aSThomas Huth /* According to the table in the UA2011 manual, the only 2499fcf5ef2aSThomas Huth other asis that are valid for ldfa/lddfa/ldqfa are 2500fcf5ef2aSThomas Huth the PST* asis, which aren't currently handled. */ 2501fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 2502fcf5ef2aSThomas Huth break; 2503fcf5ef2aSThomas Huth } 2504fcf5ef2aSThomas Huth } 2505fcf5ef2aSThomas Huth 2506fcf5ef2aSThomas Huth static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) 2507fcf5ef2aSThomas Huth { 2508fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, MO_TEUQ); 2509fcf5ef2aSThomas Huth TCGv_i64 hi = gen_dest_gpr(dc, rd); 2510fcf5ef2aSThomas Huth TCGv_i64 lo = gen_dest_gpr(dc, rd + 1); 2511fcf5ef2aSThomas Huth 2512fcf5ef2aSThomas Huth switch (da.type) { 2513fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2514fcf5ef2aSThomas Huth return; 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth case GET_ASI_DTWINX: 2517fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2518fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); 2519fcf5ef2aSThomas Huth tcg_gen_addi_tl(addr, addr, 8); 2520fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); 2521fcf5ef2aSThomas Huth break; 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2524fcf5ef2aSThomas Huth { 2525fcf5ef2aSThomas Huth TCGv_i64 tmp = tcg_temp_new_i64(); 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2528316b6783SRichard Henderson tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN); 2529fcf5ef2aSThomas Huth 2530fcf5ef2aSThomas Huth /* Note that LE ldda acts as if each 32-bit register 2531fcf5ef2aSThomas Huth result is byte swapped. Having just performed one 2532fcf5ef2aSThomas Huth 64-bit bswap, we need now to swap the writebacks. */ 2533fcf5ef2aSThomas Huth if ((da.memop & MO_BSWAP) == MO_TE) { 2534fcf5ef2aSThomas Huth tcg_gen_extr32_i64(lo, hi, tmp); 2535fcf5ef2aSThomas Huth } else { 2536fcf5ef2aSThomas Huth tcg_gen_extr32_i64(hi, lo, tmp); 2537fcf5ef2aSThomas Huth } 2538fcf5ef2aSThomas Huth } 2539fcf5ef2aSThomas Huth break; 2540fcf5ef2aSThomas Huth 2541fcf5ef2aSThomas Huth default: 2542fcf5ef2aSThomas Huth /* ??? In theory we've handled all of the ASIs that are valid 2543fcf5ef2aSThomas Huth for ldda, and this should raise DAE_invalid_asi. However, 2544fcf5ef2aSThomas Huth real hardware allows others. This can be seen with e.g. 2545fcf5ef2aSThomas Huth FreeBSD 10.3 wrt ASI_IC_TAG. */ 2546fcf5ef2aSThomas Huth { 254700ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 254800ab7e61SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(da.memop); 2549fcf5ef2aSThomas Huth TCGv_i64 tmp = tcg_temp_new_i64(); 2550fcf5ef2aSThomas Huth 2551fcf5ef2aSThomas Huth save_state(dc); 2552ad75a51eSRichard Henderson gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); 2553fcf5ef2aSThomas Huth 2554fcf5ef2aSThomas Huth /* See above. */ 2555fcf5ef2aSThomas Huth if ((da.memop & MO_BSWAP) == MO_TE) { 2556fcf5ef2aSThomas Huth tcg_gen_extr32_i64(lo, hi, tmp); 2557fcf5ef2aSThomas Huth } else { 2558fcf5ef2aSThomas Huth tcg_gen_extr32_i64(hi, lo, tmp); 2559fcf5ef2aSThomas Huth } 2560fcf5ef2aSThomas Huth } 2561fcf5ef2aSThomas Huth break; 2562fcf5ef2aSThomas Huth } 2563fcf5ef2aSThomas Huth 2564fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, hi); 2565fcf5ef2aSThomas Huth gen_store_gpr(dc, rd + 1, lo); 2566fcf5ef2aSThomas Huth } 2567fcf5ef2aSThomas Huth 2568fcf5ef2aSThomas Huth static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, 2569fcf5ef2aSThomas Huth int insn, int rd) 2570fcf5ef2aSThomas Huth { 2571fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, MO_TEUQ); 2572fcf5ef2aSThomas Huth TCGv lo = gen_load_gpr(dc, rd + 1); 2573fcf5ef2aSThomas Huth 2574fcf5ef2aSThomas Huth switch (da.type) { 2575fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2576fcf5ef2aSThomas Huth break; 2577fcf5ef2aSThomas Huth 2578fcf5ef2aSThomas Huth case GET_ASI_DTWINX: 2579fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2580fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); 2581fcf5ef2aSThomas Huth tcg_gen_addi_tl(addr, addr, 8); 2582fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); 2583fcf5ef2aSThomas Huth break; 2584fcf5ef2aSThomas Huth 2585fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2586fcf5ef2aSThomas Huth { 2587fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2588fcf5ef2aSThomas Huth 2589fcf5ef2aSThomas Huth /* Note that LE stda acts as if each 32-bit register result is 2590fcf5ef2aSThomas Huth byte swapped. We will perform one 64-bit LE store, so now 2591fcf5ef2aSThomas Huth we must swap the order of the construction. */ 2592fcf5ef2aSThomas Huth if ((da.memop & MO_BSWAP) == MO_TE) { 2593fcf5ef2aSThomas Huth tcg_gen_concat32_i64(t64, lo, hi); 2594fcf5ef2aSThomas Huth } else { 2595fcf5ef2aSThomas Huth tcg_gen_concat32_i64(t64, hi, lo); 2596fcf5ef2aSThomas Huth } 2597fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2598316b6783SRichard Henderson tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); 2599fcf5ef2aSThomas Huth } 2600fcf5ef2aSThomas Huth break; 2601fcf5ef2aSThomas Huth 2602fcf5ef2aSThomas Huth default: 2603fcf5ef2aSThomas Huth /* ??? In theory we've handled all of the ASIs that are valid 2604fcf5ef2aSThomas Huth for stda, and this should raise DAE_invalid_asi. */ 2605fcf5ef2aSThomas Huth { 260600ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 260700ab7e61SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(da.memop); 2608fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth /* See above. */ 2611fcf5ef2aSThomas Huth if ((da.memop & MO_BSWAP) == MO_TE) { 2612fcf5ef2aSThomas Huth tcg_gen_concat32_i64(t64, lo, hi); 2613fcf5ef2aSThomas Huth } else { 2614fcf5ef2aSThomas Huth tcg_gen_concat32_i64(t64, hi, lo); 2615fcf5ef2aSThomas Huth } 2616fcf5ef2aSThomas Huth 2617fcf5ef2aSThomas Huth save_state(dc); 2618ad75a51eSRichard Henderson gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); 2619fcf5ef2aSThomas Huth } 2620fcf5ef2aSThomas Huth break; 2621fcf5ef2aSThomas Huth } 2622fcf5ef2aSThomas Huth } 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, 2625fcf5ef2aSThomas Huth int insn, int rd) 2626fcf5ef2aSThomas Huth { 2627fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, MO_TEUQ); 2628fcf5ef2aSThomas Huth TCGv oldv; 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth switch (da.type) { 2631fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2632fcf5ef2aSThomas Huth return; 2633fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2634fcf5ef2aSThomas Huth oldv = tcg_temp_new(); 2635fcf5ef2aSThomas Huth tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), 2636316b6783SRichard Henderson da.mem_idx, da.memop | MO_ALIGN); 2637fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, oldv); 2638fcf5ef2aSThomas Huth break; 2639fcf5ef2aSThomas Huth default: 2640fcf5ef2aSThomas Huth /* ??? Should be DAE_invalid_asi. */ 2641fcf5ef2aSThomas Huth gen_exception(dc, TT_DATA_ACCESS); 2642fcf5ef2aSThomas Huth break; 2643fcf5ef2aSThomas Huth } 2644fcf5ef2aSThomas Huth } 2645fcf5ef2aSThomas Huth 2646fcf5ef2aSThomas Huth #elif !defined(CONFIG_USER_ONLY) 2647fcf5ef2aSThomas Huth static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) 2648fcf5ef2aSThomas Huth { 2649fcf5ef2aSThomas Huth /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12, 2650fcf5ef2aSThomas Huth whereby "rd + 1" elicits "error: array subscript is above array". 2651fcf5ef2aSThomas Huth Since we have already asserted that rd is even, the semantics 2652fcf5ef2aSThomas Huth are unchanged. */ 2653fcf5ef2aSThomas Huth TCGv lo = gen_dest_gpr(dc, rd | 1); 2654fcf5ef2aSThomas Huth TCGv hi = gen_dest_gpr(dc, rd); 2655fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2656fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, MO_TEUQ); 2657fcf5ef2aSThomas Huth 2658fcf5ef2aSThomas Huth switch (da.type) { 2659fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2660fcf5ef2aSThomas Huth return; 2661fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2662fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2663316b6783SRichard Henderson tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); 2664fcf5ef2aSThomas Huth break; 2665fcf5ef2aSThomas Huth default: 2666fcf5ef2aSThomas Huth { 266700ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 266800ab7e61SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); 2669fcf5ef2aSThomas Huth 2670fcf5ef2aSThomas Huth save_state(dc); 2671ad75a51eSRichard Henderson gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); 2672fcf5ef2aSThomas Huth } 2673fcf5ef2aSThomas Huth break; 2674fcf5ef2aSThomas Huth } 2675fcf5ef2aSThomas Huth 2676fcf5ef2aSThomas Huth tcg_gen_extr_i64_i32(lo, hi, t64); 2677fcf5ef2aSThomas Huth gen_store_gpr(dc, rd | 1, lo); 2678fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, hi); 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth 2681fcf5ef2aSThomas Huth static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, 2682fcf5ef2aSThomas Huth int insn, int rd) 2683fcf5ef2aSThomas Huth { 2684fc313c64SFrédéric Pétrot DisasASI da = get_asi(dc, insn, MO_TEUQ); 2685fcf5ef2aSThomas Huth TCGv lo = gen_load_gpr(dc, rd + 1); 2686fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth tcg_gen_concat_tl_i64(t64, lo, hi); 2689fcf5ef2aSThomas Huth 2690fcf5ef2aSThomas Huth switch (da.type) { 2691fcf5ef2aSThomas Huth case GET_ASI_EXCP: 2692fcf5ef2aSThomas Huth break; 2693fcf5ef2aSThomas Huth case GET_ASI_DIRECT: 2694fcf5ef2aSThomas Huth gen_address_mask(dc, addr); 2695316b6783SRichard Henderson tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); 2696fcf5ef2aSThomas Huth break; 2697fcf5ef2aSThomas Huth case GET_ASI_BFILL: 2698fcf5ef2aSThomas Huth /* Store 32 bytes of T64 to ADDR. */ 2699fcf5ef2aSThomas Huth /* ??? The original qemu code suggests 8-byte alignment, dropping 2700fcf5ef2aSThomas Huth the low bits, but the only place I can see this used is in the 2701fcf5ef2aSThomas Huth Linux kernel with 32 byte alignment, which would make more sense 2702fcf5ef2aSThomas Huth as a cacheline-style operation. */ 2703fcf5ef2aSThomas Huth { 2704fcf5ef2aSThomas Huth TCGv d_addr = tcg_temp_new(); 270500ab7e61SRichard Henderson TCGv eight = tcg_constant_tl(8); 2706fcf5ef2aSThomas Huth int i; 2707fcf5ef2aSThomas Huth 2708fcf5ef2aSThomas Huth tcg_gen_andi_tl(d_addr, addr, -8); 2709fcf5ef2aSThomas Huth for (i = 0; i < 32; i += 8) { 2710fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); 2711fcf5ef2aSThomas Huth tcg_gen_add_tl(d_addr, d_addr, eight); 2712fcf5ef2aSThomas Huth } 2713fcf5ef2aSThomas Huth } 2714fcf5ef2aSThomas Huth break; 2715fcf5ef2aSThomas Huth default: 2716fcf5ef2aSThomas Huth { 271700ab7e61SRichard Henderson TCGv_i32 r_asi = tcg_constant_i32(da.asi); 271800ab7e61SRichard Henderson TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); 2719fcf5ef2aSThomas Huth 2720fcf5ef2aSThomas Huth save_state(dc); 2721ad75a51eSRichard Henderson gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); 2722fcf5ef2aSThomas Huth } 2723fcf5ef2aSThomas Huth break; 2724fcf5ef2aSThomas Huth } 2725fcf5ef2aSThomas Huth } 2726fcf5ef2aSThomas Huth #endif 2727fcf5ef2aSThomas Huth 2728fcf5ef2aSThomas Huth static TCGv get_src1(DisasContext *dc, unsigned int insn) 2729fcf5ef2aSThomas Huth { 2730fcf5ef2aSThomas Huth unsigned int rs1 = GET_FIELD(insn, 13, 17); 2731fcf5ef2aSThomas Huth return gen_load_gpr(dc, rs1); 2732fcf5ef2aSThomas Huth } 2733fcf5ef2aSThomas Huth 2734fcf5ef2aSThomas Huth static TCGv get_src2(DisasContext *dc, unsigned int insn) 2735fcf5ef2aSThomas Huth { 2736fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 2737fcf5ef2aSThomas Huth target_long simm = GET_FIELDs(insn, 19, 31); 273852123f14SRichard Henderson TCGv t = tcg_temp_new(); 2739fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, simm); 2740fcf5ef2aSThomas Huth return t; 2741fcf5ef2aSThomas Huth } else { /* register */ 2742fcf5ef2aSThomas Huth unsigned int rs2 = GET_FIELD(insn, 27, 31); 2743fcf5ef2aSThomas Huth return gen_load_gpr(dc, rs2); 2744fcf5ef2aSThomas Huth } 2745fcf5ef2aSThomas Huth } 2746fcf5ef2aSThomas Huth 2747fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 2748fcf5ef2aSThomas Huth static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2749fcf5ef2aSThomas Huth { 2750fcf5ef2aSThomas Huth TCGv_i32 c32, zero, dst, s1, s2; 2751fcf5ef2aSThomas Huth 2752fcf5ef2aSThomas Huth /* We have two choices here: extend the 32 bit data and use movcond_i64, 2753fcf5ef2aSThomas Huth or fold the comparison down to 32 bits and use movcond_i32. Choose 2754fcf5ef2aSThomas Huth the later. */ 2755fcf5ef2aSThomas Huth c32 = tcg_temp_new_i32(); 2756fcf5ef2aSThomas Huth if (cmp->is_bool) { 2757fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(c32, cmp->c1); 2758fcf5ef2aSThomas Huth } else { 2759fcf5ef2aSThomas Huth TCGv_i64 c64 = tcg_temp_new_i64(); 2760fcf5ef2aSThomas Huth tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); 2761fcf5ef2aSThomas Huth tcg_gen_extrl_i64_i32(c32, c64); 2762fcf5ef2aSThomas Huth } 2763fcf5ef2aSThomas Huth 2764fcf5ef2aSThomas Huth s1 = gen_load_fpr_F(dc, rs); 2765fcf5ef2aSThomas Huth s2 = gen_load_fpr_F(dc, rd); 2766fcf5ef2aSThomas Huth dst = gen_dest_fpr_F(dc); 276700ab7e61SRichard Henderson zero = tcg_constant_i32(0); 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); 2770fcf5ef2aSThomas Huth 2771fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, dst); 2772fcf5ef2aSThomas Huth } 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2775fcf5ef2aSThomas Huth { 2776fcf5ef2aSThomas Huth TCGv_i64 dst = gen_dest_fpr_D(dc, rd); 2777fcf5ef2aSThomas Huth tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, 2778fcf5ef2aSThomas Huth gen_load_fpr_D(dc, rs), 2779fcf5ef2aSThomas Huth gen_load_fpr_D(dc, rd)); 2780fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, dst); 2781fcf5ef2aSThomas Huth } 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2784fcf5ef2aSThomas Huth { 2785fcf5ef2aSThomas Huth int qd = QFPREG(rd); 2786fcf5ef2aSThomas Huth int qs = QFPREG(rs); 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2, 2789fcf5ef2aSThomas Huth cpu_fpr[qs / 2], cpu_fpr[qd / 2]); 2790fcf5ef2aSThomas Huth tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2, 2791fcf5ef2aSThomas Huth cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); 2792fcf5ef2aSThomas Huth 2793fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, qd); 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 2797ad75a51eSRichard Henderson static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env) 2798fcf5ef2aSThomas Huth { 2799fcf5ef2aSThomas Huth TCGv_i32 r_tl = tcg_temp_new_i32(); 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth /* load env->tl into r_tl */ 2802ad75a51eSRichard Henderson tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl)); 2803fcf5ef2aSThomas Huth 2804fcf5ef2aSThomas Huth /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */ 2805fcf5ef2aSThomas Huth tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); 2806fcf5ef2aSThomas Huth 2807fcf5ef2aSThomas Huth /* calculate offset to current trap state from env->ts, reuse r_tl */ 2808fcf5ef2aSThomas Huth tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state)); 2809ad75a51eSRichard Henderson tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts)); 2810fcf5ef2aSThomas Huth 2811fcf5ef2aSThomas Huth /* tsptr = env->ts[env->tl & MAXTL_MASK] */ 2812fcf5ef2aSThomas Huth { 2813fcf5ef2aSThomas Huth TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); 2814fcf5ef2aSThomas Huth tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); 2815fcf5ef2aSThomas Huth tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); 2816fcf5ef2aSThomas Huth } 2817fcf5ef2aSThomas Huth } 2818fcf5ef2aSThomas Huth #endif 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, 2821fcf5ef2aSThomas Huth int width, bool cc, bool left) 2822fcf5ef2aSThomas Huth { 2823905a83deSRichard Henderson TCGv lo1, lo2; 2824fcf5ef2aSThomas Huth uint64_t amask, tabl, tabr; 2825fcf5ef2aSThomas Huth int shift, imask, omask; 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth if (cc) { 2828fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src, s1); 2829fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_src2, s2); 2830fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_cc_dst, s1, s2); 2831fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); 2832fcf5ef2aSThomas Huth dc->cc_op = CC_OP_SUB; 2833fcf5ef2aSThomas Huth } 2834fcf5ef2aSThomas Huth 2835fcf5ef2aSThomas Huth /* Theory of operation: there are two tables, left and right (not to 2836fcf5ef2aSThomas Huth be confused with the left and right versions of the opcode). These 2837fcf5ef2aSThomas Huth are indexed by the low 3 bits of the inputs. To make things "easy", 2838fcf5ef2aSThomas Huth these tables are loaded into two constants, TABL and TABR below. 2839fcf5ef2aSThomas Huth The operation index = (input & imask) << shift calculates the index 2840fcf5ef2aSThomas Huth into the constant, while val = (table >> index) & omask calculates 2841fcf5ef2aSThomas Huth the value we're looking for. */ 2842fcf5ef2aSThomas Huth switch (width) { 2843fcf5ef2aSThomas Huth case 8: 2844fcf5ef2aSThomas Huth imask = 0x7; 2845fcf5ef2aSThomas Huth shift = 3; 2846fcf5ef2aSThomas Huth omask = 0xff; 2847fcf5ef2aSThomas Huth if (left) { 2848fcf5ef2aSThomas Huth tabl = 0x80c0e0f0f8fcfeffULL; 2849fcf5ef2aSThomas Huth tabr = 0xff7f3f1f0f070301ULL; 2850fcf5ef2aSThomas Huth } else { 2851fcf5ef2aSThomas Huth tabl = 0x0103070f1f3f7fffULL; 2852fcf5ef2aSThomas Huth tabr = 0xfffefcf8f0e0c080ULL; 2853fcf5ef2aSThomas Huth } 2854fcf5ef2aSThomas Huth break; 2855fcf5ef2aSThomas Huth case 16: 2856fcf5ef2aSThomas Huth imask = 0x6; 2857fcf5ef2aSThomas Huth shift = 1; 2858fcf5ef2aSThomas Huth omask = 0xf; 2859fcf5ef2aSThomas Huth if (left) { 2860fcf5ef2aSThomas Huth tabl = 0x8cef; 2861fcf5ef2aSThomas Huth tabr = 0xf731; 2862fcf5ef2aSThomas Huth } else { 2863fcf5ef2aSThomas Huth tabl = 0x137f; 2864fcf5ef2aSThomas Huth tabr = 0xfec8; 2865fcf5ef2aSThomas Huth } 2866fcf5ef2aSThomas Huth break; 2867fcf5ef2aSThomas Huth case 32: 2868fcf5ef2aSThomas Huth imask = 0x4; 2869fcf5ef2aSThomas Huth shift = 0; 2870fcf5ef2aSThomas Huth omask = 0x3; 2871fcf5ef2aSThomas Huth if (left) { 2872fcf5ef2aSThomas Huth tabl = (2 << 2) | 3; 2873fcf5ef2aSThomas Huth tabr = (3 << 2) | 1; 2874fcf5ef2aSThomas Huth } else { 2875fcf5ef2aSThomas Huth tabl = (1 << 2) | 3; 2876fcf5ef2aSThomas Huth tabr = (3 << 2) | 2; 2877fcf5ef2aSThomas Huth } 2878fcf5ef2aSThomas Huth break; 2879fcf5ef2aSThomas Huth default: 2880fcf5ef2aSThomas Huth abort(); 2881fcf5ef2aSThomas Huth } 2882fcf5ef2aSThomas Huth 2883fcf5ef2aSThomas Huth lo1 = tcg_temp_new(); 2884fcf5ef2aSThomas Huth lo2 = tcg_temp_new(); 2885fcf5ef2aSThomas Huth tcg_gen_andi_tl(lo1, s1, imask); 2886fcf5ef2aSThomas Huth tcg_gen_andi_tl(lo2, s2, imask); 2887fcf5ef2aSThomas Huth tcg_gen_shli_tl(lo1, lo1, shift); 2888fcf5ef2aSThomas Huth tcg_gen_shli_tl(lo2, lo2, shift); 2889fcf5ef2aSThomas Huth 2890905a83deSRichard Henderson tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); 2891905a83deSRichard Henderson tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); 2892e3ebbadeSRichard Henderson tcg_gen_andi_tl(lo1, lo1, omask); 2893fcf5ef2aSThomas Huth tcg_gen_andi_tl(lo2, lo2, omask); 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth amask = -8; 2896fcf5ef2aSThomas Huth if (AM_CHECK(dc)) { 2897fcf5ef2aSThomas Huth amask &= 0xffffffffULL; 2898fcf5ef2aSThomas Huth } 2899fcf5ef2aSThomas Huth tcg_gen_andi_tl(s1, s1, amask); 2900fcf5ef2aSThomas Huth tcg_gen_andi_tl(s2, s2, amask); 2901fcf5ef2aSThomas Huth 2902e3ebbadeSRichard Henderson /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */ 2903e3ebbadeSRichard Henderson tcg_gen_and_tl(lo2, lo2, lo1); 2904e3ebbadeSRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); 2905fcf5ef2aSThomas Huth } 2906fcf5ef2aSThomas Huth 2907fcf5ef2aSThomas Huth static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) 2908fcf5ef2aSThomas Huth { 2909fcf5ef2aSThomas Huth TCGv tmp = tcg_temp_new(); 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth tcg_gen_add_tl(tmp, s1, s2); 2912fcf5ef2aSThomas Huth tcg_gen_andi_tl(dst, tmp, -8); 2913fcf5ef2aSThomas Huth if (left) { 2914fcf5ef2aSThomas Huth tcg_gen_neg_tl(tmp, tmp); 2915fcf5ef2aSThomas Huth } 2916fcf5ef2aSThomas Huth tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); 2917fcf5ef2aSThomas Huth } 2918fcf5ef2aSThomas Huth 2919fcf5ef2aSThomas Huth static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) 2920fcf5ef2aSThomas Huth { 2921fcf5ef2aSThomas Huth TCGv t1, t2, shift; 2922fcf5ef2aSThomas Huth 2923fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2924fcf5ef2aSThomas Huth t2 = tcg_temp_new(); 2925fcf5ef2aSThomas Huth shift = tcg_temp_new(); 2926fcf5ef2aSThomas Huth 2927fcf5ef2aSThomas Huth tcg_gen_andi_tl(shift, gsr, 7); 2928fcf5ef2aSThomas Huth tcg_gen_shli_tl(shift, shift, 3); 2929fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, s1, shift); 2930fcf5ef2aSThomas Huth 2931fcf5ef2aSThomas Huth /* A shift of 64 does not produce 0 in TCG. Divide this into a 2932fcf5ef2aSThomas Huth shift of (up to 63) followed by a constant shift of 1. */ 2933fcf5ef2aSThomas Huth tcg_gen_xori_tl(shift, shift, 63); 2934fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, s2, shift); 2935fcf5ef2aSThomas Huth tcg_gen_shri_tl(t2, t2, 1); 2936fcf5ef2aSThomas Huth 2937fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, t1, t2); 2938fcf5ef2aSThomas Huth } 2939fcf5ef2aSThomas Huth #endif 2940fcf5ef2aSThomas Huth 2941878cc677SRichard Henderson /* Include the auto-generated decoder. */ 2942878cc677SRichard Henderson #include "decode-insns.c.inc" 2943878cc677SRichard Henderson 2944878cc677SRichard Henderson #define TRANS(NAME, AVAIL, FUNC, ...) \ 2945878cc677SRichard Henderson static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \ 2946878cc677SRichard Henderson { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); } 2947878cc677SRichard Henderson 2948878cc677SRichard Henderson #define avail_ALL(C) true 2949878cc677SRichard Henderson #ifdef TARGET_SPARC64 2950878cc677SRichard Henderson # define avail_32(C) false 2951878cc677SRichard Henderson # define avail_64(C) true 2952878cc677SRichard Henderson #else 2953878cc677SRichard Henderson # define avail_32(C) true 2954878cc677SRichard Henderson # define avail_64(C) false 2955878cc677SRichard Henderson #endif 2956878cc677SRichard Henderson 2957878cc677SRichard Henderson /* Default case for non jump instructions. */ 2958878cc677SRichard Henderson static bool advance_pc(DisasContext *dc) 2959878cc677SRichard Henderson { 2960878cc677SRichard Henderson if (dc->npc & 3) { 2961878cc677SRichard Henderson switch (dc->npc) { 2962878cc677SRichard Henderson case DYNAMIC_PC: 2963878cc677SRichard Henderson case DYNAMIC_PC_LOOKUP: 2964878cc677SRichard Henderson dc->pc = dc->npc; 2965878cc677SRichard Henderson gen_op_next_insn(); 2966878cc677SRichard Henderson break; 2967878cc677SRichard Henderson case JUMP_PC: 2968878cc677SRichard Henderson /* we can do a static jump */ 2969878cc677SRichard Henderson gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); 2970878cc677SRichard Henderson dc->base.is_jmp = DISAS_NORETURN; 2971878cc677SRichard Henderson break; 2972878cc677SRichard Henderson default: 2973878cc677SRichard Henderson g_assert_not_reached(); 2974878cc677SRichard Henderson } 2975878cc677SRichard Henderson } else { 2976878cc677SRichard Henderson dc->pc = dc->npc; 2977878cc677SRichard Henderson dc->npc = dc->npc + 4; 2978878cc677SRichard Henderson } 2979878cc677SRichard Henderson return true; 2980878cc677SRichard Henderson } 2981878cc677SRichard Henderson 2982276567aaSRichard Henderson static bool advance_jump_uncond_never(DisasContext *dc, bool annul) 2983276567aaSRichard Henderson { 2984276567aaSRichard Henderson if (annul) { 2985276567aaSRichard Henderson dc->pc = dc->npc + 4; 2986276567aaSRichard Henderson dc->npc = dc->pc + 4; 2987276567aaSRichard Henderson } else { 2988276567aaSRichard Henderson dc->pc = dc->npc; 2989276567aaSRichard Henderson dc->npc = dc->pc + 4; 2990276567aaSRichard Henderson } 2991276567aaSRichard Henderson return true; 2992276567aaSRichard Henderson } 2993276567aaSRichard Henderson 2994276567aaSRichard Henderson static bool advance_jump_uncond_always(DisasContext *dc, bool annul, 2995276567aaSRichard Henderson target_ulong dest) 2996276567aaSRichard Henderson { 2997276567aaSRichard Henderson if (annul) { 2998276567aaSRichard Henderson dc->pc = dest; 2999276567aaSRichard Henderson dc->npc = dest + 4; 3000276567aaSRichard Henderson } else { 3001276567aaSRichard Henderson dc->pc = dc->npc; 3002276567aaSRichard Henderson dc->npc = dest; 3003276567aaSRichard Henderson tcg_gen_mov_tl(cpu_pc, cpu_npc); 3004276567aaSRichard Henderson } 3005276567aaSRichard Henderson return true; 3006276567aaSRichard Henderson } 3007276567aaSRichard Henderson 3008276567aaSRichard Henderson static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) 3009276567aaSRichard Henderson { 3010276567aaSRichard Henderson if (annul) { 3011276567aaSRichard Henderson gen_branch_a(dc, dest); 3012276567aaSRichard Henderson } else { 3013276567aaSRichard Henderson gen_branch_n(dc, dest); 3014276567aaSRichard Henderson } 3015276567aaSRichard Henderson return true; 3016276567aaSRichard Henderson } 3017276567aaSRichard Henderson 3018276567aaSRichard Henderson static bool do_bpcc(DisasContext *dc, arg_bcc *a) 3019276567aaSRichard Henderson { 3020276567aaSRichard Henderson target_long target = address_mask_i(dc, dc->pc + a->i * 4); 3021276567aaSRichard Henderson 3022276567aaSRichard Henderson switch (a->cond) { 3023276567aaSRichard Henderson case 0x0: 3024276567aaSRichard Henderson return advance_jump_uncond_never(dc, a->a); 3025276567aaSRichard Henderson case 0x8: 3026276567aaSRichard Henderson return advance_jump_uncond_always(dc, a->a, target); 3027276567aaSRichard Henderson default: 3028276567aaSRichard Henderson flush_cond(dc); 3029276567aaSRichard Henderson gen_cond(cpu_cond, a->cc, a->cond, dc); 3030276567aaSRichard Henderson return advance_jump_cond(dc, a->a, target); 3031276567aaSRichard Henderson } 3032276567aaSRichard Henderson } 3033276567aaSRichard Henderson 3034276567aaSRichard Henderson TRANS(Bicc, ALL, do_bpcc, a) 3035276567aaSRichard Henderson TRANS(BPcc, 64, do_bpcc, a) 3036276567aaSRichard Henderson 3037*ab9ffe98SRichard Henderson static bool trans_BPr(DisasContext *dc, arg_BPr *a) 3038*ab9ffe98SRichard Henderson { 3039*ab9ffe98SRichard Henderson target_long target = address_mask_i(dc, dc->pc + a->i * 4); 3040*ab9ffe98SRichard Henderson DisasCompare cmp; 3041*ab9ffe98SRichard Henderson 3042*ab9ffe98SRichard Henderson if (!avail_64(dc)) { 3043*ab9ffe98SRichard Henderson return false; 3044*ab9ffe98SRichard Henderson } 3045*ab9ffe98SRichard Henderson if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) { 3046*ab9ffe98SRichard Henderson return false; 3047*ab9ffe98SRichard Henderson } 3048*ab9ffe98SRichard Henderson 3049*ab9ffe98SRichard Henderson flush_cond(dc); 3050*ab9ffe98SRichard Henderson gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); 3051*ab9ffe98SRichard Henderson tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); 3052*ab9ffe98SRichard Henderson return advance_jump_cond(dc, a->a, target); 3053*ab9ffe98SRichard Henderson } 3054*ab9ffe98SRichard Henderson 305523ada1b1SRichard Henderson static bool trans_CALL(DisasContext *dc, arg_CALL *a) 305623ada1b1SRichard Henderson { 305723ada1b1SRichard Henderson target_long target = address_mask_i(dc, dc->pc + a->i * 4); 305823ada1b1SRichard Henderson 305923ada1b1SRichard Henderson gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc)); 306023ada1b1SRichard Henderson gen_mov_pc_npc(dc); 306123ada1b1SRichard Henderson dc->npc = target; 306223ada1b1SRichard Henderson return true; 306323ada1b1SRichard Henderson } 306423ada1b1SRichard Henderson 3065fcf5ef2aSThomas Huth #define CHECK_IU_FEATURE(dc, FEATURE) \ 3066fcf5ef2aSThomas Huth if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ 3067fcf5ef2aSThomas Huth goto illegal_insn; 3068fcf5ef2aSThomas Huth #define CHECK_FPU_FEATURE(dc, FEATURE) \ 3069fcf5ef2aSThomas Huth if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ 3070fcf5ef2aSThomas Huth goto nfpu_insn; 3071fcf5ef2aSThomas Huth 3072fcf5ef2aSThomas Huth /* before an instruction, dc->pc must be static */ 3073878cc677SRichard Henderson static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) 3074fcf5ef2aSThomas Huth { 3075fcf5ef2aSThomas Huth unsigned int opc, rs1, rs2, rd; 3076fcf5ef2aSThomas Huth TCGv cpu_src1, cpu_src2; 3077fcf5ef2aSThomas Huth TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; 3078fcf5ef2aSThomas Huth TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; 3079fcf5ef2aSThomas Huth target_long simm; 3080fcf5ef2aSThomas Huth 3081fcf5ef2aSThomas Huth opc = GET_FIELD(insn, 0, 1); 3082fcf5ef2aSThomas Huth rd = GET_FIELD(insn, 2, 6); 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth switch (opc) { 3085fcf5ef2aSThomas Huth case 0: /* branches/sethi */ 3086fcf5ef2aSThomas Huth { 3087fcf5ef2aSThomas Huth unsigned int xop = GET_FIELD(insn, 7, 9); 3088fcf5ef2aSThomas Huth int32_t target; 3089fcf5ef2aSThomas Huth switch (xop) { 3090fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3091fcf5ef2aSThomas Huth case 0x1: /* V9 BPcc */ 3092276567aaSRichard Henderson g_assert_not_reached(); /* in decodetree */ 3093fcf5ef2aSThomas Huth case 0x3: /* V9 BPr */ 3094*ab9ffe98SRichard Henderson g_assert_not_reached(); /* in decodetree */ 3095fcf5ef2aSThomas Huth case 0x5: /* V9 FBPcc */ 3096fcf5ef2aSThomas Huth { 3097fcf5ef2aSThomas Huth int cc = GET_FIELD_SP(insn, 20, 21); 3098fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 3099fcf5ef2aSThomas Huth goto jmp_insn; 3100fcf5ef2aSThomas Huth } 3101fcf5ef2aSThomas Huth target = GET_FIELD_SP(insn, 0, 18); 3102fcf5ef2aSThomas Huth target = sign_extend(target, 19); 3103fcf5ef2aSThomas Huth target <<= 2; 3104fcf5ef2aSThomas Huth do_fbranch(dc, target, insn, cc); 3105fcf5ef2aSThomas Huth goto jmp_insn; 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth #else 3108fcf5ef2aSThomas Huth case 0x7: /* CBN+x */ 3109fcf5ef2aSThomas Huth { 3110fcf5ef2aSThomas Huth goto ncp_insn; 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth #endif 3113fcf5ef2aSThomas Huth case 0x2: /* BN+x */ 3114276567aaSRichard Henderson g_assert_not_reached(); /* in decodetree */ 3115fcf5ef2aSThomas Huth case 0x6: /* FBN+x */ 3116fcf5ef2aSThomas Huth { 3117fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 3118fcf5ef2aSThomas Huth goto jmp_insn; 3119fcf5ef2aSThomas Huth } 3120fcf5ef2aSThomas Huth target = GET_FIELD(insn, 10, 31); 3121fcf5ef2aSThomas Huth target = sign_extend(target, 22); 3122fcf5ef2aSThomas Huth target <<= 2; 3123fcf5ef2aSThomas Huth do_fbranch(dc, target, insn, 0); 3124fcf5ef2aSThomas Huth goto jmp_insn; 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth case 0x4: /* SETHI */ 3127fcf5ef2aSThomas Huth /* Special-case %g0 because that's the canonical nop. */ 3128fcf5ef2aSThomas Huth if (rd) { 3129fcf5ef2aSThomas Huth uint32_t value = GET_FIELD(insn, 10, 31); 3130fcf5ef2aSThomas Huth TCGv t = gen_dest_gpr(dc, rd); 3131fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, value << 10); 3132fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, t); 3133fcf5ef2aSThomas Huth } 3134fcf5ef2aSThomas Huth break; 3135fcf5ef2aSThomas Huth case 0x0: /* UNIMPL */ 3136fcf5ef2aSThomas Huth default: 3137fcf5ef2aSThomas Huth goto illegal_insn; 3138fcf5ef2aSThomas Huth } 3139fcf5ef2aSThomas Huth break; 3140fcf5ef2aSThomas Huth } 3141fcf5ef2aSThomas Huth break; 314223ada1b1SRichard Henderson case 1: 314323ada1b1SRichard Henderson g_assert_not_reached(); /* in decodetree */ 3144fcf5ef2aSThomas Huth case 2: /* FPU & Logical Operations */ 3145fcf5ef2aSThomas Huth { 3146fcf5ef2aSThomas Huth unsigned int xop = GET_FIELD(insn, 7, 12); 314752123f14SRichard Henderson TCGv cpu_dst = tcg_temp_new(); 3148fcf5ef2aSThomas Huth TCGv cpu_tmp0; 3149fcf5ef2aSThomas Huth 3150fcf5ef2aSThomas Huth if (xop == 0x3a) { /* generate trap */ 3151fcf5ef2aSThomas Huth int cond = GET_FIELD(insn, 3, 6); 3152fcf5ef2aSThomas Huth TCGv_i32 trap; 3153fcf5ef2aSThomas Huth TCGLabel *l1 = NULL; 3154fcf5ef2aSThomas Huth int mask; 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth if (cond == 0) { 3157fcf5ef2aSThomas Huth /* Trap never. */ 3158fcf5ef2aSThomas Huth break; 3159fcf5ef2aSThomas Huth } 3160fcf5ef2aSThomas Huth 3161fcf5ef2aSThomas Huth save_state(dc); 3162fcf5ef2aSThomas Huth 3163fcf5ef2aSThomas Huth if (cond != 8) { 3164fcf5ef2aSThomas Huth /* Conditional trap. */ 3165fcf5ef2aSThomas Huth DisasCompare cmp; 3166fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3167fcf5ef2aSThomas Huth /* V9 icc/xcc */ 3168fcf5ef2aSThomas Huth int cc = GET_FIELD_SP(insn, 11, 12); 3169fcf5ef2aSThomas Huth if (cc == 0) { 3170fcf5ef2aSThomas Huth gen_compare(&cmp, 0, cond, dc); 3171fcf5ef2aSThomas Huth } else if (cc == 2) { 3172fcf5ef2aSThomas Huth gen_compare(&cmp, 1, cond, dc); 3173fcf5ef2aSThomas Huth } else { 3174fcf5ef2aSThomas Huth goto illegal_insn; 3175fcf5ef2aSThomas Huth } 3176fcf5ef2aSThomas Huth #else 3177fcf5ef2aSThomas Huth gen_compare(&cmp, 0, cond, dc); 3178fcf5ef2aSThomas Huth #endif 3179fcf5ef2aSThomas Huth l1 = gen_new_label(); 3180fcf5ef2aSThomas Huth tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), 3181fcf5ef2aSThomas Huth cmp.c1, cmp.c2, l1); 3182fcf5ef2aSThomas Huth } 3183fcf5ef2aSThomas Huth 3184fcf5ef2aSThomas Huth mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) 3185fcf5ef2aSThomas Huth ? UA2005_HTRAP_MASK : V8_TRAP_MASK); 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth /* Don't use the normal temporaries, as they may well have 3188fcf5ef2aSThomas Huth gone out of scope with the branch above. While we're 3189fcf5ef2aSThomas Huth doing that we might as well pre-truncate to 32-bit. */ 3190fcf5ef2aSThomas Huth trap = tcg_temp_new_i32(); 3191fcf5ef2aSThomas Huth 3192fcf5ef2aSThomas Huth rs1 = GET_FIELD_SP(insn, 14, 18); 3193fcf5ef2aSThomas Huth if (IS_IMM) { 31945c65df36SArtyom Tarasenko rs2 = GET_FIELD_SP(insn, 0, 7); 3195fcf5ef2aSThomas Huth if (rs1 == 0) { 3196fcf5ef2aSThomas Huth tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP); 3197fcf5ef2aSThomas Huth /* Signal that the trap value is fully constant. */ 3198fcf5ef2aSThomas Huth mask = 0; 3199fcf5ef2aSThomas Huth } else { 3200fcf5ef2aSThomas Huth TCGv t1 = gen_load_gpr(dc, rs1); 3201fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(trap, t1); 3202fcf5ef2aSThomas Huth tcg_gen_addi_i32(trap, trap, rs2); 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth } else { 3205fcf5ef2aSThomas Huth TCGv t1, t2; 3206fcf5ef2aSThomas Huth rs2 = GET_FIELD_SP(insn, 0, 4); 3207fcf5ef2aSThomas Huth t1 = gen_load_gpr(dc, rs1); 3208fcf5ef2aSThomas Huth t2 = gen_load_gpr(dc, rs2); 3209fcf5ef2aSThomas Huth tcg_gen_add_tl(t1, t1, t2); 3210fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(trap, t1); 3211fcf5ef2aSThomas Huth } 3212fcf5ef2aSThomas Huth if (mask != 0) { 3213fcf5ef2aSThomas Huth tcg_gen_andi_i32(trap, trap, mask); 3214fcf5ef2aSThomas Huth tcg_gen_addi_i32(trap, trap, TT_TRAP); 3215fcf5ef2aSThomas Huth } 3216fcf5ef2aSThomas Huth 3217ad75a51eSRichard Henderson gen_helper_raise_exception(tcg_env, trap); 3218fcf5ef2aSThomas Huth 3219fcf5ef2aSThomas Huth if (cond == 8) { 3220fcf5ef2aSThomas Huth /* An unconditional trap ends the TB. */ 3221af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 3222fcf5ef2aSThomas Huth goto jmp_insn; 3223fcf5ef2aSThomas Huth } else { 3224fcf5ef2aSThomas Huth /* A conditional trap falls through to the next insn. */ 3225fcf5ef2aSThomas Huth gen_set_label(l1); 3226fcf5ef2aSThomas Huth break; 3227fcf5ef2aSThomas Huth } 3228fcf5ef2aSThomas Huth } else if (xop == 0x28) { 3229fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3230fcf5ef2aSThomas Huth switch(rs1) { 3231fcf5ef2aSThomas Huth case 0: /* rdy */ 3232fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 3233fcf5ef2aSThomas Huth case 0x01 ... 0x0e: /* undefined in the SPARCv8 3234fcf5ef2aSThomas Huth manual, rdy on the microSPARC 3235fcf5ef2aSThomas Huth II */ 3236fcf5ef2aSThomas Huth case 0x0f: /* stbar in the SPARCv8 manual, 3237fcf5ef2aSThomas Huth rdy on the microSPARC II */ 3238fcf5ef2aSThomas Huth case 0x10 ... 0x1f: /* implementation-dependent in the 3239fcf5ef2aSThomas Huth SPARCv8 manual, rdy on the 3240fcf5ef2aSThomas Huth microSPARC II */ 3241fcf5ef2aSThomas Huth /* Read Asr17 */ 3242fcf5ef2aSThomas Huth if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { 3243fcf5ef2aSThomas Huth TCGv t = gen_dest_gpr(dc, rd); 3244fcf5ef2aSThomas Huth /* Read Asr17 for a Leon3 monoprocessor */ 3245fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1)); 3246fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, t); 3247fcf5ef2aSThomas Huth break; 3248fcf5ef2aSThomas Huth } 3249fcf5ef2aSThomas Huth #endif 3250fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_y); 3251fcf5ef2aSThomas Huth break; 3252fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3253fcf5ef2aSThomas Huth case 0x2: /* V9 rdccr */ 3254fcf5ef2aSThomas Huth update_psr(dc); 3255ad75a51eSRichard Henderson gen_helper_rdccr(cpu_dst, tcg_env); 3256fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3257fcf5ef2aSThomas Huth break; 3258fcf5ef2aSThomas Huth case 0x3: /* V9 rdasi */ 3259fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_dst, dc->asi); 3260fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3261fcf5ef2aSThomas Huth break; 3262fcf5ef2aSThomas Huth case 0x4: /* V9 rdtick */ 3263fcf5ef2aSThomas Huth { 3264fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 3265fcf5ef2aSThomas Huth TCGv_i32 r_const; 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 326800ab7e61SRichard Henderson r_const = tcg_constant_i32(dc->mem_idx); 3269ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 3270fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tick)); 3271dfd1b812SRichard Henderson if (translator_io_start(&dc->base)) { 3272dfd1b812SRichard Henderson dc->base.is_jmp = DISAS_EXIT; 327346bb0137SMark Cave-Ayland } 3274ad75a51eSRichard Henderson gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr, 3275fcf5ef2aSThomas Huth r_const); 3276fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3277fcf5ef2aSThomas Huth } 3278fcf5ef2aSThomas Huth break; 3279fcf5ef2aSThomas Huth case 0x5: /* V9 rdpc */ 3280fcf5ef2aSThomas Huth { 3281fcf5ef2aSThomas Huth TCGv t = gen_dest_gpr(dc, rd); 3282fcf5ef2aSThomas Huth if (unlikely(AM_CHECK(dc))) { 3283fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL); 3284fcf5ef2aSThomas Huth } else { 3285fcf5ef2aSThomas Huth tcg_gen_movi_tl(t, dc->pc); 3286fcf5ef2aSThomas Huth } 3287fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, t); 3288fcf5ef2aSThomas Huth } 3289fcf5ef2aSThomas Huth break; 3290fcf5ef2aSThomas Huth case 0x6: /* V9 rdfprs */ 3291fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); 3292fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3293fcf5ef2aSThomas Huth break; 3294fcf5ef2aSThomas Huth case 0xf: /* V9 membar */ 3295fcf5ef2aSThomas Huth break; /* no effect */ 3296fcf5ef2aSThomas Huth case 0x13: /* Graphics Status */ 3297fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 3298fcf5ef2aSThomas Huth goto jmp_insn; 3299fcf5ef2aSThomas Huth } 3300fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_gsr); 3301fcf5ef2aSThomas Huth break; 3302fcf5ef2aSThomas Huth case 0x16: /* Softint */ 3303ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_dst, tcg_env, 3304fcf5ef2aSThomas Huth offsetof(CPUSPARCState, softint)); 3305fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3306fcf5ef2aSThomas Huth break; 3307fcf5ef2aSThomas Huth case 0x17: /* Tick compare */ 3308fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_tick_cmpr); 3309fcf5ef2aSThomas Huth break; 3310fcf5ef2aSThomas Huth case 0x18: /* System tick */ 3311fcf5ef2aSThomas Huth { 3312fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 3313fcf5ef2aSThomas Huth TCGv_i32 r_const; 3314fcf5ef2aSThomas Huth 3315fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 331600ab7e61SRichard Henderson r_const = tcg_constant_i32(dc->mem_idx); 3317ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 3318fcf5ef2aSThomas Huth offsetof(CPUSPARCState, stick)); 3319dfd1b812SRichard Henderson if (translator_io_start(&dc->base)) { 3320dfd1b812SRichard Henderson dc->base.is_jmp = DISAS_EXIT; 332146bb0137SMark Cave-Ayland } 3322ad75a51eSRichard Henderson gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr, 3323fcf5ef2aSThomas Huth r_const); 3324fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3325fcf5ef2aSThomas Huth } 3326fcf5ef2aSThomas Huth break; 3327fcf5ef2aSThomas Huth case 0x19: /* System tick compare */ 3328fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_stick_cmpr); 3329fcf5ef2aSThomas Huth break; 3330b8e31b3cSArtyom Tarasenko case 0x1a: /* UltraSPARC-T1 Strand status */ 3331b8e31b3cSArtyom Tarasenko /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe 3332b8e31b3cSArtyom Tarasenko * this ASR as impl. dep 3333b8e31b3cSArtyom Tarasenko */ 3334b8e31b3cSArtyom Tarasenko CHECK_IU_FEATURE(dc, HYPV); 3335b8e31b3cSArtyom Tarasenko { 3336b8e31b3cSArtyom Tarasenko TCGv t = gen_dest_gpr(dc, rd); 3337b8e31b3cSArtyom Tarasenko tcg_gen_movi_tl(t, 1UL); 3338b8e31b3cSArtyom Tarasenko gen_store_gpr(dc, rd, t); 3339b8e31b3cSArtyom Tarasenko } 3340b8e31b3cSArtyom Tarasenko break; 3341fcf5ef2aSThomas Huth case 0x10: /* Performance Control */ 3342fcf5ef2aSThomas Huth case 0x11: /* Performance Instrumentation Counter */ 3343fcf5ef2aSThomas Huth case 0x12: /* Dispatch Control */ 3344fcf5ef2aSThomas Huth case 0x14: /* Softint set, WO */ 3345fcf5ef2aSThomas Huth case 0x15: /* Softint clear, WO */ 3346fcf5ef2aSThomas Huth #endif 3347fcf5ef2aSThomas Huth default: 3348fcf5ef2aSThomas Huth goto illegal_insn; 3349fcf5ef2aSThomas Huth } 3350fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3351fcf5ef2aSThomas Huth } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ 3352fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 3353fcf5ef2aSThomas Huth if (!supervisor(dc)) { 3354fcf5ef2aSThomas Huth goto priv_insn; 3355fcf5ef2aSThomas Huth } 3356fcf5ef2aSThomas Huth update_psr(dc); 3357ad75a51eSRichard Henderson gen_helper_rdpsr(cpu_dst, tcg_env); 3358fcf5ef2aSThomas Huth #else 3359fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, HYPV); 3360fcf5ef2aSThomas Huth if (!hypervisor(dc)) 3361fcf5ef2aSThomas Huth goto priv_insn; 3362fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3363fcf5ef2aSThomas Huth switch (rs1) { 3364fcf5ef2aSThomas Huth case 0: // hpstate 3365ad75a51eSRichard Henderson tcg_gen_ld_i64(cpu_dst, tcg_env, 3366f7f17ef7SArtyom Tarasenko offsetof(CPUSPARCState, hpstate)); 3367fcf5ef2aSThomas Huth break; 3368fcf5ef2aSThomas Huth case 1: // htstate 3369fcf5ef2aSThomas Huth // gen_op_rdhtstate(); 3370fcf5ef2aSThomas Huth break; 3371fcf5ef2aSThomas Huth case 3: // hintp 3372fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_dst, cpu_hintp); 3373fcf5ef2aSThomas Huth break; 3374fcf5ef2aSThomas Huth case 5: // htba 3375fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_dst, cpu_htba); 3376fcf5ef2aSThomas Huth break; 3377fcf5ef2aSThomas Huth case 6: // hver 3378fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_dst, cpu_hver); 3379fcf5ef2aSThomas Huth break; 3380fcf5ef2aSThomas Huth case 31: // hstick_cmpr 3381fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); 3382fcf5ef2aSThomas Huth break; 3383fcf5ef2aSThomas Huth default: 3384fcf5ef2aSThomas Huth goto illegal_insn; 3385fcf5ef2aSThomas Huth } 3386fcf5ef2aSThomas Huth #endif 3387fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3388fcf5ef2aSThomas Huth break; 3389fcf5ef2aSThomas Huth } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ 3390fcf5ef2aSThomas Huth if (!supervisor(dc)) { 3391fcf5ef2aSThomas Huth goto priv_insn; 3392fcf5ef2aSThomas Huth } 339352123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 3394fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3395fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3396fcf5ef2aSThomas Huth switch (rs1) { 3397fcf5ef2aSThomas Huth case 0: // tpc 3398fcf5ef2aSThomas Huth { 3399fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 3402ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 3403fcf5ef2aSThomas Huth tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3404fcf5ef2aSThomas Huth offsetof(trap_state, tpc)); 3405fcf5ef2aSThomas Huth } 3406fcf5ef2aSThomas Huth break; 3407fcf5ef2aSThomas Huth case 1: // tnpc 3408fcf5ef2aSThomas Huth { 3409fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 3410fcf5ef2aSThomas Huth 3411fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 3412ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 3413fcf5ef2aSThomas Huth tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3414fcf5ef2aSThomas Huth offsetof(trap_state, tnpc)); 3415fcf5ef2aSThomas Huth } 3416fcf5ef2aSThomas Huth break; 3417fcf5ef2aSThomas Huth case 2: // tstate 3418fcf5ef2aSThomas Huth { 3419fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 3420fcf5ef2aSThomas Huth 3421fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 3422ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 3423fcf5ef2aSThomas Huth tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3424fcf5ef2aSThomas Huth offsetof(trap_state, tstate)); 3425fcf5ef2aSThomas Huth } 3426fcf5ef2aSThomas Huth break; 3427fcf5ef2aSThomas Huth case 3: // tt 3428fcf5ef2aSThomas Huth { 3429fcf5ef2aSThomas Huth TCGv_ptr r_tsptr = tcg_temp_new_ptr(); 3430fcf5ef2aSThomas Huth 3431ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 3432fcf5ef2aSThomas Huth tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, 3433fcf5ef2aSThomas Huth offsetof(trap_state, tt)); 3434fcf5ef2aSThomas Huth } 3435fcf5ef2aSThomas Huth break; 3436fcf5ef2aSThomas Huth case 4: // tick 3437fcf5ef2aSThomas Huth { 3438fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 3439fcf5ef2aSThomas Huth TCGv_i32 r_const; 3440fcf5ef2aSThomas Huth 3441fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 344200ab7e61SRichard Henderson r_const = tcg_constant_i32(dc->mem_idx); 3443ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 3444fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tick)); 3445dfd1b812SRichard Henderson if (translator_io_start(&dc->base)) { 3446dfd1b812SRichard Henderson dc->base.is_jmp = DISAS_EXIT; 344746bb0137SMark Cave-Ayland } 3448ad75a51eSRichard Henderson gen_helper_tick_get_count(cpu_tmp0, tcg_env, 3449fcf5ef2aSThomas Huth r_tickptr, r_const); 3450fcf5ef2aSThomas Huth } 3451fcf5ef2aSThomas Huth break; 3452fcf5ef2aSThomas Huth case 5: // tba 3453fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); 3454fcf5ef2aSThomas Huth break; 3455fcf5ef2aSThomas Huth case 6: // pstate 3456ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3457fcf5ef2aSThomas Huth offsetof(CPUSPARCState, pstate)); 3458fcf5ef2aSThomas Huth break; 3459fcf5ef2aSThomas Huth case 7: // tl 3460ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3461fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tl)); 3462fcf5ef2aSThomas Huth break; 3463fcf5ef2aSThomas Huth case 8: // pil 3464ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3465fcf5ef2aSThomas Huth offsetof(CPUSPARCState, psrpil)); 3466fcf5ef2aSThomas Huth break; 3467fcf5ef2aSThomas Huth case 9: // cwp 3468ad75a51eSRichard Henderson gen_helper_rdcwp(cpu_tmp0, tcg_env); 3469fcf5ef2aSThomas Huth break; 3470fcf5ef2aSThomas Huth case 10: // cansave 3471ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3472fcf5ef2aSThomas Huth offsetof(CPUSPARCState, cansave)); 3473fcf5ef2aSThomas Huth break; 3474fcf5ef2aSThomas Huth case 11: // canrestore 3475ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3476fcf5ef2aSThomas Huth offsetof(CPUSPARCState, canrestore)); 3477fcf5ef2aSThomas Huth break; 3478fcf5ef2aSThomas Huth case 12: // cleanwin 3479ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3480fcf5ef2aSThomas Huth offsetof(CPUSPARCState, cleanwin)); 3481fcf5ef2aSThomas Huth break; 3482fcf5ef2aSThomas Huth case 13: // otherwin 3483ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3484fcf5ef2aSThomas Huth offsetof(CPUSPARCState, otherwin)); 3485fcf5ef2aSThomas Huth break; 3486fcf5ef2aSThomas Huth case 14: // wstate 3487ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3488fcf5ef2aSThomas Huth offsetof(CPUSPARCState, wstate)); 3489fcf5ef2aSThomas Huth break; 3490fcf5ef2aSThomas Huth case 16: // UA2005 gl 3491fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, GL); 3492ad75a51eSRichard Henderson tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, 3493fcf5ef2aSThomas Huth offsetof(CPUSPARCState, gl)); 3494fcf5ef2aSThomas Huth break; 3495fcf5ef2aSThomas Huth case 26: // UA2005 strand status 3496fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, HYPV); 3497fcf5ef2aSThomas Huth if (!hypervisor(dc)) 3498fcf5ef2aSThomas Huth goto priv_insn; 3499fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); 3500fcf5ef2aSThomas Huth break; 3501fcf5ef2aSThomas Huth case 31: // ver 3502fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tmp0, cpu_ver); 3503fcf5ef2aSThomas Huth break; 3504fcf5ef2aSThomas Huth case 15: // fq 3505fcf5ef2aSThomas Huth default: 3506fcf5ef2aSThomas Huth goto illegal_insn; 3507fcf5ef2aSThomas Huth } 3508fcf5ef2aSThomas Huth #else 3509fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); 3510fcf5ef2aSThomas Huth #endif 3511fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_tmp0); 3512fcf5ef2aSThomas Huth break; 3513aa04c9d9SGiuseppe Musacchio #endif 3514aa04c9d9SGiuseppe Musacchio #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 3515fcf5ef2aSThomas Huth } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ 3516fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3517ad75a51eSRichard Henderson gen_helper_flushw(tcg_env); 3518fcf5ef2aSThomas Huth #else 3519fcf5ef2aSThomas Huth if (!supervisor(dc)) 3520fcf5ef2aSThomas Huth goto priv_insn; 3521fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_tbr); 3522fcf5ef2aSThomas Huth #endif 3523fcf5ef2aSThomas Huth break; 3524fcf5ef2aSThomas Huth #endif 3525fcf5ef2aSThomas Huth } else if (xop == 0x34) { /* FPU Operations */ 3526fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 3527fcf5ef2aSThomas Huth goto jmp_insn; 3528fcf5ef2aSThomas Huth } 3529fcf5ef2aSThomas Huth gen_op_clear_ieee_excp_and_FTT(); 3530fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3531fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3532fcf5ef2aSThomas Huth xop = GET_FIELD(insn, 18, 26); 3533fcf5ef2aSThomas Huth 3534fcf5ef2aSThomas Huth switch (xop) { 3535fcf5ef2aSThomas Huth case 0x1: /* fmovs */ 3536fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rs2); 3537fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_src1_32); 3538fcf5ef2aSThomas Huth break; 3539fcf5ef2aSThomas Huth case 0x5: /* fnegs */ 3540fcf5ef2aSThomas Huth gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs); 3541fcf5ef2aSThomas Huth break; 3542fcf5ef2aSThomas Huth case 0x9: /* fabss */ 3543fcf5ef2aSThomas Huth gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); 3544fcf5ef2aSThomas Huth break; 3545fcf5ef2aSThomas Huth case 0x29: /* fsqrts */ 3546fcf5ef2aSThomas Huth gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); 3547fcf5ef2aSThomas Huth break; 3548fcf5ef2aSThomas Huth case 0x2a: /* fsqrtd */ 3549fcf5ef2aSThomas Huth gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); 3550fcf5ef2aSThomas Huth break; 3551fcf5ef2aSThomas Huth case 0x2b: /* fsqrtq */ 3552fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3553fcf5ef2aSThomas Huth gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); 3554fcf5ef2aSThomas Huth break; 3555fcf5ef2aSThomas Huth case 0x41: /* fadds */ 3556fcf5ef2aSThomas Huth gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); 3557fcf5ef2aSThomas Huth break; 3558fcf5ef2aSThomas Huth case 0x42: /* faddd */ 3559fcf5ef2aSThomas Huth gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); 3560fcf5ef2aSThomas Huth break; 3561fcf5ef2aSThomas Huth case 0x43: /* faddq */ 3562fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3563fcf5ef2aSThomas Huth gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); 3564fcf5ef2aSThomas Huth break; 3565fcf5ef2aSThomas Huth case 0x45: /* fsubs */ 3566fcf5ef2aSThomas Huth gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); 3567fcf5ef2aSThomas Huth break; 3568fcf5ef2aSThomas Huth case 0x46: /* fsubd */ 3569fcf5ef2aSThomas Huth gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); 3570fcf5ef2aSThomas Huth break; 3571fcf5ef2aSThomas Huth case 0x47: /* fsubq */ 3572fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3573fcf5ef2aSThomas Huth gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); 3574fcf5ef2aSThomas Huth break; 3575fcf5ef2aSThomas Huth case 0x49: /* fmuls */ 3576fcf5ef2aSThomas Huth gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); 3577fcf5ef2aSThomas Huth break; 3578fcf5ef2aSThomas Huth case 0x4a: /* fmuld */ 3579fcf5ef2aSThomas Huth gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); 3580fcf5ef2aSThomas Huth break; 3581fcf5ef2aSThomas Huth case 0x4b: /* fmulq */ 3582fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3583fcf5ef2aSThomas Huth gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); 3584fcf5ef2aSThomas Huth break; 3585fcf5ef2aSThomas Huth case 0x4d: /* fdivs */ 3586fcf5ef2aSThomas Huth gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); 3587fcf5ef2aSThomas Huth break; 3588fcf5ef2aSThomas Huth case 0x4e: /* fdivd */ 3589fcf5ef2aSThomas Huth gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); 3590fcf5ef2aSThomas Huth break; 3591fcf5ef2aSThomas Huth case 0x4f: /* fdivq */ 3592fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3593fcf5ef2aSThomas Huth gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); 3594fcf5ef2aSThomas Huth break; 3595fcf5ef2aSThomas Huth case 0x69: /* fsmuld */ 3596fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FSMULD); 3597fcf5ef2aSThomas Huth gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); 3598fcf5ef2aSThomas Huth break; 3599fcf5ef2aSThomas Huth case 0x6e: /* fdmulq */ 3600fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3601fcf5ef2aSThomas Huth gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); 3602fcf5ef2aSThomas Huth break; 3603fcf5ef2aSThomas Huth case 0xc4: /* fitos */ 3604fcf5ef2aSThomas Huth gen_fop_FF(dc, rd, rs2, gen_helper_fitos); 3605fcf5ef2aSThomas Huth break; 3606fcf5ef2aSThomas Huth case 0xc6: /* fdtos */ 3607fcf5ef2aSThomas Huth gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); 3608fcf5ef2aSThomas Huth break; 3609fcf5ef2aSThomas Huth case 0xc7: /* fqtos */ 3610fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3611fcf5ef2aSThomas Huth gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); 3612fcf5ef2aSThomas Huth break; 3613fcf5ef2aSThomas Huth case 0xc8: /* fitod */ 3614fcf5ef2aSThomas Huth gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod); 3615fcf5ef2aSThomas Huth break; 3616fcf5ef2aSThomas Huth case 0xc9: /* fstod */ 3617fcf5ef2aSThomas Huth gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod); 3618fcf5ef2aSThomas Huth break; 3619fcf5ef2aSThomas Huth case 0xcb: /* fqtod */ 3620fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3621fcf5ef2aSThomas Huth gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); 3622fcf5ef2aSThomas Huth break; 3623fcf5ef2aSThomas Huth case 0xcc: /* fitoq */ 3624fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3625fcf5ef2aSThomas Huth gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); 3626fcf5ef2aSThomas Huth break; 3627fcf5ef2aSThomas Huth case 0xcd: /* fstoq */ 3628fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3629fcf5ef2aSThomas Huth gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq); 3630fcf5ef2aSThomas Huth break; 3631fcf5ef2aSThomas Huth case 0xce: /* fdtoq */ 3632fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3633fcf5ef2aSThomas Huth gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); 3634fcf5ef2aSThomas Huth break; 3635fcf5ef2aSThomas Huth case 0xd1: /* fstoi */ 3636fcf5ef2aSThomas Huth gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); 3637fcf5ef2aSThomas Huth break; 3638fcf5ef2aSThomas Huth case 0xd2: /* fdtoi */ 3639fcf5ef2aSThomas Huth gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); 3640fcf5ef2aSThomas Huth break; 3641fcf5ef2aSThomas Huth case 0xd3: /* fqtoi */ 3642fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3643fcf5ef2aSThomas Huth gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); 3644fcf5ef2aSThomas Huth break; 3645fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3646fcf5ef2aSThomas Huth case 0x2: /* V9 fmovd */ 3647fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs2); 3648fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_src1_64); 3649fcf5ef2aSThomas Huth break; 3650fcf5ef2aSThomas Huth case 0x3: /* V9 fmovq */ 3651fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3652fcf5ef2aSThomas Huth gen_move_Q(dc, rd, rs2); 3653fcf5ef2aSThomas Huth break; 3654fcf5ef2aSThomas Huth case 0x6: /* V9 fnegd */ 3655fcf5ef2aSThomas Huth gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); 3656fcf5ef2aSThomas Huth break; 3657fcf5ef2aSThomas Huth case 0x7: /* V9 fnegq */ 3658fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3659fcf5ef2aSThomas Huth gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); 3660fcf5ef2aSThomas Huth break; 3661fcf5ef2aSThomas Huth case 0xa: /* V9 fabsd */ 3662fcf5ef2aSThomas Huth gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd); 3663fcf5ef2aSThomas Huth break; 3664fcf5ef2aSThomas Huth case 0xb: /* V9 fabsq */ 3665fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3666fcf5ef2aSThomas Huth gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); 3667fcf5ef2aSThomas Huth break; 3668fcf5ef2aSThomas Huth case 0x81: /* V9 fstox */ 3669fcf5ef2aSThomas Huth gen_fop_DF(dc, rd, rs2, gen_helper_fstox); 3670fcf5ef2aSThomas Huth break; 3671fcf5ef2aSThomas Huth case 0x82: /* V9 fdtox */ 3672fcf5ef2aSThomas Huth gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); 3673fcf5ef2aSThomas Huth break; 3674fcf5ef2aSThomas Huth case 0x83: /* V9 fqtox */ 3675fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3676fcf5ef2aSThomas Huth gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); 3677fcf5ef2aSThomas Huth break; 3678fcf5ef2aSThomas Huth case 0x84: /* V9 fxtos */ 3679fcf5ef2aSThomas Huth gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); 3680fcf5ef2aSThomas Huth break; 3681fcf5ef2aSThomas Huth case 0x88: /* V9 fxtod */ 3682fcf5ef2aSThomas Huth gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); 3683fcf5ef2aSThomas Huth break; 3684fcf5ef2aSThomas Huth case 0x8c: /* V9 fxtoq */ 3685fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3686fcf5ef2aSThomas Huth gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); 3687fcf5ef2aSThomas Huth break; 3688fcf5ef2aSThomas Huth #endif 3689fcf5ef2aSThomas Huth default: 3690fcf5ef2aSThomas Huth goto illegal_insn; 3691fcf5ef2aSThomas Huth } 3692fcf5ef2aSThomas Huth } else if (xop == 0x35) { /* FPU Operations */ 3693fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3694fcf5ef2aSThomas Huth int cond; 3695fcf5ef2aSThomas Huth #endif 3696fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 3697fcf5ef2aSThomas Huth goto jmp_insn; 3698fcf5ef2aSThomas Huth } 3699fcf5ef2aSThomas Huth gen_op_clear_ieee_excp_and_FTT(); 3700fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3701fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3702fcf5ef2aSThomas Huth xop = GET_FIELD(insn, 18, 26); 3703fcf5ef2aSThomas Huth 3704fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3705fcf5ef2aSThomas Huth #define FMOVR(sz) \ 3706fcf5ef2aSThomas Huth do { \ 3707fcf5ef2aSThomas Huth DisasCompare cmp; \ 3708fcf5ef2aSThomas Huth cond = GET_FIELD_SP(insn, 10, 12); \ 3709fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); \ 3710fcf5ef2aSThomas Huth gen_compare_reg(&cmp, cond, cpu_src1); \ 3711fcf5ef2aSThomas Huth gen_fmov##sz(dc, &cmp, rd, rs2); \ 3712fcf5ef2aSThomas Huth } while (0) 3713fcf5ef2aSThomas Huth 3714fcf5ef2aSThomas Huth if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */ 3715fcf5ef2aSThomas Huth FMOVR(s); 3716fcf5ef2aSThomas Huth break; 3717fcf5ef2aSThomas Huth } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr 3718fcf5ef2aSThomas Huth FMOVR(d); 3719fcf5ef2aSThomas Huth break; 3720fcf5ef2aSThomas Huth } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr 3721fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3722fcf5ef2aSThomas Huth FMOVR(q); 3723fcf5ef2aSThomas Huth break; 3724fcf5ef2aSThomas Huth } 3725fcf5ef2aSThomas Huth #undef FMOVR 3726fcf5ef2aSThomas Huth #endif 3727fcf5ef2aSThomas Huth switch (xop) { 3728fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3729fcf5ef2aSThomas Huth #define FMOVCC(fcc, sz) \ 3730fcf5ef2aSThomas Huth do { \ 3731fcf5ef2aSThomas Huth DisasCompare cmp; \ 3732fcf5ef2aSThomas Huth cond = GET_FIELD_SP(insn, 14, 17); \ 3733fcf5ef2aSThomas Huth gen_fcompare(&cmp, fcc, cond); \ 3734fcf5ef2aSThomas Huth gen_fmov##sz(dc, &cmp, rd, rs2); \ 3735fcf5ef2aSThomas Huth } while (0) 3736fcf5ef2aSThomas Huth 3737fcf5ef2aSThomas Huth case 0x001: /* V9 fmovscc %fcc0 */ 3738fcf5ef2aSThomas Huth FMOVCC(0, s); 3739fcf5ef2aSThomas Huth break; 3740fcf5ef2aSThomas Huth case 0x002: /* V9 fmovdcc %fcc0 */ 3741fcf5ef2aSThomas Huth FMOVCC(0, d); 3742fcf5ef2aSThomas Huth break; 3743fcf5ef2aSThomas Huth case 0x003: /* V9 fmovqcc %fcc0 */ 3744fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3745fcf5ef2aSThomas Huth FMOVCC(0, q); 3746fcf5ef2aSThomas Huth break; 3747fcf5ef2aSThomas Huth case 0x041: /* V9 fmovscc %fcc1 */ 3748fcf5ef2aSThomas Huth FMOVCC(1, s); 3749fcf5ef2aSThomas Huth break; 3750fcf5ef2aSThomas Huth case 0x042: /* V9 fmovdcc %fcc1 */ 3751fcf5ef2aSThomas Huth FMOVCC(1, d); 3752fcf5ef2aSThomas Huth break; 3753fcf5ef2aSThomas Huth case 0x043: /* V9 fmovqcc %fcc1 */ 3754fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3755fcf5ef2aSThomas Huth FMOVCC(1, q); 3756fcf5ef2aSThomas Huth break; 3757fcf5ef2aSThomas Huth case 0x081: /* V9 fmovscc %fcc2 */ 3758fcf5ef2aSThomas Huth FMOVCC(2, s); 3759fcf5ef2aSThomas Huth break; 3760fcf5ef2aSThomas Huth case 0x082: /* V9 fmovdcc %fcc2 */ 3761fcf5ef2aSThomas Huth FMOVCC(2, d); 3762fcf5ef2aSThomas Huth break; 3763fcf5ef2aSThomas Huth case 0x083: /* V9 fmovqcc %fcc2 */ 3764fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3765fcf5ef2aSThomas Huth FMOVCC(2, q); 3766fcf5ef2aSThomas Huth break; 3767fcf5ef2aSThomas Huth case 0x0c1: /* V9 fmovscc %fcc3 */ 3768fcf5ef2aSThomas Huth FMOVCC(3, s); 3769fcf5ef2aSThomas Huth break; 3770fcf5ef2aSThomas Huth case 0x0c2: /* V9 fmovdcc %fcc3 */ 3771fcf5ef2aSThomas Huth FMOVCC(3, d); 3772fcf5ef2aSThomas Huth break; 3773fcf5ef2aSThomas Huth case 0x0c3: /* V9 fmovqcc %fcc3 */ 3774fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3775fcf5ef2aSThomas Huth FMOVCC(3, q); 3776fcf5ef2aSThomas Huth break; 3777fcf5ef2aSThomas Huth #undef FMOVCC 3778fcf5ef2aSThomas Huth #define FMOVCC(xcc, sz) \ 3779fcf5ef2aSThomas Huth do { \ 3780fcf5ef2aSThomas Huth DisasCompare cmp; \ 3781fcf5ef2aSThomas Huth cond = GET_FIELD_SP(insn, 14, 17); \ 3782fcf5ef2aSThomas Huth gen_compare(&cmp, xcc, cond, dc); \ 3783fcf5ef2aSThomas Huth gen_fmov##sz(dc, &cmp, rd, rs2); \ 3784fcf5ef2aSThomas Huth } while (0) 3785fcf5ef2aSThomas Huth 3786fcf5ef2aSThomas Huth case 0x101: /* V9 fmovscc %icc */ 3787fcf5ef2aSThomas Huth FMOVCC(0, s); 3788fcf5ef2aSThomas Huth break; 3789fcf5ef2aSThomas Huth case 0x102: /* V9 fmovdcc %icc */ 3790fcf5ef2aSThomas Huth FMOVCC(0, d); 3791fcf5ef2aSThomas Huth break; 3792fcf5ef2aSThomas Huth case 0x103: /* V9 fmovqcc %icc */ 3793fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3794fcf5ef2aSThomas Huth FMOVCC(0, q); 3795fcf5ef2aSThomas Huth break; 3796fcf5ef2aSThomas Huth case 0x181: /* V9 fmovscc %xcc */ 3797fcf5ef2aSThomas Huth FMOVCC(1, s); 3798fcf5ef2aSThomas Huth break; 3799fcf5ef2aSThomas Huth case 0x182: /* V9 fmovdcc %xcc */ 3800fcf5ef2aSThomas Huth FMOVCC(1, d); 3801fcf5ef2aSThomas Huth break; 3802fcf5ef2aSThomas Huth case 0x183: /* V9 fmovqcc %xcc */ 3803fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3804fcf5ef2aSThomas Huth FMOVCC(1, q); 3805fcf5ef2aSThomas Huth break; 3806fcf5ef2aSThomas Huth #undef FMOVCC 3807fcf5ef2aSThomas Huth #endif 3808fcf5ef2aSThomas Huth case 0x51: /* fcmps, V9 %fcc */ 3809fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rs1); 3810fcf5ef2aSThomas Huth cpu_src2_32 = gen_load_fpr_F(dc, rs2); 3811fcf5ef2aSThomas Huth gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); 3812fcf5ef2aSThomas Huth break; 3813fcf5ef2aSThomas Huth case 0x52: /* fcmpd, V9 %fcc */ 3814fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 3815fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 3816fcf5ef2aSThomas Huth gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64); 3817fcf5ef2aSThomas Huth break; 3818fcf5ef2aSThomas Huth case 0x53: /* fcmpq, V9 %fcc */ 3819fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3820fcf5ef2aSThomas Huth gen_op_load_fpr_QT0(QFPREG(rs1)); 3821fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs2)); 3822fcf5ef2aSThomas Huth gen_op_fcmpq(rd & 3); 3823fcf5ef2aSThomas Huth break; 3824fcf5ef2aSThomas Huth case 0x55: /* fcmpes, V9 %fcc */ 3825fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rs1); 3826fcf5ef2aSThomas Huth cpu_src2_32 = gen_load_fpr_F(dc, rs2); 3827fcf5ef2aSThomas Huth gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); 3828fcf5ef2aSThomas Huth break; 3829fcf5ef2aSThomas Huth case 0x56: /* fcmped, V9 %fcc */ 3830fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 3831fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 3832fcf5ef2aSThomas Huth gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64); 3833fcf5ef2aSThomas Huth break; 3834fcf5ef2aSThomas Huth case 0x57: /* fcmpeq, V9 %fcc */ 3835fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 3836fcf5ef2aSThomas Huth gen_op_load_fpr_QT0(QFPREG(rs1)); 3837fcf5ef2aSThomas Huth gen_op_load_fpr_QT1(QFPREG(rs2)); 3838fcf5ef2aSThomas Huth gen_op_fcmpeq(rd & 3); 3839fcf5ef2aSThomas Huth break; 3840fcf5ef2aSThomas Huth default: 3841fcf5ef2aSThomas Huth goto illegal_insn; 3842fcf5ef2aSThomas Huth } 3843fcf5ef2aSThomas Huth } else if (xop == 0x2) { 3844fcf5ef2aSThomas Huth TCGv dst = gen_dest_gpr(dc, rd); 3845fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 3846fcf5ef2aSThomas Huth if (rs1 == 0) { 3847fcf5ef2aSThomas Huth /* clr/mov shortcut : or %g0, x, y -> mov x, y */ 3848fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 3849fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 19, 31); 3850fcf5ef2aSThomas Huth tcg_gen_movi_tl(dst, simm); 3851fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 3852fcf5ef2aSThomas Huth } else { /* register */ 3853fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3854fcf5ef2aSThomas Huth if (rs2 == 0) { 3855fcf5ef2aSThomas Huth tcg_gen_movi_tl(dst, 0); 3856fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 3857fcf5ef2aSThomas Huth } else { 3858fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 3859fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_src2); 3860fcf5ef2aSThomas Huth } 3861fcf5ef2aSThomas Huth } 3862fcf5ef2aSThomas Huth } else { 3863fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 3864fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 3865fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 19, 31); 3866fcf5ef2aSThomas Huth tcg_gen_ori_tl(dst, cpu_src1, simm); 3867fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 3868fcf5ef2aSThomas Huth } else { /* register */ 3869fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3870fcf5ef2aSThomas Huth if (rs2 == 0) { 3871fcf5ef2aSThomas Huth /* mov shortcut: or x, %g0, y -> mov x, y */ 3872fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_src1); 3873fcf5ef2aSThomas Huth } else { 3874fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 3875fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, cpu_src1, cpu_src2); 3876fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 3877fcf5ef2aSThomas Huth } 3878fcf5ef2aSThomas Huth } 3879fcf5ef2aSThomas Huth } 3880fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 3881fcf5ef2aSThomas Huth } else if (xop == 0x25) { /* sll, V9 sllx */ 3882fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 3883fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 3884fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 3885fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3886fcf5ef2aSThomas Huth tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f); 3887fcf5ef2aSThomas Huth } else { 3888fcf5ef2aSThomas Huth tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f); 3889fcf5ef2aSThomas Huth } 3890fcf5ef2aSThomas Huth } else { /* register */ 3891fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3892fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 389352123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 3894fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3895fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 3896fcf5ef2aSThomas Huth } else { 3897fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 3898fcf5ef2aSThomas Huth } 3899fcf5ef2aSThomas Huth tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); 3900fcf5ef2aSThomas Huth } 3901fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3902fcf5ef2aSThomas Huth } else if (xop == 0x26) { /* srl, V9 srlx */ 3903fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 3904fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 3905fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 3906fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3907fcf5ef2aSThomas Huth tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f); 3908fcf5ef2aSThomas Huth } else { 3909fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 3910fcf5ef2aSThomas Huth tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f); 3911fcf5ef2aSThomas Huth } 3912fcf5ef2aSThomas Huth } else { /* register */ 3913fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3914fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 391552123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 3916fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3917fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 3918fcf5ef2aSThomas Huth tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); 3919fcf5ef2aSThomas Huth } else { 3920fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 3921fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 3922fcf5ef2aSThomas Huth tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); 3923fcf5ef2aSThomas Huth } 3924fcf5ef2aSThomas Huth } 3925fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3926fcf5ef2aSThomas Huth } else if (xop == 0x27) { /* sra, V9 srax */ 3927fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 3928fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 3929fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 3930fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3931fcf5ef2aSThomas Huth tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f); 3932fcf5ef2aSThomas Huth } else { 3933fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(cpu_dst, cpu_src1); 3934fcf5ef2aSThomas Huth tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f); 3935fcf5ef2aSThomas Huth } 3936fcf5ef2aSThomas Huth } else { /* register */ 3937fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 3938fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 393952123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 3940fcf5ef2aSThomas Huth if (insn & (1 << 12)) { 3941fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 3942fcf5ef2aSThomas Huth tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); 3943fcf5ef2aSThomas Huth } else { 3944fcf5ef2aSThomas Huth tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 3945fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(cpu_dst, cpu_src1); 3946fcf5ef2aSThomas Huth tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); 3947fcf5ef2aSThomas Huth } 3948fcf5ef2aSThomas Huth } 3949fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 3950fcf5ef2aSThomas Huth #endif 3951fcf5ef2aSThomas Huth } else if (xop < 0x36) { 3952fcf5ef2aSThomas Huth if (xop < 0x20) { 3953fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 3954fcf5ef2aSThomas Huth cpu_src2 = get_src2(dc, insn); 3955fcf5ef2aSThomas Huth switch (xop & ~0x10) { 3956fcf5ef2aSThomas Huth case 0x0: /* add */ 3957fcf5ef2aSThomas Huth if (xop & 0x10) { 3958fcf5ef2aSThomas Huth gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); 3959fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); 3960fcf5ef2aSThomas Huth dc->cc_op = CC_OP_ADD; 3961fcf5ef2aSThomas Huth } else { 3962fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); 3963fcf5ef2aSThomas Huth } 3964fcf5ef2aSThomas Huth break; 3965fcf5ef2aSThomas Huth case 0x1: /* and */ 3966fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); 3967fcf5ef2aSThomas Huth if (xop & 0x10) { 3968fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 3969fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 3970fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 3971fcf5ef2aSThomas Huth } 3972fcf5ef2aSThomas Huth break; 3973fcf5ef2aSThomas Huth case 0x2: /* or */ 3974fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); 3975fcf5ef2aSThomas Huth if (xop & 0x10) { 3976fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 3977fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 3978fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 3979fcf5ef2aSThomas Huth } 3980fcf5ef2aSThomas Huth break; 3981fcf5ef2aSThomas Huth case 0x3: /* xor */ 3982fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); 3983fcf5ef2aSThomas Huth if (xop & 0x10) { 3984fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 3985fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 3986fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 3987fcf5ef2aSThomas Huth } 3988fcf5ef2aSThomas Huth break; 3989fcf5ef2aSThomas Huth case 0x4: /* sub */ 3990fcf5ef2aSThomas Huth if (xop & 0x10) { 3991fcf5ef2aSThomas Huth gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); 3992fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); 3993fcf5ef2aSThomas Huth dc->cc_op = CC_OP_SUB; 3994fcf5ef2aSThomas Huth } else { 3995fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); 3996fcf5ef2aSThomas Huth } 3997fcf5ef2aSThomas Huth break; 3998fcf5ef2aSThomas Huth case 0x5: /* andn */ 3999fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); 4000fcf5ef2aSThomas Huth if (xop & 0x10) { 4001fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4002fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4003fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 4004fcf5ef2aSThomas Huth } 4005fcf5ef2aSThomas Huth break; 4006fcf5ef2aSThomas Huth case 0x6: /* orn */ 4007fcf5ef2aSThomas Huth tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); 4008fcf5ef2aSThomas Huth if (xop & 0x10) { 4009fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4010fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4011fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 4012fcf5ef2aSThomas Huth } 4013fcf5ef2aSThomas Huth break; 4014fcf5ef2aSThomas Huth case 0x7: /* xorn */ 4015fcf5ef2aSThomas Huth tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2); 4016fcf5ef2aSThomas Huth if (xop & 0x10) { 4017fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4018fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4019fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 4020fcf5ef2aSThomas Huth } 4021fcf5ef2aSThomas Huth break; 4022fcf5ef2aSThomas Huth case 0x8: /* addx, V9 addc */ 4023fcf5ef2aSThomas Huth gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, 4024fcf5ef2aSThomas Huth (xop & 0x10)); 4025fcf5ef2aSThomas Huth break; 4026fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4027fcf5ef2aSThomas Huth case 0x9: /* V9 mulx */ 4028fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); 4029fcf5ef2aSThomas Huth break; 4030fcf5ef2aSThomas Huth #endif 4031fcf5ef2aSThomas Huth case 0xa: /* umul */ 4032fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, MUL); 4033fcf5ef2aSThomas Huth gen_op_umul(cpu_dst, cpu_src1, cpu_src2); 4034fcf5ef2aSThomas Huth if (xop & 0x10) { 4035fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4036fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4037fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 4038fcf5ef2aSThomas Huth } 4039fcf5ef2aSThomas Huth break; 4040fcf5ef2aSThomas Huth case 0xb: /* smul */ 4041fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, MUL); 4042fcf5ef2aSThomas Huth gen_op_smul(cpu_dst, cpu_src1, cpu_src2); 4043fcf5ef2aSThomas Huth if (xop & 0x10) { 4044fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4045fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4046fcf5ef2aSThomas Huth dc->cc_op = CC_OP_LOGIC; 4047fcf5ef2aSThomas Huth } 4048fcf5ef2aSThomas Huth break; 4049fcf5ef2aSThomas Huth case 0xc: /* subx, V9 subc */ 4050fcf5ef2aSThomas Huth gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, 4051fcf5ef2aSThomas Huth (xop & 0x10)); 4052fcf5ef2aSThomas Huth break; 4053fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4054fcf5ef2aSThomas Huth case 0xd: /* V9 udivx */ 4055ad75a51eSRichard Henderson gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); 4056fcf5ef2aSThomas Huth break; 4057fcf5ef2aSThomas Huth #endif 4058fcf5ef2aSThomas Huth case 0xe: /* udiv */ 4059fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, DIV); 4060fcf5ef2aSThomas Huth if (xop & 0x10) { 4061ad75a51eSRichard Henderson gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, 4062fcf5ef2aSThomas Huth cpu_src2); 4063fcf5ef2aSThomas Huth dc->cc_op = CC_OP_DIV; 4064fcf5ef2aSThomas Huth } else { 4065ad75a51eSRichard Henderson gen_helper_udiv(cpu_dst, tcg_env, cpu_src1, 4066fcf5ef2aSThomas Huth cpu_src2); 4067fcf5ef2aSThomas Huth } 4068fcf5ef2aSThomas Huth break; 4069fcf5ef2aSThomas Huth case 0xf: /* sdiv */ 4070fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, DIV); 4071fcf5ef2aSThomas Huth if (xop & 0x10) { 4072ad75a51eSRichard Henderson gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, 4073fcf5ef2aSThomas Huth cpu_src2); 4074fcf5ef2aSThomas Huth dc->cc_op = CC_OP_DIV; 4075fcf5ef2aSThomas Huth } else { 4076ad75a51eSRichard Henderson gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1, 4077fcf5ef2aSThomas Huth cpu_src2); 4078fcf5ef2aSThomas Huth } 4079fcf5ef2aSThomas Huth break; 4080fcf5ef2aSThomas Huth default: 4081fcf5ef2aSThomas Huth goto illegal_insn; 4082fcf5ef2aSThomas Huth } 4083fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4084fcf5ef2aSThomas Huth } else { 4085fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 4086fcf5ef2aSThomas Huth cpu_src2 = get_src2(dc, insn); 4087fcf5ef2aSThomas Huth switch (xop) { 4088fcf5ef2aSThomas Huth case 0x20: /* taddcc */ 4089fcf5ef2aSThomas Huth gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); 4090fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4091fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); 4092fcf5ef2aSThomas Huth dc->cc_op = CC_OP_TADD; 4093fcf5ef2aSThomas Huth break; 4094fcf5ef2aSThomas Huth case 0x21: /* tsubcc */ 4095fcf5ef2aSThomas Huth gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); 4096fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4097fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); 4098fcf5ef2aSThomas Huth dc->cc_op = CC_OP_TSUB; 4099fcf5ef2aSThomas Huth break; 4100fcf5ef2aSThomas Huth case 0x22: /* taddcctv */ 4101ad75a51eSRichard Henderson gen_helper_taddcctv(cpu_dst, tcg_env, 4102fcf5ef2aSThomas Huth cpu_src1, cpu_src2); 4103fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4104fcf5ef2aSThomas Huth dc->cc_op = CC_OP_TADDTV; 4105fcf5ef2aSThomas Huth break; 4106fcf5ef2aSThomas Huth case 0x23: /* tsubcctv */ 4107ad75a51eSRichard Henderson gen_helper_tsubcctv(cpu_dst, tcg_env, 4108fcf5ef2aSThomas Huth cpu_src1, cpu_src2); 4109fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4110fcf5ef2aSThomas Huth dc->cc_op = CC_OP_TSUBTV; 4111fcf5ef2aSThomas Huth break; 4112fcf5ef2aSThomas Huth case 0x24: /* mulscc */ 4113fcf5ef2aSThomas Huth update_psr(dc); 4114fcf5ef2aSThomas Huth gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); 4115fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4116fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); 4117fcf5ef2aSThomas Huth dc->cc_op = CC_OP_ADD; 4118fcf5ef2aSThomas Huth break; 4119fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 4120fcf5ef2aSThomas Huth case 0x25: /* sll */ 4121fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 4122fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 4123fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f); 4124fcf5ef2aSThomas Huth } else { /* register */ 412552123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4126fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4127fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); 4128fcf5ef2aSThomas Huth } 4129fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4130fcf5ef2aSThomas Huth break; 4131fcf5ef2aSThomas Huth case 0x26: /* srl */ 4132fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 4133fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 4134fcf5ef2aSThomas Huth tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f); 4135fcf5ef2aSThomas Huth } else { /* register */ 413652123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4137fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4138fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); 4139fcf5ef2aSThomas Huth } 4140fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4141fcf5ef2aSThomas Huth break; 4142fcf5ef2aSThomas Huth case 0x27: /* sra */ 4143fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 4144fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 20, 31); 4145fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f); 4146fcf5ef2aSThomas Huth } else { /* register */ 414752123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4148fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4149fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); 4150fcf5ef2aSThomas Huth } 4151fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4152fcf5ef2aSThomas Huth break; 4153fcf5ef2aSThomas Huth #endif 4154fcf5ef2aSThomas Huth case 0x30: 4155fcf5ef2aSThomas Huth { 415652123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4157fcf5ef2aSThomas Huth switch(rd) { 4158fcf5ef2aSThomas Huth case 0: /* wry */ 4159fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4160fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); 4161fcf5ef2aSThomas Huth break; 4162fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 4163fcf5ef2aSThomas Huth case 0x01 ... 0x0f: /* undefined in the 4164fcf5ef2aSThomas Huth SPARCv8 manual, nop 4165fcf5ef2aSThomas Huth on the microSPARC 4166fcf5ef2aSThomas Huth II */ 4167fcf5ef2aSThomas Huth case 0x10 ... 0x1f: /* implementation-dependent 4168fcf5ef2aSThomas Huth in the SPARCv8 4169fcf5ef2aSThomas Huth manual, nop on the 4170fcf5ef2aSThomas Huth microSPARC II */ 4171fcf5ef2aSThomas Huth if ((rd == 0x13) && (dc->def->features & 4172fcf5ef2aSThomas Huth CPU_FEATURE_POWERDOWN)) { 4173fcf5ef2aSThomas Huth /* LEON3 power-down */ 4174fcf5ef2aSThomas Huth save_state(dc); 4175ad75a51eSRichard Henderson gen_helper_power_down(tcg_env); 4176fcf5ef2aSThomas Huth } 4177fcf5ef2aSThomas Huth break; 4178fcf5ef2aSThomas Huth #else 4179fcf5ef2aSThomas Huth case 0x2: /* V9 wrccr */ 4180fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4181ad75a51eSRichard Henderson gen_helper_wrccr(tcg_env, cpu_tmp0); 4182fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); 4183fcf5ef2aSThomas Huth dc->cc_op = CC_OP_FLAGS; 4184fcf5ef2aSThomas Huth break; 4185fcf5ef2aSThomas Huth case 0x3: /* V9 wrasi */ 4186fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4187fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); 4188ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4189fcf5ef2aSThomas Huth offsetof(CPUSPARCState, asi)); 419044a7c2ecSRichard Henderson /* 419144a7c2ecSRichard Henderson * End TB to notice changed ASI. 419244a7c2ecSRichard Henderson * TODO: Could notice src1 = %g0 and IS_IMM, 419344a7c2ecSRichard Henderson * update DisasContext and not exit the TB. 419444a7c2ecSRichard Henderson */ 4195fcf5ef2aSThomas Huth save_state(dc); 4196fcf5ef2aSThomas Huth gen_op_next_insn(); 419744a7c2ecSRichard Henderson tcg_gen_lookup_and_goto_ptr(); 4198af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 4199fcf5ef2aSThomas Huth break; 4200fcf5ef2aSThomas Huth case 0x6: /* V9 wrfprs */ 4201fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4202fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); 4203fcf5ef2aSThomas Huth dc->fprs_dirty = 0; 4204fcf5ef2aSThomas Huth save_state(dc); 4205fcf5ef2aSThomas Huth gen_op_next_insn(); 420607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 4207af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 4208fcf5ef2aSThomas Huth break; 4209fcf5ef2aSThomas Huth case 0xf: /* V9 sir, nop if user */ 4210fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4211fcf5ef2aSThomas Huth if (supervisor(dc)) { 4212fcf5ef2aSThomas Huth ; // XXX 4213fcf5ef2aSThomas Huth } 4214fcf5ef2aSThomas Huth #endif 4215fcf5ef2aSThomas Huth break; 4216fcf5ef2aSThomas Huth case 0x13: /* Graphics Status */ 4217fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 4218fcf5ef2aSThomas Huth goto jmp_insn; 4219fcf5ef2aSThomas Huth } 4220fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); 4221fcf5ef2aSThomas Huth break; 4222fcf5ef2aSThomas Huth case 0x14: /* Softint set */ 4223fcf5ef2aSThomas Huth if (!supervisor(dc)) 4224fcf5ef2aSThomas Huth goto illegal_insn; 4225fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4226ad75a51eSRichard Henderson gen_helper_set_softint(tcg_env, cpu_tmp0); 4227fcf5ef2aSThomas Huth break; 4228fcf5ef2aSThomas Huth case 0x15: /* Softint clear */ 4229fcf5ef2aSThomas Huth if (!supervisor(dc)) 4230fcf5ef2aSThomas Huth goto illegal_insn; 4231fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4232ad75a51eSRichard Henderson gen_helper_clear_softint(tcg_env, cpu_tmp0); 4233fcf5ef2aSThomas Huth break; 4234fcf5ef2aSThomas Huth case 0x16: /* Softint write */ 4235fcf5ef2aSThomas Huth if (!supervisor(dc)) 4236fcf5ef2aSThomas Huth goto illegal_insn; 4237fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4238ad75a51eSRichard Henderson gen_helper_write_softint(tcg_env, cpu_tmp0); 4239fcf5ef2aSThomas Huth break; 4240fcf5ef2aSThomas Huth case 0x17: /* Tick compare */ 4241fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4242fcf5ef2aSThomas Huth if (!supervisor(dc)) 4243fcf5ef2aSThomas Huth goto illegal_insn; 4244fcf5ef2aSThomas Huth #endif 4245fcf5ef2aSThomas Huth { 4246fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 4247fcf5ef2aSThomas Huth 4248fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, 4249fcf5ef2aSThomas Huth cpu_src2); 4250fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 4251ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 4252fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tick)); 4253dfd1b812SRichard Henderson translator_io_start(&dc->base); 4254fcf5ef2aSThomas Huth gen_helper_tick_set_limit(r_tickptr, 4255fcf5ef2aSThomas Huth cpu_tick_cmpr); 425646bb0137SMark Cave-Ayland /* End TB to handle timer interrupt */ 425746bb0137SMark Cave-Ayland dc->base.is_jmp = DISAS_EXIT; 4258fcf5ef2aSThomas Huth } 4259fcf5ef2aSThomas Huth break; 4260fcf5ef2aSThomas Huth case 0x18: /* System tick */ 4261fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4262fcf5ef2aSThomas Huth if (!supervisor(dc)) 4263fcf5ef2aSThomas Huth goto illegal_insn; 4264fcf5ef2aSThomas Huth #endif 4265fcf5ef2aSThomas Huth { 4266fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 4267fcf5ef2aSThomas Huth 4268fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, 4269fcf5ef2aSThomas Huth cpu_src2); 4270fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 4271ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 4272fcf5ef2aSThomas Huth offsetof(CPUSPARCState, stick)); 4273dfd1b812SRichard Henderson translator_io_start(&dc->base); 4274fcf5ef2aSThomas Huth gen_helper_tick_set_count(r_tickptr, 4275fcf5ef2aSThomas Huth cpu_tmp0); 427646bb0137SMark Cave-Ayland /* End TB to handle timer interrupt */ 427746bb0137SMark Cave-Ayland dc->base.is_jmp = DISAS_EXIT; 4278fcf5ef2aSThomas Huth } 4279fcf5ef2aSThomas Huth break; 4280fcf5ef2aSThomas Huth case 0x19: /* System tick compare */ 4281fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4282fcf5ef2aSThomas Huth if (!supervisor(dc)) 4283fcf5ef2aSThomas Huth goto illegal_insn; 4284fcf5ef2aSThomas Huth #endif 4285fcf5ef2aSThomas Huth { 4286fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 4287fcf5ef2aSThomas Huth 4288fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, 4289fcf5ef2aSThomas Huth cpu_src2); 4290fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 4291ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 4292fcf5ef2aSThomas Huth offsetof(CPUSPARCState, stick)); 4293dfd1b812SRichard Henderson translator_io_start(&dc->base); 4294fcf5ef2aSThomas Huth gen_helper_tick_set_limit(r_tickptr, 4295fcf5ef2aSThomas Huth cpu_stick_cmpr); 429646bb0137SMark Cave-Ayland /* End TB to handle timer interrupt */ 429746bb0137SMark Cave-Ayland dc->base.is_jmp = DISAS_EXIT; 4298fcf5ef2aSThomas Huth } 4299fcf5ef2aSThomas Huth break; 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth case 0x10: /* Performance Control */ 4302fcf5ef2aSThomas Huth case 0x11: /* Performance Instrumentation 4303fcf5ef2aSThomas Huth Counter */ 4304fcf5ef2aSThomas Huth case 0x12: /* Dispatch Control */ 4305fcf5ef2aSThomas Huth #endif 4306fcf5ef2aSThomas Huth default: 4307fcf5ef2aSThomas Huth goto illegal_insn; 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth } 4310fcf5ef2aSThomas Huth break; 4311fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4312fcf5ef2aSThomas Huth case 0x31: /* wrpsr, V9 saved, restored */ 4313fcf5ef2aSThomas Huth { 4314fcf5ef2aSThomas Huth if (!supervisor(dc)) 4315fcf5ef2aSThomas Huth goto priv_insn; 4316fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4317fcf5ef2aSThomas Huth switch (rd) { 4318fcf5ef2aSThomas Huth case 0: 4319ad75a51eSRichard Henderson gen_helper_saved(tcg_env); 4320fcf5ef2aSThomas Huth break; 4321fcf5ef2aSThomas Huth case 1: 4322ad75a51eSRichard Henderson gen_helper_restored(tcg_env); 4323fcf5ef2aSThomas Huth break; 4324fcf5ef2aSThomas Huth case 2: /* UA2005 allclean */ 4325fcf5ef2aSThomas Huth case 3: /* UA2005 otherw */ 4326fcf5ef2aSThomas Huth case 4: /* UA2005 normalw */ 4327fcf5ef2aSThomas Huth case 5: /* UA2005 invalw */ 4328fcf5ef2aSThomas Huth // XXX 4329fcf5ef2aSThomas Huth default: 4330fcf5ef2aSThomas Huth goto illegal_insn; 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth #else 433352123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4334fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4335ad75a51eSRichard Henderson gen_helper_wrpsr(tcg_env, cpu_tmp0); 4336fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); 4337fcf5ef2aSThomas Huth dc->cc_op = CC_OP_FLAGS; 4338fcf5ef2aSThomas Huth save_state(dc); 4339fcf5ef2aSThomas Huth gen_op_next_insn(); 434007ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 4341af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 4342fcf5ef2aSThomas Huth #endif 4343fcf5ef2aSThomas Huth } 4344fcf5ef2aSThomas Huth break; 4345fcf5ef2aSThomas Huth case 0x32: /* wrwim, V9 wrpr */ 4346fcf5ef2aSThomas Huth { 4347fcf5ef2aSThomas Huth if (!supervisor(dc)) 4348fcf5ef2aSThomas Huth goto priv_insn; 434952123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4350fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4351fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4352fcf5ef2aSThomas Huth switch (rd) { 4353fcf5ef2aSThomas Huth case 0: // tpc 4354fcf5ef2aSThomas Huth { 4355fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 4358ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 4359fcf5ef2aSThomas Huth tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4360fcf5ef2aSThomas Huth offsetof(trap_state, tpc)); 4361fcf5ef2aSThomas Huth } 4362fcf5ef2aSThomas Huth break; 4363fcf5ef2aSThomas Huth case 1: // tnpc 4364fcf5ef2aSThomas Huth { 4365fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 4366fcf5ef2aSThomas Huth 4367fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 4368ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 4369fcf5ef2aSThomas Huth tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4370fcf5ef2aSThomas Huth offsetof(trap_state, tnpc)); 4371fcf5ef2aSThomas Huth } 4372fcf5ef2aSThomas Huth break; 4373fcf5ef2aSThomas Huth case 2: // tstate 4374fcf5ef2aSThomas Huth { 4375fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 4376fcf5ef2aSThomas Huth 4377fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 4378ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 4379fcf5ef2aSThomas Huth tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4380fcf5ef2aSThomas Huth offsetof(trap_state, 4381fcf5ef2aSThomas Huth tstate)); 4382fcf5ef2aSThomas Huth } 4383fcf5ef2aSThomas Huth break; 4384fcf5ef2aSThomas Huth case 3: // tt 4385fcf5ef2aSThomas Huth { 4386fcf5ef2aSThomas Huth TCGv_ptr r_tsptr; 4387fcf5ef2aSThomas Huth 4388fcf5ef2aSThomas Huth r_tsptr = tcg_temp_new_ptr(); 4389ad75a51eSRichard Henderson gen_load_trap_state_at_tl(r_tsptr, tcg_env); 4390fcf5ef2aSThomas Huth tcg_gen_st32_tl(cpu_tmp0, r_tsptr, 4391fcf5ef2aSThomas Huth offsetof(trap_state, tt)); 4392fcf5ef2aSThomas Huth } 4393fcf5ef2aSThomas Huth break; 4394fcf5ef2aSThomas Huth case 4: // tick 4395fcf5ef2aSThomas Huth { 4396fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 4397fcf5ef2aSThomas Huth 4398fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 4399ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 4400fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tick)); 4401dfd1b812SRichard Henderson translator_io_start(&dc->base); 4402fcf5ef2aSThomas Huth gen_helper_tick_set_count(r_tickptr, 4403fcf5ef2aSThomas Huth cpu_tmp0); 440446bb0137SMark Cave-Ayland /* End TB to handle timer interrupt */ 440546bb0137SMark Cave-Ayland dc->base.is_jmp = DISAS_EXIT; 4406fcf5ef2aSThomas Huth } 4407fcf5ef2aSThomas Huth break; 4408fcf5ef2aSThomas Huth case 5: // tba 4409fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); 4410fcf5ef2aSThomas Huth break; 4411fcf5ef2aSThomas Huth case 6: // pstate 4412fcf5ef2aSThomas Huth save_state(dc); 4413dfd1b812SRichard Henderson if (translator_io_start(&dc->base)) { 4414b5328172SPeter Maydell dc->base.is_jmp = DISAS_EXIT; 441546bb0137SMark Cave-Ayland } 4416ad75a51eSRichard Henderson gen_helper_wrpstate(tcg_env, cpu_tmp0); 4417fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 4418fcf5ef2aSThomas Huth break; 4419fcf5ef2aSThomas Huth case 7: // tl 4420fcf5ef2aSThomas Huth save_state(dc); 4421ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4422fcf5ef2aSThomas Huth offsetof(CPUSPARCState, tl)); 4423fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 4424fcf5ef2aSThomas Huth break; 4425fcf5ef2aSThomas Huth case 8: // pil 4426dfd1b812SRichard Henderson if (translator_io_start(&dc->base)) { 4427b5328172SPeter Maydell dc->base.is_jmp = DISAS_EXIT; 442846bb0137SMark Cave-Ayland } 4429ad75a51eSRichard Henderson gen_helper_wrpil(tcg_env, cpu_tmp0); 4430fcf5ef2aSThomas Huth break; 4431fcf5ef2aSThomas Huth case 9: // cwp 4432ad75a51eSRichard Henderson gen_helper_wrcwp(tcg_env, cpu_tmp0); 4433fcf5ef2aSThomas Huth break; 4434fcf5ef2aSThomas Huth case 10: // cansave 4435ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4436fcf5ef2aSThomas Huth offsetof(CPUSPARCState, 4437fcf5ef2aSThomas Huth cansave)); 4438fcf5ef2aSThomas Huth break; 4439fcf5ef2aSThomas Huth case 11: // canrestore 4440ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4441fcf5ef2aSThomas Huth offsetof(CPUSPARCState, 4442fcf5ef2aSThomas Huth canrestore)); 4443fcf5ef2aSThomas Huth break; 4444fcf5ef2aSThomas Huth case 12: // cleanwin 4445ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4446fcf5ef2aSThomas Huth offsetof(CPUSPARCState, 4447fcf5ef2aSThomas Huth cleanwin)); 4448fcf5ef2aSThomas Huth break; 4449fcf5ef2aSThomas Huth case 13: // otherwin 4450ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4451fcf5ef2aSThomas Huth offsetof(CPUSPARCState, 4452fcf5ef2aSThomas Huth otherwin)); 4453fcf5ef2aSThomas Huth break; 4454fcf5ef2aSThomas Huth case 14: // wstate 4455ad75a51eSRichard Henderson tcg_gen_st32_tl(cpu_tmp0, tcg_env, 4456fcf5ef2aSThomas Huth offsetof(CPUSPARCState, 4457fcf5ef2aSThomas Huth wstate)); 4458fcf5ef2aSThomas Huth break; 4459fcf5ef2aSThomas Huth case 16: // UA2005 gl 4460fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, GL); 4461ad75a51eSRichard Henderson gen_helper_wrgl(tcg_env, cpu_tmp0); 4462fcf5ef2aSThomas Huth break; 4463fcf5ef2aSThomas Huth case 26: // UA2005 strand status 4464fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, HYPV); 4465fcf5ef2aSThomas Huth if (!hypervisor(dc)) 4466fcf5ef2aSThomas Huth goto priv_insn; 4467fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); 4468fcf5ef2aSThomas Huth break; 4469fcf5ef2aSThomas Huth default: 4470fcf5ef2aSThomas Huth goto illegal_insn; 4471fcf5ef2aSThomas Huth } 4472fcf5ef2aSThomas Huth #else 4473fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0); 4474fcf5ef2aSThomas Huth if (dc->def->nwindows != 32) { 4475fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_wim, cpu_wim, 4476fcf5ef2aSThomas Huth (1 << dc->def->nwindows) - 1); 4477fcf5ef2aSThomas Huth } 4478fcf5ef2aSThomas Huth #endif 4479fcf5ef2aSThomas Huth } 4480fcf5ef2aSThomas Huth break; 4481fcf5ef2aSThomas Huth case 0x33: /* wrtbr, UA2005 wrhpr */ 4482fcf5ef2aSThomas Huth { 4483fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 4484fcf5ef2aSThomas Huth if (!supervisor(dc)) 4485fcf5ef2aSThomas Huth goto priv_insn; 4486fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); 4487fcf5ef2aSThomas Huth #else 4488fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, HYPV); 4489fcf5ef2aSThomas Huth if (!hypervisor(dc)) 4490fcf5ef2aSThomas Huth goto priv_insn; 449152123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 4492fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4493fcf5ef2aSThomas Huth switch (rd) { 4494fcf5ef2aSThomas Huth case 0: // hpstate 4495ad75a51eSRichard Henderson tcg_gen_st_i64(cpu_tmp0, tcg_env, 4496f7f17ef7SArtyom Tarasenko offsetof(CPUSPARCState, 4497f7f17ef7SArtyom Tarasenko hpstate)); 4498fcf5ef2aSThomas Huth save_state(dc); 4499fcf5ef2aSThomas Huth gen_op_next_insn(); 450007ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 4501af00be49SEmilio G. Cota dc->base.is_jmp = DISAS_NORETURN; 4502fcf5ef2aSThomas Huth break; 4503fcf5ef2aSThomas Huth case 1: // htstate 4504fcf5ef2aSThomas Huth // XXX gen_op_wrhtstate(); 4505fcf5ef2aSThomas Huth break; 4506fcf5ef2aSThomas Huth case 3: // hintp 4507fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); 4508fcf5ef2aSThomas Huth break; 4509fcf5ef2aSThomas Huth case 5: // htba 4510fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_htba, cpu_tmp0); 4511fcf5ef2aSThomas Huth break; 4512fcf5ef2aSThomas Huth case 31: // hstick_cmpr 4513fcf5ef2aSThomas Huth { 4514fcf5ef2aSThomas Huth TCGv_ptr r_tickptr; 4515fcf5ef2aSThomas Huth 4516fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); 4517fcf5ef2aSThomas Huth r_tickptr = tcg_temp_new_ptr(); 4518ad75a51eSRichard Henderson tcg_gen_ld_ptr(r_tickptr, tcg_env, 4519fcf5ef2aSThomas Huth offsetof(CPUSPARCState, hstick)); 4520dfd1b812SRichard Henderson translator_io_start(&dc->base); 4521fcf5ef2aSThomas Huth gen_helper_tick_set_limit(r_tickptr, 4522fcf5ef2aSThomas Huth cpu_hstick_cmpr); 452346bb0137SMark Cave-Ayland /* End TB to handle timer interrupt */ 452446bb0137SMark Cave-Ayland dc->base.is_jmp = DISAS_EXIT; 4525fcf5ef2aSThomas Huth } 4526fcf5ef2aSThomas Huth break; 4527fcf5ef2aSThomas Huth case 6: // hver readonly 4528fcf5ef2aSThomas Huth default: 4529fcf5ef2aSThomas Huth goto illegal_insn; 4530fcf5ef2aSThomas Huth } 4531fcf5ef2aSThomas Huth #endif 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth break; 4534fcf5ef2aSThomas Huth #endif 4535fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4536fcf5ef2aSThomas Huth case 0x2c: /* V9 movcc */ 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth int cc = GET_FIELD_SP(insn, 11, 12); 4539fcf5ef2aSThomas Huth int cond = GET_FIELD_SP(insn, 14, 17); 4540fcf5ef2aSThomas Huth DisasCompare cmp; 4541fcf5ef2aSThomas Huth TCGv dst; 4542fcf5ef2aSThomas Huth 4543fcf5ef2aSThomas Huth if (insn & (1 << 18)) { 4544fcf5ef2aSThomas Huth if (cc == 0) { 4545fcf5ef2aSThomas Huth gen_compare(&cmp, 0, cond, dc); 4546fcf5ef2aSThomas Huth } else if (cc == 2) { 4547fcf5ef2aSThomas Huth gen_compare(&cmp, 1, cond, dc); 4548fcf5ef2aSThomas Huth } else { 4549fcf5ef2aSThomas Huth goto illegal_insn; 4550fcf5ef2aSThomas Huth } 4551fcf5ef2aSThomas Huth } else { 4552fcf5ef2aSThomas Huth gen_fcompare(&cmp, cc, cond); 4553fcf5ef2aSThomas Huth } 4554fcf5ef2aSThomas Huth 4555fcf5ef2aSThomas Huth /* The get_src2 above loaded the normal 13-bit 4556fcf5ef2aSThomas Huth immediate field, not the 11-bit field we have 4557fcf5ef2aSThomas Huth in movcc. But it did handle the reg case. */ 4558fcf5ef2aSThomas Huth if (IS_IMM) { 4559fcf5ef2aSThomas Huth simm = GET_FIELD_SPs(insn, 0, 10); 4560fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_src2, simm); 4561fcf5ef2aSThomas Huth } 4562fcf5ef2aSThomas Huth 4563fcf5ef2aSThomas Huth dst = gen_load_gpr(dc, rd); 4564fcf5ef2aSThomas Huth tcg_gen_movcond_tl(cmp.cond, dst, 4565fcf5ef2aSThomas Huth cmp.c1, cmp.c2, 4566fcf5ef2aSThomas Huth cpu_src2, dst); 4567fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 4568fcf5ef2aSThomas Huth break; 4569fcf5ef2aSThomas Huth } 4570fcf5ef2aSThomas Huth case 0x2d: /* V9 sdivx */ 4571ad75a51eSRichard Henderson gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); 4572fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4573fcf5ef2aSThomas Huth break; 4574fcf5ef2aSThomas Huth case 0x2e: /* V9 popc */ 457508da3180SRichard Henderson tcg_gen_ctpop_tl(cpu_dst, cpu_src2); 4576fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4577fcf5ef2aSThomas Huth break; 4578fcf5ef2aSThomas Huth case 0x2f: /* V9 movr */ 4579fcf5ef2aSThomas Huth { 4580fcf5ef2aSThomas Huth int cond = GET_FIELD_SP(insn, 10, 12); 4581fcf5ef2aSThomas Huth DisasCompare cmp; 4582fcf5ef2aSThomas Huth TCGv dst; 4583fcf5ef2aSThomas Huth 4584fcf5ef2aSThomas Huth gen_compare_reg(&cmp, cond, cpu_src1); 4585fcf5ef2aSThomas Huth 4586fcf5ef2aSThomas Huth /* The get_src2 above loaded the normal 13-bit 4587fcf5ef2aSThomas Huth immediate field, not the 10-bit field we have 4588fcf5ef2aSThomas Huth in movr. But it did handle the reg case. */ 4589fcf5ef2aSThomas Huth if (IS_IMM) { 4590fcf5ef2aSThomas Huth simm = GET_FIELD_SPs(insn, 0, 9); 4591fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_src2, simm); 4592fcf5ef2aSThomas Huth } 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth dst = gen_load_gpr(dc, rd); 4595fcf5ef2aSThomas Huth tcg_gen_movcond_tl(cmp.cond, dst, 4596fcf5ef2aSThomas Huth cmp.c1, cmp.c2, 4597fcf5ef2aSThomas Huth cpu_src2, dst); 4598fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, dst); 4599fcf5ef2aSThomas Huth break; 4600fcf5ef2aSThomas Huth } 4601fcf5ef2aSThomas Huth #endif 4602fcf5ef2aSThomas Huth default: 4603fcf5ef2aSThomas Huth goto illegal_insn; 4604fcf5ef2aSThomas Huth } 4605fcf5ef2aSThomas Huth } 4606fcf5ef2aSThomas Huth } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ 4607fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 4608fcf5ef2aSThomas Huth int opf = GET_FIELD_SP(insn, 5, 13); 4609fcf5ef2aSThomas Huth rs1 = GET_FIELD(insn, 13, 17); 4610fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 4611fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 4612fcf5ef2aSThomas Huth goto jmp_insn; 4613fcf5ef2aSThomas Huth } 4614fcf5ef2aSThomas Huth 4615fcf5ef2aSThomas Huth switch (opf) { 4616fcf5ef2aSThomas Huth case 0x000: /* VIS I edge8cc */ 4617fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4618fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4619fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4620fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); 4621fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4622fcf5ef2aSThomas Huth break; 4623fcf5ef2aSThomas Huth case 0x001: /* VIS II edge8n */ 4624fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4625fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4626fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4627fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); 4628fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4629fcf5ef2aSThomas Huth break; 4630fcf5ef2aSThomas Huth case 0x002: /* VIS I edge8lcc */ 4631fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4632fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4633fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4634fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); 4635fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4636fcf5ef2aSThomas Huth break; 4637fcf5ef2aSThomas Huth case 0x003: /* VIS II edge8ln */ 4638fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4639fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4640fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4641fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); 4642fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4643fcf5ef2aSThomas Huth break; 4644fcf5ef2aSThomas Huth case 0x004: /* VIS I edge16cc */ 4645fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4646fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4647fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4648fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); 4649fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4650fcf5ef2aSThomas Huth break; 4651fcf5ef2aSThomas Huth case 0x005: /* VIS II edge16n */ 4652fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4653fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4654fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4655fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); 4656fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4657fcf5ef2aSThomas Huth break; 4658fcf5ef2aSThomas Huth case 0x006: /* VIS I edge16lcc */ 4659fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4660fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4661fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4662fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); 4663fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4664fcf5ef2aSThomas Huth break; 4665fcf5ef2aSThomas Huth case 0x007: /* VIS II edge16ln */ 4666fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4667fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4668fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4669fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); 4670fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4671fcf5ef2aSThomas Huth break; 4672fcf5ef2aSThomas Huth case 0x008: /* VIS I edge32cc */ 4673fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4674fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4675fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4676fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); 4677fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4678fcf5ef2aSThomas Huth break; 4679fcf5ef2aSThomas Huth case 0x009: /* VIS II edge32n */ 4680fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4681fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4682fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4683fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); 4684fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4685fcf5ef2aSThomas Huth break; 4686fcf5ef2aSThomas Huth case 0x00a: /* VIS I edge32lcc */ 4687fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4688fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4689fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4690fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); 4691fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4692fcf5ef2aSThomas Huth break; 4693fcf5ef2aSThomas Huth case 0x00b: /* VIS II edge32ln */ 4694fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4695fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4696fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4697fcf5ef2aSThomas Huth gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); 4698fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4699fcf5ef2aSThomas Huth break; 4700fcf5ef2aSThomas Huth case 0x010: /* VIS I array8 */ 4701fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4702fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4703fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4704fcf5ef2aSThomas Huth gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4705fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4706fcf5ef2aSThomas Huth break; 4707fcf5ef2aSThomas Huth case 0x012: /* VIS I array16 */ 4708fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4709fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4710fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4711fcf5ef2aSThomas Huth gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4712fcf5ef2aSThomas Huth tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); 4713fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4714fcf5ef2aSThomas Huth break; 4715fcf5ef2aSThomas Huth case 0x014: /* VIS I array32 */ 4716fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4717fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4718fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4719fcf5ef2aSThomas Huth gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4720fcf5ef2aSThomas Huth tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); 4721fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4722fcf5ef2aSThomas Huth break; 4723fcf5ef2aSThomas Huth case 0x018: /* VIS I alignaddr */ 4724fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4725fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4726fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4727fcf5ef2aSThomas Huth gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); 4728fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4729fcf5ef2aSThomas Huth break; 4730fcf5ef2aSThomas Huth case 0x01a: /* VIS I alignaddrl */ 4731fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4732fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4733fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4734fcf5ef2aSThomas Huth gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); 4735fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4736fcf5ef2aSThomas Huth break; 4737fcf5ef2aSThomas Huth case 0x019: /* VIS II bmask */ 4738fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4739fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rs1); 4740fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 4741fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); 4742fcf5ef2aSThomas Huth tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); 4743fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4744fcf5ef2aSThomas Huth break; 4745fcf5ef2aSThomas Huth case 0x020: /* VIS I fcmple16 */ 4746fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4747fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4748fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4749fcf5ef2aSThomas Huth gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); 4750fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4751fcf5ef2aSThomas Huth break; 4752fcf5ef2aSThomas Huth case 0x022: /* VIS I fcmpne16 */ 4753fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4754fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4755fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4756fcf5ef2aSThomas Huth gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); 4757fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4758fcf5ef2aSThomas Huth break; 4759fcf5ef2aSThomas Huth case 0x024: /* VIS I fcmple32 */ 4760fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4761fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4762fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4763fcf5ef2aSThomas Huth gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); 4764fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4765fcf5ef2aSThomas Huth break; 4766fcf5ef2aSThomas Huth case 0x026: /* VIS I fcmpne32 */ 4767fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4768fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4769fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4770fcf5ef2aSThomas Huth gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); 4771fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4772fcf5ef2aSThomas Huth break; 4773fcf5ef2aSThomas Huth case 0x028: /* VIS I fcmpgt16 */ 4774fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4775fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4776fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4777fcf5ef2aSThomas Huth gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); 4778fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4779fcf5ef2aSThomas Huth break; 4780fcf5ef2aSThomas Huth case 0x02a: /* VIS I fcmpeq16 */ 4781fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4782fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4783fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4784fcf5ef2aSThomas Huth gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); 4785fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4786fcf5ef2aSThomas Huth break; 4787fcf5ef2aSThomas Huth case 0x02c: /* VIS I fcmpgt32 */ 4788fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4789fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4790fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4791fcf5ef2aSThomas Huth gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); 4792fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4793fcf5ef2aSThomas Huth break; 4794fcf5ef2aSThomas Huth case 0x02e: /* VIS I fcmpeq32 */ 4795fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4796fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4797fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4798fcf5ef2aSThomas Huth gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); 4799fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_dst); 4800fcf5ef2aSThomas Huth break; 4801fcf5ef2aSThomas Huth case 0x031: /* VIS I fmul8x16 */ 4802fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4803fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); 4804fcf5ef2aSThomas Huth break; 4805fcf5ef2aSThomas Huth case 0x033: /* VIS I fmul8x16au */ 4806fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4807fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au); 4808fcf5ef2aSThomas Huth break; 4809fcf5ef2aSThomas Huth case 0x035: /* VIS I fmul8x16al */ 4810fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4811fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al); 4812fcf5ef2aSThomas Huth break; 4813fcf5ef2aSThomas Huth case 0x036: /* VIS I fmul8sux16 */ 4814fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4815fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16); 4816fcf5ef2aSThomas Huth break; 4817fcf5ef2aSThomas Huth case 0x037: /* VIS I fmul8ulx16 */ 4818fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4819fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16); 4820fcf5ef2aSThomas Huth break; 4821fcf5ef2aSThomas Huth case 0x038: /* VIS I fmuld8sux16 */ 4822fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4823fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); 4824fcf5ef2aSThomas Huth break; 4825fcf5ef2aSThomas Huth case 0x039: /* VIS I fmuld8ulx16 */ 4826fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4827fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); 4828fcf5ef2aSThomas Huth break; 4829fcf5ef2aSThomas Huth case 0x03a: /* VIS I fpack32 */ 4830fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4831fcf5ef2aSThomas Huth gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); 4832fcf5ef2aSThomas Huth break; 4833fcf5ef2aSThomas Huth case 0x03b: /* VIS I fpack16 */ 4834fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4835fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs2); 4836fcf5ef2aSThomas Huth cpu_dst_32 = gen_dest_fpr_F(dc); 4837fcf5ef2aSThomas Huth gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); 4838fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_dst_32); 4839fcf5ef2aSThomas Huth break; 4840fcf5ef2aSThomas Huth case 0x03d: /* VIS I fpackfix */ 4841fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4842fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs2); 4843fcf5ef2aSThomas Huth cpu_dst_32 = gen_dest_fpr_F(dc); 4844fcf5ef2aSThomas Huth gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); 4845fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_dst_32); 4846fcf5ef2aSThomas Huth break; 4847fcf5ef2aSThomas Huth case 0x03e: /* VIS I pdist */ 4848fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4849fcf5ef2aSThomas Huth gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); 4850fcf5ef2aSThomas Huth break; 4851fcf5ef2aSThomas Huth case 0x048: /* VIS I faligndata */ 4852fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4853fcf5ef2aSThomas Huth gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); 4854fcf5ef2aSThomas Huth break; 4855fcf5ef2aSThomas Huth case 0x04b: /* VIS I fpmerge */ 4856fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4857fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); 4858fcf5ef2aSThomas Huth break; 4859fcf5ef2aSThomas Huth case 0x04c: /* VIS II bshuffle */ 4860fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS2); 4861fcf5ef2aSThomas Huth gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); 4862fcf5ef2aSThomas Huth break; 4863fcf5ef2aSThomas Huth case 0x04d: /* VIS I fexpand */ 4864fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4865fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); 4866fcf5ef2aSThomas Huth break; 4867fcf5ef2aSThomas Huth case 0x050: /* VIS I fpadd16 */ 4868fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4869fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16); 4870fcf5ef2aSThomas Huth break; 4871fcf5ef2aSThomas Huth case 0x051: /* VIS I fpadd16s */ 4872fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4873fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s); 4874fcf5ef2aSThomas Huth break; 4875fcf5ef2aSThomas Huth case 0x052: /* VIS I fpadd32 */ 4876fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4877fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32); 4878fcf5ef2aSThomas Huth break; 4879fcf5ef2aSThomas Huth case 0x053: /* VIS I fpadd32s */ 4880fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4881fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32); 4882fcf5ef2aSThomas Huth break; 4883fcf5ef2aSThomas Huth case 0x054: /* VIS I fpsub16 */ 4884fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4885fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16); 4886fcf5ef2aSThomas Huth break; 4887fcf5ef2aSThomas Huth case 0x055: /* VIS I fpsub16s */ 4888fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4889fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s); 4890fcf5ef2aSThomas Huth break; 4891fcf5ef2aSThomas Huth case 0x056: /* VIS I fpsub32 */ 4892fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4893fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32); 4894fcf5ef2aSThomas Huth break; 4895fcf5ef2aSThomas Huth case 0x057: /* VIS I fpsub32s */ 4896fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4897fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32); 4898fcf5ef2aSThomas Huth break; 4899fcf5ef2aSThomas Huth case 0x060: /* VIS I fzero */ 4900fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4901fcf5ef2aSThomas Huth cpu_dst_64 = gen_dest_fpr_D(dc, rd); 4902fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_dst_64, 0); 4903fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_dst_64); 4904fcf5ef2aSThomas Huth break; 4905fcf5ef2aSThomas Huth case 0x061: /* VIS I fzeros */ 4906fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4907fcf5ef2aSThomas Huth cpu_dst_32 = gen_dest_fpr_F(dc); 4908fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_dst_32, 0); 4909fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_dst_32); 4910fcf5ef2aSThomas Huth break; 4911fcf5ef2aSThomas Huth case 0x062: /* VIS I fnor */ 4912fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4913fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); 4914fcf5ef2aSThomas Huth break; 4915fcf5ef2aSThomas Huth case 0x063: /* VIS I fnors */ 4916fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4917fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32); 4918fcf5ef2aSThomas Huth break; 4919fcf5ef2aSThomas Huth case 0x064: /* VIS I fandnot2 */ 4920fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4921fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); 4922fcf5ef2aSThomas Huth break; 4923fcf5ef2aSThomas Huth case 0x065: /* VIS I fandnot2s */ 4924fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4925fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); 4926fcf5ef2aSThomas Huth break; 4927fcf5ef2aSThomas Huth case 0x066: /* VIS I fnot2 */ 4928fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4929fcf5ef2aSThomas Huth gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); 4930fcf5ef2aSThomas Huth break; 4931fcf5ef2aSThomas Huth case 0x067: /* VIS I fnot2s */ 4932fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4933fcf5ef2aSThomas Huth gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32); 4934fcf5ef2aSThomas Huth break; 4935fcf5ef2aSThomas Huth case 0x068: /* VIS I fandnot1 */ 4936fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4937fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); 4938fcf5ef2aSThomas Huth break; 4939fcf5ef2aSThomas Huth case 0x069: /* VIS I fandnot1s */ 4940fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4941fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); 4942fcf5ef2aSThomas Huth break; 4943fcf5ef2aSThomas Huth case 0x06a: /* VIS I fnot1 */ 4944fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4945fcf5ef2aSThomas Huth gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); 4946fcf5ef2aSThomas Huth break; 4947fcf5ef2aSThomas Huth case 0x06b: /* VIS I fnot1s */ 4948fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4949fcf5ef2aSThomas Huth gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32); 4950fcf5ef2aSThomas Huth break; 4951fcf5ef2aSThomas Huth case 0x06c: /* VIS I fxor */ 4952fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4953fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); 4954fcf5ef2aSThomas Huth break; 4955fcf5ef2aSThomas Huth case 0x06d: /* VIS I fxors */ 4956fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4957fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32); 4958fcf5ef2aSThomas Huth break; 4959fcf5ef2aSThomas Huth case 0x06e: /* VIS I fnand */ 4960fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4961fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); 4962fcf5ef2aSThomas Huth break; 4963fcf5ef2aSThomas Huth case 0x06f: /* VIS I fnands */ 4964fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4965fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32); 4966fcf5ef2aSThomas Huth break; 4967fcf5ef2aSThomas Huth case 0x070: /* VIS I fand */ 4968fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4969fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); 4970fcf5ef2aSThomas Huth break; 4971fcf5ef2aSThomas Huth case 0x071: /* VIS I fands */ 4972fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4973fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32); 4974fcf5ef2aSThomas Huth break; 4975fcf5ef2aSThomas Huth case 0x072: /* VIS I fxnor */ 4976fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4977fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); 4978fcf5ef2aSThomas Huth break; 4979fcf5ef2aSThomas Huth case 0x073: /* VIS I fxnors */ 4980fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4981fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); 4982fcf5ef2aSThomas Huth break; 4983fcf5ef2aSThomas Huth case 0x074: /* VIS I fsrc1 */ 4984fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4985fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4986fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_src1_64); 4987fcf5ef2aSThomas Huth break; 4988fcf5ef2aSThomas Huth case 0x075: /* VIS I fsrc1s */ 4989fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4990fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rs1); 4991fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_src1_32); 4992fcf5ef2aSThomas Huth break; 4993fcf5ef2aSThomas Huth case 0x076: /* VIS I fornot2 */ 4994fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4995fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); 4996fcf5ef2aSThomas Huth break; 4997fcf5ef2aSThomas Huth case 0x077: /* VIS I fornot2s */ 4998fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 4999fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); 5000fcf5ef2aSThomas Huth break; 5001fcf5ef2aSThomas Huth case 0x078: /* VIS I fsrc2 */ 5002fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5003fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rs2); 5004fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_src1_64); 5005fcf5ef2aSThomas Huth break; 5006fcf5ef2aSThomas Huth case 0x079: /* VIS I fsrc2s */ 5007fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5008fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rs2); 5009fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_src1_32); 5010fcf5ef2aSThomas Huth break; 5011fcf5ef2aSThomas Huth case 0x07a: /* VIS I fornot1 */ 5012fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5013fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); 5014fcf5ef2aSThomas Huth break; 5015fcf5ef2aSThomas Huth case 0x07b: /* VIS I fornot1s */ 5016fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5017fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32); 5018fcf5ef2aSThomas Huth break; 5019fcf5ef2aSThomas Huth case 0x07c: /* VIS I for */ 5020fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5021fcf5ef2aSThomas Huth gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); 5022fcf5ef2aSThomas Huth break; 5023fcf5ef2aSThomas Huth case 0x07d: /* VIS I fors */ 5024fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5025fcf5ef2aSThomas Huth gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32); 5026fcf5ef2aSThomas Huth break; 5027fcf5ef2aSThomas Huth case 0x07e: /* VIS I fone */ 5028fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5029fcf5ef2aSThomas Huth cpu_dst_64 = gen_dest_fpr_D(dc, rd); 5030fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_dst_64, -1); 5031fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_dst_64); 5032fcf5ef2aSThomas Huth break; 5033fcf5ef2aSThomas Huth case 0x07f: /* VIS I fones */ 5034fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, VIS1); 5035fcf5ef2aSThomas Huth cpu_dst_32 = gen_dest_fpr_F(dc); 5036fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_dst_32, -1); 5037fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_dst_32); 5038fcf5ef2aSThomas Huth break; 5039fcf5ef2aSThomas Huth case 0x080: /* VIS I shutdown */ 5040fcf5ef2aSThomas Huth case 0x081: /* VIS II siam */ 5041fcf5ef2aSThomas Huth // XXX 5042fcf5ef2aSThomas Huth goto illegal_insn; 5043fcf5ef2aSThomas Huth default: 5044fcf5ef2aSThomas Huth goto illegal_insn; 5045fcf5ef2aSThomas Huth } 5046fcf5ef2aSThomas Huth #else 5047fcf5ef2aSThomas Huth goto ncp_insn; 5048fcf5ef2aSThomas Huth #endif 5049fcf5ef2aSThomas Huth } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ 5050fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5051fcf5ef2aSThomas Huth goto illegal_insn; 5052fcf5ef2aSThomas Huth #else 5053fcf5ef2aSThomas Huth goto ncp_insn; 5054fcf5ef2aSThomas Huth #endif 5055fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5056fcf5ef2aSThomas Huth } else if (xop == 0x39) { /* V9 return */ 5057fcf5ef2aSThomas Huth save_state(dc); 5058fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 505952123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 5060fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 5061fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 19, 31); 5062fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); 5063fcf5ef2aSThomas Huth } else { /* register */ 5064fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 5065fcf5ef2aSThomas Huth if (rs2) { 5066fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 5067fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); 5068fcf5ef2aSThomas Huth } else { 5069fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tmp0, cpu_src1); 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth } 5072186e7890SRichard Henderson gen_check_align(dc, cpu_tmp0, 3); 5073ad75a51eSRichard Henderson gen_helper_restore(tcg_env); 5074fcf5ef2aSThomas Huth gen_mov_pc_npc(dc); 5075fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5076553338dcSRichard Henderson dc->npc = DYNAMIC_PC_LOOKUP; 5077fcf5ef2aSThomas Huth goto jmp_insn; 5078fcf5ef2aSThomas Huth #endif 5079fcf5ef2aSThomas Huth } else { 5080fcf5ef2aSThomas Huth cpu_src1 = get_src1(dc, insn); 508152123f14SRichard Henderson cpu_tmp0 = tcg_temp_new(); 5082fcf5ef2aSThomas Huth if (IS_IMM) { /* immediate */ 5083fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 19, 31); 5084fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); 5085fcf5ef2aSThomas Huth } else { /* register */ 5086fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 5087fcf5ef2aSThomas Huth if (rs2) { 5088fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 5089fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); 5090fcf5ef2aSThomas Huth } else { 5091fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_tmp0, cpu_src1); 5092fcf5ef2aSThomas Huth } 5093fcf5ef2aSThomas Huth } 5094fcf5ef2aSThomas Huth switch (xop) { 5095fcf5ef2aSThomas Huth case 0x38: /* jmpl */ 5096fcf5ef2aSThomas Huth { 5097186e7890SRichard Henderson gen_check_align(dc, cpu_tmp0, 3); 5098186e7890SRichard Henderson gen_store_gpr(dc, rd, tcg_constant_tl(dc->pc)); 5099fcf5ef2aSThomas Huth gen_mov_pc_npc(dc); 5100fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_tmp0); 5101fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5102831543fcSRichard Henderson dc->npc = DYNAMIC_PC_LOOKUP; 5103fcf5ef2aSThomas Huth } 5104fcf5ef2aSThomas Huth goto jmp_insn; 5105fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) 5106fcf5ef2aSThomas Huth case 0x39: /* rett, V9 return */ 5107fcf5ef2aSThomas Huth { 5108fcf5ef2aSThomas Huth if (!supervisor(dc)) 5109fcf5ef2aSThomas Huth goto priv_insn; 5110186e7890SRichard Henderson gen_check_align(dc, cpu_tmp0, 3); 5111fcf5ef2aSThomas Huth gen_mov_pc_npc(dc); 5112fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5113fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 5114ad75a51eSRichard Henderson gen_helper_rett(tcg_env); 5115fcf5ef2aSThomas Huth } 5116fcf5ef2aSThomas Huth goto jmp_insn; 5117fcf5ef2aSThomas Huth #endif 5118fcf5ef2aSThomas Huth case 0x3b: /* flush */ 5119fcf5ef2aSThomas Huth /* nop */ 5120fcf5ef2aSThomas Huth break; 5121fcf5ef2aSThomas Huth case 0x3c: /* save */ 5122ad75a51eSRichard Henderson gen_helper_save(tcg_env); 5123fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_tmp0); 5124fcf5ef2aSThomas Huth break; 5125fcf5ef2aSThomas Huth case 0x3d: /* restore */ 5126ad75a51eSRichard Henderson gen_helper_restore(tcg_env); 5127fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_tmp0); 5128fcf5ef2aSThomas Huth break; 5129fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) 5130fcf5ef2aSThomas Huth case 0x3e: /* V9 done/retry */ 5131fcf5ef2aSThomas Huth { 5132fcf5ef2aSThomas Huth switch (rd) { 5133fcf5ef2aSThomas Huth case 0: 5134fcf5ef2aSThomas Huth if (!supervisor(dc)) 5135fcf5ef2aSThomas Huth goto priv_insn; 5136fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 5137fcf5ef2aSThomas Huth dc->pc = DYNAMIC_PC; 5138dfd1b812SRichard Henderson translator_io_start(&dc->base); 5139ad75a51eSRichard Henderson gen_helper_done(tcg_env); 5140fcf5ef2aSThomas Huth goto jmp_insn; 5141fcf5ef2aSThomas Huth case 1: 5142fcf5ef2aSThomas Huth if (!supervisor(dc)) 5143fcf5ef2aSThomas Huth goto priv_insn; 5144fcf5ef2aSThomas Huth dc->npc = DYNAMIC_PC; 5145fcf5ef2aSThomas Huth dc->pc = DYNAMIC_PC; 5146dfd1b812SRichard Henderson translator_io_start(&dc->base); 5147ad75a51eSRichard Henderson gen_helper_retry(tcg_env); 5148fcf5ef2aSThomas Huth goto jmp_insn; 5149fcf5ef2aSThomas Huth default: 5150fcf5ef2aSThomas Huth goto illegal_insn; 5151fcf5ef2aSThomas Huth } 5152fcf5ef2aSThomas Huth } 5153fcf5ef2aSThomas Huth break; 5154fcf5ef2aSThomas Huth #endif 5155fcf5ef2aSThomas Huth default: 5156fcf5ef2aSThomas Huth goto illegal_insn; 5157fcf5ef2aSThomas Huth } 5158fcf5ef2aSThomas Huth } 5159fcf5ef2aSThomas Huth break; 5160fcf5ef2aSThomas Huth } 5161fcf5ef2aSThomas Huth break; 5162fcf5ef2aSThomas Huth case 3: /* load/store instructions */ 5163fcf5ef2aSThomas Huth { 5164fcf5ef2aSThomas Huth unsigned int xop = GET_FIELD(insn, 7, 12); 5165fcf5ef2aSThomas Huth /* ??? gen_address_mask prevents us from using a source 5166fcf5ef2aSThomas Huth register directly. Always generate a temporary. */ 516752123f14SRichard Henderson TCGv cpu_addr = tcg_temp_new(); 5168fcf5ef2aSThomas Huth 5169fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); 5170fcf5ef2aSThomas Huth if (xop == 0x3c || xop == 0x3e) { 5171fcf5ef2aSThomas Huth /* V9 casa/casxa : no offset */ 5172fcf5ef2aSThomas Huth } else if (IS_IMM) { /* immediate */ 5173fcf5ef2aSThomas Huth simm = GET_FIELDs(insn, 19, 31); 5174fcf5ef2aSThomas Huth if (simm != 0) { 5175fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); 5176fcf5ef2aSThomas Huth } 5177fcf5ef2aSThomas Huth } else { /* register */ 5178fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 5179fcf5ef2aSThomas Huth if (rs2 != 0) { 5180fcf5ef2aSThomas Huth tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2)); 5181fcf5ef2aSThomas Huth } 5182fcf5ef2aSThomas Huth } 5183fcf5ef2aSThomas Huth if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || 5184fcf5ef2aSThomas Huth (xop > 0x17 && xop <= 0x1d ) || 5185fcf5ef2aSThomas Huth (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { 5186fcf5ef2aSThomas Huth TCGv cpu_val = gen_dest_gpr(dc, rd); 5187fcf5ef2aSThomas Huth 5188fcf5ef2aSThomas Huth switch (xop) { 5189fcf5ef2aSThomas Huth case 0x0: /* ld, V9 lduw, load unsigned word */ 5190fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 519108149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 5192316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5193fcf5ef2aSThomas Huth break; 5194fcf5ef2aSThomas Huth case 0x1: /* ldub, load unsigned byte */ 5195fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 519608149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 519708149118SRichard Henderson dc->mem_idx, MO_UB); 5198fcf5ef2aSThomas Huth break; 5199fcf5ef2aSThomas Huth case 0x2: /* lduh, load unsigned halfword */ 5200fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 520108149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 5202316b6783SRichard Henderson dc->mem_idx, MO_TEUW | MO_ALIGN); 5203fcf5ef2aSThomas Huth break; 5204fcf5ef2aSThomas Huth case 0x3: /* ldd, load double word */ 5205fcf5ef2aSThomas Huth if (rd & 1) 5206fcf5ef2aSThomas Huth goto illegal_insn; 5207fcf5ef2aSThomas Huth else { 5208fcf5ef2aSThomas Huth TCGv_i64 t64; 5209fcf5ef2aSThomas Huth 5210fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5211fcf5ef2aSThomas Huth t64 = tcg_temp_new_i64(); 521208149118SRichard Henderson tcg_gen_qemu_ld_i64(t64, cpu_addr, 5213316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5214fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_val, t64); 5215fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_val, cpu_val); 5216fcf5ef2aSThomas Huth gen_store_gpr(dc, rd + 1, cpu_val); 5217fcf5ef2aSThomas Huth tcg_gen_shri_i64(t64, t64, 32); 5218fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_val, t64); 5219fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_val, cpu_val); 5220fcf5ef2aSThomas Huth } 5221fcf5ef2aSThomas Huth break; 5222fcf5ef2aSThomas Huth case 0x9: /* ldsb, load signed byte */ 5223fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 522408149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB); 5225fcf5ef2aSThomas Huth break; 5226fcf5ef2aSThomas Huth case 0xa: /* ldsh, load signed halfword */ 5227fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 522808149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 5229316b6783SRichard Henderson dc->mem_idx, MO_TESW | MO_ALIGN); 5230fcf5ef2aSThomas Huth break; 5231fcf5ef2aSThomas Huth case 0xd: /* ldstub */ 5232fcf5ef2aSThomas Huth gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); 5233fcf5ef2aSThomas Huth break; 5234fcf5ef2aSThomas Huth case 0x0f: 5235fcf5ef2aSThomas Huth /* swap, swap register with memory. Also atomically */ 5236fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rd); 5237fcf5ef2aSThomas Huth gen_swap(dc, cpu_val, cpu_src1, cpu_addr, 5238fcf5ef2aSThomas Huth dc->mem_idx, MO_TEUL); 5239fcf5ef2aSThomas Huth break; 5240fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5241fcf5ef2aSThomas Huth case 0x10: /* lda, V9 lduwa, load word alternate */ 5242fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); 5243fcf5ef2aSThomas Huth break; 5244fcf5ef2aSThomas Huth case 0x11: /* lduba, load unsigned byte alternate */ 5245fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); 5246fcf5ef2aSThomas Huth break; 5247fcf5ef2aSThomas Huth case 0x12: /* lduha, load unsigned halfword alternate */ 5248fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); 5249fcf5ef2aSThomas Huth break; 5250fcf5ef2aSThomas Huth case 0x13: /* ldda, load double word alternate */ 5251fcf5ef2aSThomas Huth if (rd & 1) { 5252fcf5ef2aSThomas Huth goto illegal_insn; 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth gen_ldda_asi(dc, cpu_addr, insn, rd); 5255fcf5ef2aSThomas Huth goto skip_move; 5256fcf5ef2aSThomas Huth case 0x19: /* ldsba, load signed byte alternate */ 5257fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); 5258fcf5ef2aSThomas Huth break; 5259fcf5ef2aSThomas Huth case 0x1a: /* ldsha, load signed halfword alternate */ 5260fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); 5261fcf5ef2aSThomas Huth break; 5262fcf5ef2aSThomas Huth case 0x1d: /* ldstuba -- XXX: should be atomically */ 5263fcf5ef2aSThomas Huth gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); 5264fcf5ef2aSThomas Huth break; 5265fcf5ef2aSThomas Huth case 0x1f: /* swapa, swap reg with alt. memory. Also 5266fcf5ef2aSThomas Huth atomically */ 5267fcf5ef2aSThomas Huth cpu_src1 = gen_load_gpr(dc, rd); 5268fcf5ef2aSThomas Huth gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); 5269fcf5ef2aSThomas Huth break; 5270fcf5ef2aSThomas Huth 5271fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 5272fcf5ef2aSThomas Huth case 0x30: /* ldc */ 5273fcf5ef2aSThomas Huth case 0x31: /* ldcsr */ 5274fcf5ef2aSThomas Huth case 0x33: /* lddc */ 5275fcf5ef2aSThomas Huth goto ncp_insn; 5276fcf5ef2aSThomas Huth #endif 5277fcf5ef2aSThomas Huth #endif 5278fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5279fcf5ef2aSThomas Huth case 0x08: /* V9 ldsw */ 5280fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 528108149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 5282316b6783SRichard Henderson dc->mem_idx, MO_TESL | MO_ALIGN); 5283fcf5ef2aSThomas Huth break; 5284fcf5ef2aSThomas Huth case 0x0b: /* V9 ldx */ 5285fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 528608149118SRichard Henderson tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, 5287316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5288fcf5ef2aSThomas Huth break; 5289fcf5ef2aSThomas Huth case 0x18: /* V9 ldswa */ 5290fcf5ef2aSThomas Huth gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); 5291fcf5ef2aSThomas Huth break; 5292fcf5ef2aSThomas Huth case 0x1b: /* V9 ldxa */ 5293fc313c64SFrédéric Pétrot gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); 5294fcf5ef2aSThomas Huth break; 5295fcf5ef2aSThomas Huth case 0x2d: /* V9 prefetch, no effect */ 5296fcf5ef2aSThomas Huth goto skip_move; 5297fcf5ef2aSThomas Huth case 0x30: /* V9 ldfa */ 5298fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5299fcf5ef2aSThomas Huth goto jmp_insn; 5300fcf5ef2aSThomas Huth } 5301fcf5ef2aSThomas Huth gen_ldf_asi(dc, cpu_addr, insn, 4, rd); 5302fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, rd); 5303fcf5ef2aSThomas Huth goto skip_move; 5304fcf5ef2aSThomas Huth case 0x33: /* V9 lddfa */ 5305fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5306fcf5ef2aSThomas Huth goto jmp_insn; 5307fcf5ef2aSThomas Huth } 5308fcf5ef2aSThomas Huth gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); 5309fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, DFPREG(rd)); 5310fcf5ef2aSThomas Huth goto skip_move; 5311fcf5ef2aSThomas Huth case 0x3d: /* V9 prefetcha, no effect */ 5312fcf5ef2aSThomas Huth goto skip_move; 5313fcf5ef2aSThomas Huth case 0x32: /* V9 ldqfa */ 5314fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 5315fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5316fcf5ef2aSThomas Huth goto jmp_insn; 5317fcf5ef2aSThomas Huth } 5318fcf5ef2aSThomas Huth gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); 5319fcf5ef2aSThomas Huth gen_update_fprs_dirty(dc, QFPREG(rd)); 5320fcf5ef2aSThomas Huth goto skip_move; 5321fcf5ef2aSThomas Huth #endif 5322fcf5ef2aSThomas Huth default: 5323fcf5ef2aSThomas Huth goto illegal_insn; 5324fcf5ef2aSThomas Huth } 5325fcf5ef2aSThomas Huth gen_store_gpr(dc, rd, cpu_val); 5326fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5327fcf5ef2aSThomas Huth skip_move: ; 5328fcf5ef2aSThomas Huth #endif 5329fcf5ef2aSThomas Huth } else if (xop >= 0x20 && xop < 0x24) { 5330fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5331fcf5ef2aSThomas Huth goto jmp_insn; 5332fcf5ef2aSThomas Huth } 5333fcf5ef2aSThomas Huth switch (xop) { 5334fcf5ef2aSThomas Huth case 0x20: /* ldf, load fpreg */ 5335fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5336fcf5ef2aSThomas Huth cpu_dst_32 = gen_dest_fpr_F(dc); 5337fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, 5338316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5339fcf5ef2aSThomas Huth gen_store_fpr_F(dc, rd, cpu_dst_32); 5340fcf5ef2aSThomas Huth break; 5341fcf5ef2aSThomas Huth case 0x21: /* ldfsr, V9 ldxfsr */ 5342fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5343fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5344fcf5ef2aSThomas Huth if (rd == 1) { 5345fcf5ef2aSThomas Huth TCGv_i64 t64 = tcg_temp_new_i64(); 5346fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(t64, cpu_addr, 5347316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5348ad75a51eSRichard Henderson gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64); 5349fcf5ef2aSThomas Huth break; 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth #endif 535236ab4623SRichard Henderson cpu_dst_32 = tcg_temp_new_i32(); 5353fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, 5354316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5355ad75a51eSRichard Henderson gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32); 5356fcf5ef2aSThomas Huth break; 5357fcf5ef2aSThomas Huth case 0x22: /* ldqf, load quad fpreg */ 5358fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 5359fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5360fcf5ef2aSThomas Huth cpu_src1_64 = tcg_temp_new_i64(); 5361fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx, 5362fc313c64SFrédéric Pétrot MO_TEUQ | MO_ALIGN_4); 5363fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); 5364fcf5ef2aSThomas Huth cpu_src2_64 = tcg_temp_new_i64(); 5365fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx, 5366fc313c64SFrédéric Pétrot MO_TEUQ | MO_ALIGN_4); 5367fcf5ef2aSThomas Huth gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64); 5368fcf5ef2aSThomas Huth break; 5369fcf5ef2aSThomas Huth case 0x23: /* lddf, load double fpreg */ 5370fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5371fcf5ef2aSThomas Huth cpu_dst_64 = gen_dest_fpr_D(dc, rd); 5372fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx, 5373fc313c64SFrédéric Pétrot MO_TEUQ | MO_ALIGN_4); 5374fcf5ef2aSThomas Huth gen_store_fpr_D(dc, rd, cpu_dst_64); 5375fcf5ef2aSThomas Huth break; 5376fcf5ef2aSThomas Huth default: 5377fcf5ef2aSThomas Huth goto illegal_insn; 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || 5380fcf5ef2aSThomas Huth xop == 0xe || xop == 0x1e) { 5381fcf5ef2aSThomas Huth TCGv cpu_val = gen_load_gpr(dc, rd); 5382fcf5ef2aSThomas Huth 5383fcf5ef2aSThomas Huth switch (xop) { 5384fcf5ef2aSThomas Huth case 0x4: /* st, store word */ 5385fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 538608149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_val, cpu_addr, 5387316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5388fcf5ef2aSThomas Huth break; 5389fcf5ef2aSThomas Huth case 0x5: /* stb, store byte */ 5390fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 539108149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB); 5392fcf5ef2aSThomas Huth break; 5393fcf5ef2aSThomas Huth case 0x6: /* sth, store halfword */ 5394fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 539508149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_val, cpu_addr, 5396316b6783SRichard Henderson dc->mem_idx, MO_TEUW | MO_ALIGN); 5397fcf5ef2aSThomas Huth break; 5398fcf5ef2aSThomas Huth case 0x7: /* std, store double word */ 5399fcf5ef2aSThomas Huth if (rd & 1) 5400fcf5ef2aSThomas Huth goto illegal_insn; 5401fcf5ef2aSThomas Huth else { 5402fcf5ef2aSThomas Huth TCGv_i64 t64; 5403fcf5ef2aSThomas Huth TCGv lo; 5404fcf5ef2aSThomas Huth 5405fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5406fcf5ef2aSThomas Huth lo = gen_load_gpr(dc, rd + 1); 5407fcf5ef2aSThomas Huth t64 = tcg_temp_new_i64(); 5408fcf5ef2aSThomas Huth tcg_gen_concat_tl_i64(t64, lo, cpu_val); 540908149118SRichard Henderson tcg_gen_qemu_st_i64(t64, cpu_addr, 5410316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5411fcf5ef2aSThomas Huth } 5412fcf5ef2aSThomas Huth break; 5413fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5414fcf5ef2aSThomas Huth case 0x14: /* sta, V9 stwa, store word alternate */ 5415fcf5ef2aSThomas Huth gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); 5416fcf5ef2aSThomas Huth break; 5417fcf5ef2aSThomas Huth case 0x15: /* stba, store byte alternate */ 5418fcf5ef2aSThomas Huth gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); 5419fcf5ef2aSThomas Huth break; 5420fcf5ef2aSThomas Huth case 0x16: /* stha, store halfword alternate */ 5421fcf5ef2aSThomas Huth gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); 5422fcf5ef2aSThomas Huth break; 5423fcf5ef2aSThomas Huth case 0x17: /* stda, store double word alternate */ 5424fcf5ef2aSThomas Huth if (rd & 1) { 5425fcf5ef2aSThomas Huth goto illegal_insn; 5426fcf5ef2aSThomas Huth } 5427fcf5ef2aSThomas Huth gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); 5428fcf5ef2aSThomas Huth break; 5429fcf5ef2aSThomas Huth #endif 5430fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5431fcf5ef2aSThomas Huth case 0x0e: /* V9 stx */ 5432fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 543308149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_val, cpu_addr, 5434316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5435fcf5ef2aSThomas Huth break; 5436fcf5ef2aSThomas Huth case 0x1e: /* V9 stxa */ 5437fc313c64SFrédéric Pétrot gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); 5438fcf5ef2aSThomas Huth break; 5439fcf5ef2aSThomas Huth #endif 5440fcf5ef2aSThomas Huth default: 5441fcf5ef2aSThomas Huth goto illegal_insn; 5442fcf5ef2aSThomas Huth } 5443fcf5ef2aSThomas Huth } else if (xop > 0x23 && xop < 0x28) { 5444fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5445fcf5ef2aSThomas Huth goto jmp_insn; 5446fcf5ef2aSThomas Huth } 5447fcf5ef2aSThomas Huth switch (xop) { 5448fcf5ef2aSThomas Huth case 0x24: /* stf, store fpreg */ 5449fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5450fcf5ef2aSThomas Huth cpu_src1_32 = gen_load_fpr_F(dc, rd); 5451fcf5ef2aSThomas Huth tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr, 5452316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5453fcf5ef2aSThomas Huth break; 5454fcf5ef2aSThomas Huth case 0x25: /* stfsr, V9 stxfsr */ 5455fcf5ef2aSThomas Huth { 5456fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5457fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5458fcf5ef2aSThomas Huth if (rd == 1) { 545908149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, 5460316b6783SRichard Henderson dc->mem_idx, MO_TEUQ | MO_ALIGN); 5461fcf5ef2aSThomas Huth break; 5462fcf5ef2aSThomas Huth } 5463fcf5ef2aSThomas Huth #endif 546408149118SRichard Henderson tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, 5465316b6783SRichard Henderson dc->mem_idx, MO_TEUL | MO_ALIGN); 5466fcf5ef2aSThomas Huth } 5467fcf5ef2aSThomas Huth break; 5468fcf5ef2aSThomas Huth case 0x26: 5469fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5470fcf5ef2aSThomas Huth /* V9 stqf, store quad fpreg */ 5471fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 5472fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5473fcf5ef2aSThomas Huth /* ??? While stqf only requires 4-byte alignment, it is 5474fcf5ef2aSThomas Huth legal for the cpu to signal the unaligned exception. 5475fcf5ef2aSThomas Huth The OS trap handler is then required to fix it up. 5476fcf5ef2aSThomas Huth For qemu, this avoids having to probe the second page 5477fcf5ef2aSThomas Huth before performing the first write. */ 5478fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_Q0(dc, rd); 5479fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, 5480fc313c64SFrédéric Pétrot dc->mem_idx, MO_TEUQ | MO_ALIGN_16); 5481fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); 5482fcf5ef2aSThomas Huth cpu_src2_64 = gen_load_fpr_Q1(dc, rd); 5483fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, 5484fc313c64SFrédéric Pétrot dc->mem_idx, MO_TEUQ); 5485fcf5ef2aSThomas Huth break; 5486fcf5ef2aSThomas Huth #else /* !TARGET_SPARC64 */ 5487fcf5ef2aSThomas Huth /* stdfq, store floating point queue */ 5488fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5489fcf5ef2aSThomas Huth goto illegal_insn; 5490fcf5ef2aSThomas Huth #else 5491fcf5ef2aSThomas Huth if (!supervisor(dc)) 5492fcf5ef2aSThomas Huth goto priv_insn; 5493fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5494fcf5ef2aSThomas Huth goto jmp_insn; 5495fcf5ef2aSThomas Huth } 5496fcf5ef2aSThomas Huth goto nfq_insn; 5497fcf5ef2aSThomas Huth #endif 5498fcf5ef2aSThomas Huth #endif 5499fcf5ef2aSThomas Huth case 0x27: /* stdf, store double fpreg */ 5500fcf5ef2aSThomas Huth gen_address_mask(dc, cpu_addr); 5501fcf5ef2aSThomas Huth cpu_src1_64 = gen_load_fpr_D(dc, rd); 5502fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx, 5503fc313c64SFrédéric Pétrot MO_TEUQ | MO_ALIGN_4); 5504fcf5ef2aSThomas Huth break; 5505fcf5ef2aSThomas Huth default: 5506fcf5ef2aSThomas Huth goto illegal_insn; 5507fcf5ef2aSThomas Huth } 5508fcf5ef2aSThomas Huth } else if (xop > 0x33 && xop < 0x3f) { 5509fcf5ef2aSThomas Huth switch (xop) { 5510fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5511fcf5ef2aSThomas Huth case 0x34: /* V9 stfa */ 5512fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5513fcf5ef2aSThomas Huth goto jmp_insn; 5514fcf5ef2aSThomas Huth } 5515fcf5ef2aSThomas Huth gen_stf_asi(dc, cpu_addr, insn, 4, rd); 5516fcf5ef2aSThomas Huth break; 5517fcf5ef2aSThomas Huth case 0x36: /* V9 stqfa */ 5518fcf5ef2aSThomas Huth { 5519fcf5ef2aSThomas Huth CHECK_FPU_FEATURE(dc, FLOAT128); 5520fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5521fcf5ef2aSThomas Huth goto jmp_insn; 5522fcf5ef2aSThomas Huth } 5523fcf5ef2aSThomas Huth gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); 5524fcf5ef2aSThomas Huth } 5525fcf5ef2aSThomas Huth break; 5526fcf5ef2aSThomas Huth case 0x37: /* V9 stdfa */ 5527fcf5ef2aSThomas Huth if (gen_trap_ifnofpu(dc)) { 5528fcf5ef2aSThomas Huth goto jmp_insn; 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); 5531fcf5ef2aSThomas Huth break; 5532fcf5ef2aSThomas Huth case 0x3e: /* V9 casxa */ 5533fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 5534fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 5535fcf5ef2aSThomas Huth gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); 5536fcf5ef2aSThomas Huth break; 5537fcf5ef2aSThomas Huth #else 5538fcf5ef2aSThomas Huth case 0x34: /* stc */ 5539fcf5ef2aSThomas Huth case 0x35: /* stcsr */ 5540fcf5ef2aSThomas Huth case 0x36: /* stdcq */ 5541fcf5ef2aSThomas Huth case 0x37: /* stdc */ 5542fcf5ef2aSThomas Huth goto ncp_insn; 5543fcf5ef2aSThomas Huth #endif 5544fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5545fcf5ef2aSThomas Huth case 0x3c: /* V9 or LEON3 casa */ 5546fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 5547fcf5ef2aSThomas Huth CHECK_IU_FEATURE(dc, CASA); 5548fcf5ef2aSThomas Huth #endif 5549fcf5ef2aSThomas Huth rs2 = GET_FIELD(insn, 27, 31); 5550fcf5ef2aSThomas Huth cpu_src2 = gen_load_gpr(dc, rs2); 5551fcf5ef2aSThomas Huth gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); 5552fcf5ef2aSThomas Huth break; 5553fcf5ef2aSThomas Huth #endif 5554fcf5ef2aSThomas Huth default: 5555fcf5ef2aSThomas Huth goto illegal_insn; 5556fcf5ef2aSThomas Huth } 5557fcf5ef2aSThomas Huth } else { 5558fcf5ef2aSThomas Huth goto illegal_insn; 5559fcf5ef2aSThomas Huth } 5560fcf5ef2aSThomas Huth } 5561fcf5ef2aSThomas Huth break; 5562fcf5ef2aSThomas Huth } 5563878cc677SRichard Henderson advance_pc(dc); 5564fcf5ef2aSThomas Huth jmp_insn: 5565a6ca81cbSRichard Henderson return; 5566fcf5ef2aSThomas Huth illegal_insn: 5567fcf5ef2aSThomas Huth gen_exception(dc, TT_ILL_INSN); 5568a6ca81cbSRichard Henderson return; 5569fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5570fcf5ef2aSThomas Huth priv_insn: 5571fcf5ef2aSThomas Huth gen_exception(dc, TT_PRIV_INSN); 5572a6ca81cbSRichard Henderson return; 5573fcf5ef2aSThomas Huth #endif 5574fcf5ef2aSThomas Huth nfpu_insn: 5575fcf5ef2aSThomas Huth gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); 5576a6ca81cbSRichard Henderson return; 5577fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) 5578fcf5ef2aSThomas Huth nfq_insn: 5579fcf5ef2aSThomas Huth gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); 5580a6ca81cbSRichard Henderson return; 5581fcf5ef2aSThomas Huth #endif 5582fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64 5583fcf5ef2aSThomas Huth ncp_insn: 5584fcf5ef2aSThomas Huth gen_exception(dc, TT_NCP_INSN); 5585a6ca81cbSRichard Henderson return; 5586fcf5ef2aSThomas Huth #endif 5587fcf5ef2aSThomas Huth } 5588fcf5ef2aSThomas Huth 55896e61bc94SEmilio G. Cota static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 5590fcf5ef2aSThomas Huth { 55916e61bc94SEmilio G. Cota DisasContext *dc = container_of(dcbase, DisasContext, base); 5592b77af26eSRichard Henderson CPUSPARCState *env = cpu_env(cs); 55936e61bc94SEmilio G. Cota int bound; 5594af00be49SEmilio G. Cota 5595af00be49SEmilio G. Cota dc->pc = dc->base.pc_first; 55966e61bc94SEmilio G. Cota dc->npc = (target_ulong)dc->base.tb->cs_base; 5597fcf5ef2aSThomas Huth dc->cc_op = CC_OP_DYNAMIC; 55986e61bc94SEmilio G. Cota dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK; 5599576e1c4cSIgor Mammedov dc->def = &env->def; 56006e61bc94SEmilio G. Cota dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags); 56016e61bc94SEmilio G. Cota dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags); 5602c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY 56036e61bc94SEmilio G. Cota dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0; 5604c9b459aaSArtyom Tarasenko #endif 5605fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5606fcf5ef2aSThomas Huth dc->fprs_dirty = 0; 56076e61bc94SEmilio G. Cota dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; 5608c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY 56096e61bc94SEmilio G. Cota dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; 5610c9b459aaSArtyom Tarasenko #endif 5611fcf5ef2aSThomas Huth #endif 56126e61bc94SEmilio G. Cota /* 56136e61bc94SEmilio G. Cota * if we reach a page boundary, we stop generation so that the 56146e61bc94SEmilio G. Cota * PC of a TT_TFAULT exception is always in the right page 56156e61bc94SEmilio G. Cota */ 56166e61bc94SEmilio G. Cota bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; 56176e61bc94SEmilio G. Cota dc->base.max_insns = MIN(dc->base.max_insns, bound); 5618af00be49SEmilio G. Cota } 5619fcf5ef2aSThomas Huth 56206e61bc94SEmilio G. Cota static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs) 56216e61bc94SEmilio G. Cota { 56226e61bc94SEmilio G. Cota } 56236e61bc94SEmilio G. Cota 56246e61bc94SEmilio G. Cota static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 56256e61bc94SEmilio G. Cota { 56266e61bc94SEmilio G. Cota DisasContext *dc = container_of(dcbase, DisasContext, base); 5627633c4283SRichard Henderson target_ulong npc = dc->npc; 56286e61bc94SEmilio G. Cota 5629633c4283SRichard Henderson if (npc & 3) { 5630633c4283SRichard Henderson switch (npc) { 5631633c4283SRichard Henderson case JUMP_PC: 5632fcf5ef2aSThomas Huth assert(dc->jump_pc[1] == dc->pc + 4); 5633633c4283SRichard Henderson npc = dc->jump_pc[0] | JUMP_PC; 5634633c4283SRichard Henderson break; 5635633c4283SRichard Henderson case DYNAMIC_PC: 5636633c4283SRichard Henderson case DYNAMIC_PC_LOOKUP: 5637633c4283SRichard Henderson npc = DYNAMIC_PC; 5638633c4283SRichard Henderson break; 5639633c4283SRichard Henderson default: 5640633c4283SRichard Henderson g_assert_not_reached(); 5641fcf5ef2aSThomas Huth } 56426e61bc94SEmilio G. Cota } 5643633c4283SRichard Henderson tcg_gen_insn_start(dc->pc, npc); 5644633c4283SRichard Henderson } 5645fcf5ef2aSThomas Huth 56466e61bc94SEmilio G. Cota static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 56476e61bc94SEmilio G. Cota { 56486e61bc94SEmilio G. Cota DisasContext *dc = container_of(dcbase, DisasContext, base); 5649b77af26eSRichard Henderson CPUSPARCState *env = cpu_env(cs); 56506e61bc94SEmilio G. Cota unsigned int insn; 5651fcf5ef2aSThomas Huth 56524e116893SIlya Leoshkevich insn = translator_ldl(env, &dc->base, dc->pc); 5653af00be49SEmilio G. Cota dc->base.pc_next += 4; 5654878cc677SRichard Henderson 5655878cc677SRichard Henderson if (!decode(dc, insn)) { 5656878cc677SRichard Henderson disas_sparc_legacy(dc, insn); 5657878cc677SRichard Henderson } 5658fcf5ef2aSThomas Huth 5659af00be49SEmilio G. Cota if (dc->base.is_jmp == DISAS_NORETURN) { 56606e61bc94SEmilio G. Cota return; 5661c5e6ccdfSEmilio G. Cota } 5662af00be49SEmilio G. Cota if (dc->pc != dc->base.pc_next) { 56636e61bc94SEmilio G. Cota dc->base.is_jmp = DISAS_TOO_MANY; 5664af00be49SEmilio G. Cota } 56656e61bc94SEmilio G. Cota } 5666fcf5ef2aSThomas Huth 56676e61bc94SEmilio G. Cota static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 56686e61bc94SEmilio G. Cota { 56696e61bc94SEmilio G. Cota DisasContext *dc = container_of(dcbase, DisasContext, base); 5670186e7890SRichard Henderson DisasDelayException *e, *e_next; 5671633c4283SRichard Henderson bool may_lookup; 56726e61bc94SEmilio G. Cota 567346bb0137SMark Cave-Ayland switch (dc->base.is_jmp) { 567446bb0137SMark Cave-Ayland case DISAS_NEXT: 567546bb0137SMark Cave-Ayland case DISAS_TOO_MANY: 5676633c4283SRichard Henderson if (((dc->pc | dc->npc) & 3) == 0) { 5677fcf5ef2aSThomas Huth /* static PC and NPC: we can use direct chaining */ 5678fcf5ef2aSThomas Huth gen_goto_tb(dc, 0, dc->pc, dc->npc); 5679633c4283SRichard Henderson break; 5680fcf5ef2aSThomas Huth } 5681633c4283SRichard Henderson 5682930f1865SRichard Henderson may_lookup = true; 5683633c4283SRichard Henderson if (dc->pc & 3) { 5684633c4283SRichard Henderson switch (dc->pc) { 5685633c4283SRichard Henderson case DYNAMIC_PC_LOOKUP: 5686633c4283SRichard Henderson break; 5687633c4283SRichard Henderson case DYNAMIC_PC: 5688633c4283SRichard Henderson may_lookup = false; 5689633c4283SRichard Henderson break; 5690633c4283SRichard Henderson default: 5691633c4283SRichard Henderson g_assert_not_reached(); 5692633c4283SRichard Henderson } 5693633c4283SRichard Henderson } else { 5694633c4283SRichard Henderson tcg_gen_movi_tl(cpu_pc, dc->pc); 5695633c4283SRichard Henderson } 5696633c4283SRichard Henderson 5697930f1865SRichard Henderson if (dc->npc & 3) { 5698930f1865SRichard Henderson switch (dc->npc) { 5699930f1865SRichard Henderson case JUMP_PC: 5700930f1865SRichard Henderson gen_generic_branch(dc); 5701930f1865SRichard Henderson break; 5702930f1865SRichard Henderson case DYNAMIC_PC: 5703930f1865SRichard Henderson may_lookup = false; 5704930f1865SRichard Henderson break; 5705930f1865SRichard Henderson case DYNAMIC_PC_LOOKUP: 5706930f1865SRichard Henderson break; 5707930f1865SRichard Henderson default: 5708930f1865SRichard Henderson g_assert_not_reached(); 5709930f1865SRichard Henderson } 5710930f1865SRichard Henderson } else { 5711930f1865SRichard Henderson tcg_gen_movi_tl(cpu_npc, dc->npc); 5712930f1865SRichard Henderson } 5713633c4283SRichard Henderson if (may_lookup) { 5714633c4283SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 5715633c4283SRichard Henderson } else { 571607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 5717fcf5ef2aSThomas Huth } 571846bb0137SMark Cave-Ayland break; 571946bb0137SMark Cave-Ayland 572046bb0137SMark Cave-Ayland case DISAS_NORETURN: 572146bb0137SMark Cave-Ayland break; 572246bb0137SMark Cave-Ayland 572346bb0137SMark Cave-Ayland case DISAS_EXIT: 572446bb0137SMark Cave-Ayland /* Exit TB */ 572546bb0137SMark Cave-Ayland save_state(dc); 572646bb0137SMark Cave-Ayland tcg_gen_exit_tb(NULL, 0); 572746bb0137SMark Cave-Ayland break; 572846bb0137SMark Cave-Ayland 572946bb0137SMark Cave-Ayland default: 573046bb0137SMark Cave-Ayland g_assert_not_reached(); 5731fcf5ef2aSThomas Huth } 5732186e7890SRichard Henderson 5733186e7890SRichard Henderson for (e = dc->delay_excp_list; e ; e = e_next) { 5734186e7890SRichard Henderson gen_set_label(e->lab); 5735186e7890SRichard Henderson 5736186e7890SRichard Henderson tcg_gen_movi_tl(cpu_pc, e->pc); 5737186e7890SRichard Henderson if (e->npc % 4 == 0) { 5738186e7890SRichard Henderson tcg_gen_movi_tl(cpu_npc, e->npc); 5739186e7890SRichard Henderson } 5740186e7890SRichard Henderson gen_helper_raise_exception(tcg_env, e->excp); 5741186e7890SRichard Henderson 5742186e7890SRichard Henderson e_next = e->next; 5743186e7890SRichard Henderson g_free(e); 5744186e7890SRichard Henderson } 5745fcf5ef2aSThomas Huth } 57466e61bc94SEmilio G. Cota 57478eb806a7SRichard Henderson static void sparc_tr_disas_log(const DisasContextBase *dcbase, 57488eb806a7SRichard Henderson CPUState *cpu, FILE *logfile) 57496e61bc94SEmilio G. Cota { 57508eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 57518eb806a7SRichard Henderson target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 57526e61bc94SEmilio G. Cota } 57536e61bc94SEmilio G. Cota 57546e61bc94SEmilio G. Cota static const TranslatorOps sparc_tr_ops = { 57556e61bc94SEmilio G. Cota .init_disas_context = sparc_tr_init_disas_context, 57566e61bc94SEmilio G. Cota .tb_start = sparc_tr_tb_start, 57576e61bc94SEmilio G. Cota .insn_start = sparc_tr_insn_start, 57586e61bc94SEmilio G. Cota .translate_insn = sparc_tr_translate_insn, 57596e61bc94SEmilio G. Cota .tb_stop = sparc_tr_tb_stop, 57606e61bc94SEmilio G. Cota .disas_log = sparc_tr_disas_log, 57616e61bc94SEmilio G. Cota }; 57626e61bc94SEmilio G. Cota 5763597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 5764306c8721SRichard Henderson target_ulong pc, void *host_pc) 57656e61bc94SEmilio G. Cota { 57666e61bc94SEmilio G. Cota DisasContext dc = {}; 57676e61bc94SEmilio G. Cota 5768306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base); 5769fcf5ef2aSThomas Huth } 5770fcf5ef2aSThomas Huth 577155c3ceefSRichard Henderson void sparc_tcg_init(void) 5772fcf5ef2aSThomas Huth { 5773fcf5ef2aSThomas Huth static const char gregnames[32][4] = { 5774fcf5ef2aSThomas Huth "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 5775fcf5ef2aSThomas Huth "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 5776fcf5ef2aSThomas Huth "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 5777fcf5ef2aSThomas Huth "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 5778fcf5ef2aSThomas Huth }; 5779fcf5ef2aSThomas Huth static const char fregnames[32][4] = { 5780fcf5ef2aSThomas Huth "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14", 5781fcf5ef2aSThomas Huth "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30", 5782fcf5ef2aSThomas Huth "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", 5783fcf5ef2aSThomas Huth "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", 5784fcf5ef2aSThomas Huth }; 5785fcf5ef2aSThomas Huth 5786fcf5ef2aSThomas Huth static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = { 5787fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5788fcf5ef2aSThomas Huth { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, 5789fcf5ef2aSThomas Huth { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, 5790fcf5ef2aSThomas Huth #else 5791fcf5ef2aSThomas Huth { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" }, 5792fcf5ef2aSThomas Huth #endif 5793fcf5ef2aSThomas Huth { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, 5794fcf5ef2aSThomas Huth { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" }, 5795fcf5ef2aSThomas Huth }; 5796fcf5ef2aSThomas Huth 5797fcf5ef2aSThomas Huth static const struct { TCGv *ptr; int off; const char *name; } rtl[] = { 5798fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 5799fcf5ef2aSThomas Huth { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, 5800fcf5ef2aSThomas Huth { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" }, 5801fcf5ef2aSThomas Huth { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" }, 5802fcf5ef2aSThomas Huth { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr), 5803fcf5ef2aSThomas Huth "hstick_cmpr" }, 5804fcf5ef2aSThomas Huth { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" }, 5805fcf5ef2aSThomas Huth { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" }, 5806fcf5ef2aSThomas Huth { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" }, 5807fcf5ef2aSThomas Huth { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" }, 5808fcf5ef2aSThomas Huth { &cpu_ver, offsetof(CPUSPARCState, version), "ver" }, 5809fcf5ef2aSThomas Huth #endif 5810fcf5ef2aSThomas Huth { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, 5811fcf5ef2aSThomas Huth { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, 5812fcf5ef2aSThomas Huth { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" }, 5813fcf5ef2aSThomas Huth { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" }, 5814fcf5ef2aSThomas Huth { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" }, 5815fcf5ef2aSThomas Huth { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, 5816fcf5ef2aSThomas Huth { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, 5817fcf5ef2aSThomas Huth { &cpu_y, offsetof(CPUSPARCState, y), "y" }, 5818fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 5819fcf5ef2aSThomas Huth { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" }, 5820fcf5ef2aSThomas Huth #endif 5821fcf5ef2aSThomas Huth }; 5822fcf5ef2aSThomas Huth 5823fcf5ef2aSThomas Huth unsigned int i; 5824fcf5ef2aSThomas Huth 5825ad75a51eSRichard Henderson cpu_regwptr = tcg_global_mem_new_ptr(tcg_env, 5826fcf5ef2aSThomas Huth offsetof(CPUSPARCState, regwptr), 5827fcf5ef2aSThomas Huth "regwptr"); 5828fcf5ef2aSThomas Huth 5829fcf5ef2aSThomas Huth for (i = 0; i < ARRAY_SIZE(r32); ++i) { 5830ad75a51eSRichard Henderson *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name); 5831fcf5ef2aSThomas Huth } 5832fcf5ef2aSThomas Huth 5833fcf5ef2aSThomas Huth for (i = 0; i < ARRAY_SIZE(rtl); ++i) { 5834ad75a51eSRichard Henderson *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name); 5835fcf5ef2aSThomas Huth } 5836fcf5ef2aSThomas Huth 5837f764718dSRichard Henderson cpu_regs[0] = NULL; 5838fcf5ef2aSThomas Huth for (i = 1; i < 8; ++i) { 5839ad75a51eSRichard Henderson cpu_regs[i] = tcg_global_mem_new(tcg_env, 5840fcf5ef2aSThomas Huth offsetof(CPUSPARCState, gregs[i]), 5841fcf5ef2aSThomas Huth gregnames[i]); 5842fcf5ef2aSThomas Huth } 5843fcf5ef2aSThomas Huth 5844fcf5ef2aSThomas Huth for (i = 8; i < 32; ++i) { 5845fcf5ef2aSThomas Huth cpu_regs[i] = tcg_global_mem_new(cpu_regwptr, 5846fcf5ef2aSThomas Huth (i - 8) * sizeof(target_ulong), 5847fcf5ef2aSThomas Huth gregnames[i]); 5848fcf5ef2aSThomas Huth } 5849fcf5ef2aSThomas Huth 5850fcf5ef2aSThomas Huth for (i = 0; i < TARGET_DPREGS; i++) { 5851ad75a51eSRichard Henderson cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 5852fcf5ef2aSThomas Huth offsetof(CPUSPARCState, fpr[i]), 5853fcf5ef2aSThomas Huth fregnames[i]); 5854fcf5ef2aSThomas Huth } 5855fcf5ef2aSThomas Huth } 5856fcf5ef2aSThomas Huth 5857f36aaa53SRichard Henderson void sparc_restore_state_to_opc(CPUState *cs, 5858f36aaa53SRichard Henderson const TranslationBlock *tb, 5859f36aaa53SRichard Henderson const uint64_t *data) 5860fcf5ef2aSThomas Huth { 5861f36aaa53SRichard Henderson SPARCCPU *cpu = SPARC_CPU(cs); 5862f36aaa53SRichard Henderson CPUSPARCState *env = &cpu->env; 5863fcf5ef2aSThomas Huth target_ulong pc = data[0]; 5864fcf5ef2aSThomas Huth target_ulong npc = data[1]; 5865fcf5ef2aSThomas Huth 5866fcf5ef2aSThomas Huth env->pc = pc; 5867fcf5ef2aSThomas Huth if (npc == DYNAMIC_PC) { 5868fcf5ef2aSThomas Huth /* dynamic NPC: already stored */ 5869fcf5ef2aSThomas Huth } else if (npc & JUMP_PC) { 5870fcf5ef2aSThomas Huth /* jump PC: use 'cond' and the jump targets of the translation */ 5871fcf5ef2aSThomas Huth if (env->cond) { 5872fcf5ef2aSThomas Huth env->npc = npc & ~3; 5873fcf5ef2aSThomas Huth } else { 5874fcf5ef2aSThomas Huth env->npc = pc + 4; 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth } else { 5877fcf5ef2aSThomas Huth env->npc = npc; 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth } 5880