xref: /openbmc/qemu/target/sparc/translate.c (revision 36ab4623a894de80c413fa958a5fdb79dc50b1c2)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth    SPARC translation
3fcf5ef2aSThomas Huth 
4fcf5ef2aSThomas Huth    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5fcf5ef2aSThomas Huth    Copyright (C) 2003-2005 Fabrice Bellard
6fcf5ef2aSThomas Huth 
7fcf5ef2aSThomas Huth    This library is free software; you can redistribute it and/or
8fcf5ef2aSThomas Huth    modify it under the terms of the GNU Lesser General Public
9fcf5ef2aSThomas Huth    License as published by the Free Software Foundation; either
105650b549SChetan Pant    version 2.1 of the License, or (at your option) any later version.
11fcf5ef2aSThomas Huth 
12fcf5ef2aSThomas Huth    This library is distributed in the hope that it will be useful,
13fcf5ef2aSThomas Huth    but WITHOUT ANY WARRANTY; without even the implied warranty of
14fcf5ef2aSThomas Huth    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15fcf5ef2aSThomas Huth    Lesser General Public License for more details.
16fcf5ef2aSThomas Huth 
17fcf5ef2aSThomas Huth    You should have received a copy of the GNU Lesser General Public
18fcf5ef2aSThomas Huth    License along with this library; if not, see <http://www.gnu.org/licenses/>.
19fcf5ef2aSThomas Huth  */
20fcf5ef2aSThomas Huth 
21fcf5ef2aSThomas Huth #include "qemu/osdep.h"
22fcf5ef2aSThomas Huth 
23fcf5ef2aSThomas Huth #include "cpu.h"
24fcf5ef2aSThomas Huth #include "disas/disas.h"
25fcf5ef2aSThomas Huth #include "exec/helper-proto.h"
26fcf5ef2aSThomas Huth #include "exec/exec-all.h"
27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h"
28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h"
29fcf5ef2aSThomas Huth 
30fcf5ef2aSThomas Huth #include "exec/helper-gen.h"
31fcf5ef2aSThomas Huth 
32c5e6ccdfSEmilio G. Cota #include "exec/translator.h"
33fcf5ef2aSThomas Huth #include "exec/log.h"
34fcf5ef2aSThomas Huth #include "asi.h"
35fcf5ef2aSThomas Huth 
36fcf5ef2aSThomas Huth 
37fcf5ef2aSThomas Huth #define DEBUG_DISAS
38fcf5ef2aSThomas Huth 
39fcf5ef2aSThomas Huth #define DYNAMIC_PC  1 /* dynamic pc value */
40fcf5ef2aSThomas Huth #define JUMP_PC     2 /* dynamic pc value which takes only two values
41fcf5ef2aSThomas Huth                          according to jump_pc[T2] */
42fcf5ef2aSThomas Huth 
4346bb0137SMark Cave-Ayland #define DISAS_EXIT  DISAS_TARGET_0
4446bb0137SMark Cave-Ayland 
45fcf5ef2aSThomas Huth /* global register indexes */
46fcf5ef2aSThomas Huth static TCGv_ptr cpu_regwptr;
47fcf5ef2aSThomas Huth static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
48fcf5ef2aSThomas Huth static TCGv_i32 cpu_cc_op;
49fcf5ef2aSThomas Huth static TCGv_i32 cpu_psr;
50fcf5ef2aSThomas Huth static TCGv cpu_fsr, cpu_pc, cpu_npc;
51fcf5ef2aSThomas Huth static TCGv cpu_regs[32];
52fcf5ef2aSThomas Huth static TCGv cpu_y;
53fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY
54fcf5ef2aSThomas Huth static TCGv cpu_tbr;
55fcf5ef2aSThomas Huth #endif
56fcf5ef2aSThomas Huth static TCGv cpu_cond;
57fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
58fcf5ef2aSThomas Huth static TCGv_i32 cpu_xcc, cpu_fprs;
59fcf5ef2aSThomas Huth static TCGv cpu_gsr;
60fcf5ef2aSThomas Huth static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
61fcf5ef2aSThomas Huth static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
62fcf5ef2aSThomas Huth #else
63fcf5ef2aSThomas Huth static TCGv cpu_wim;
64fcf5ef2aSThomas Huth #endif
65fcf5ef2aSThomas Huth /* Floating point registers */
66fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[TARGET_DPREGS];
67fcf5ef2aSThomas Huth 
68fcf5ef2aSThomas Huth #include "exec/gen-icount.h"
69fcf5ef2aSThomas Huth 
70fcf5ef2aSThomas Huth typedef struct DisasContext {
71af00be49SEmilio G. Cota     DisasContextBase base;
72fcf5ef2aSThomas Huth     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
73fcf5ef2aSThomas Huth     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
74fcf5ef2aSThomas Huth     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
75fcf5ef2aSThomas Huth     int mem_idx;
76c9b459aaSArtyom Tarasenko     bool fpu_enabled;
77c9b459aaSArtyom Tarasenko     bool address_mask_32bit;
78c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
79c9b459aaSArtyom Tarasenko     bool supervisor;
80c9b459aaSArtyom Tarasenko #ifdef TARGET_SPARC64
81c9b459aaSArtyom Tarasenko     bool hypervisor;
82c9b459aaSArtyom Tarasenko #endif
83c9b459aaSArtyom Tarasenko #endif
84c9b459aaSArtyom Tarasenko 
85fcf5ef2aSThomas Huth     uint32_t cc_op;  /* current CC operation */
86fcf5ef2aSThomas Huth     sparc_def_t *def;
87fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
88fcf5ef2aSThomas Huth     int fprs_dirty;
89fcf5ef2aSThomas Huth     int asi;
90fcf5ef2aSThomas Huth #endif
91fcf5ef2aSThomas Huth } DisasContext;
92fcf5ef2aSThomas Huth 
93fcf5ef2aSThomas Huth typedef struct {
94fcf5ef2aSThomas Huth     TCGCond cond;
95fcf5ef2aSThomas Huth     bool is_bool;
96fcf5ef2aSThomas Huth     bool g1, g2;
97fcf5ef2aSThomas Huth     TCGv c1, c2;
98fcf5ef2aSThomas Huth } DisasCompare;
99fcf5ef2aSThomas Huth 
100fcf5ef2aSThomas Huth // This function uses non-native bit order
101fcf5ef2aSThomas Huth #define GET_FIELD(X, FROM, TO)                                  \
102fcf5ef2aSThomas Huth     ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
103fcf5ef2aSThomas Huth 
104fcf5ef2aSThomas Huth // This function uses the order in the manuals, i.e. bit 0 is 2^0
105fcf5ef2aSThomas Huth #define GET_FIELD_SP(X, FROM, TO)               \
106fcf5ef2aSThomas Huth     GET_FIELD(X, 31 - (TO), 31 - (FROM))
107fcf5ef2aSThomas Huth 
108fcf5ef2aSThomas Huth #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
109fcf5ef2aSThomas Huth #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
110fcf5ef2aSThomas Huth 
111fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
112fcf5ef2aSThomas Huth #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
113fcf5ef2aSThomas Huth #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
114fcf5ef2aSThomas Huth #else
115fcf5ef2aSThomas Huth #define DFPREG(r) (r & 0x1e)
116fcf5ef2aSThomas Huth #define QFPREG(r) (r & 0x1c)
117fcf5ef2aSThomas Huth #endif
118fcf5ef2aSThomas Huth 
119fcf5ef2aSThomas Huth #define UA2005_HTRAP_MASK 0xff
120fcf5ef2aSThomas Huth #define V8_TRAP_MASK 0x7f
121fcf5ef2aSThomas Huth 
122fcf5ef2aSThomas Huth static int sign_extend(int x, int len)
123fcf5ef2aSThomas Huth {
124fcf5ef2aSThomas Huth     len = 32 - len;
125fcf5ef2aSThomas Huth     return (x << len) >> len;
126fcf5ef2aSThomas Huth }
127fcf5ef2aSThomas Huth 
128fcf5ef2aSThomas Huth #define IS_IMM (insn & (1<<13))
129fcf5ef2aSThomas Huth 
130fcf5ef2aSThomas Huth static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
131fcf5ef2aSThomas Huth {
132fcf5ef2aSThomas Huth #if defined(TARGET_SPARC64)
133fcf5ef2aSThomas Huth     int bit = (rd < 32) ? 1 : 2;
134fcf5ef2aSThomas Huth     /* If we know we've already set this bit within the TB,
135fcf5ef2aSThomas Huth        we can avoid setting it again.  */
136fcf5ef2aSThomas Huth     if (!(dc->fprs_dirty & bit)) {
137fcf5ef2aSThomas Huth         dc->fprs_dirty |= bit;
138fcf5ef2aSThomas Huth         tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
139fcf5ef2aSThomas Huth     }
140fcf5ef2aSThomas Huth #endif
141fcf5ef2aSThomas Huth }
142fcf5ef2aSThomas Huth 
143fcf5ef2aSThomas Huth /* floating point registers moves */
144fcf5ef2aSThomas Huth static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
145fcf5ef2aSThomas Huth {
146*36ab4623SRichard Henderson     TCGv_i32 ret = tcg_temp_new_i32();
147dc41aa7dSRichard Henderson     if (src & 1) {
148dc41aa7dSRichard Henderson         tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
149dc41aa7dSRichard Henderson     } else {
150dc41aa7dSRichard Henderson         tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
151fcf5ef2aSThomas Huth     }
152dc41aa7dSRichard Henderson     return ret;
153fcf5ef2aSThomas Huth }
154fcf5ef2aSThomas Huth 
155fcf5ef2aSThomas Huth static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
156fcf5ef2aSThomas Huth {
1578e7bbc75SRichard Henderson     TCGv_i64 t = tcg_temp_new_i64();
1588e7bbc75SRichard Henderson 
1598e7bbc75SRichard Henderson     tcg_gen_extu_i32_i64(t, v);
160fcf5ef2aSThomas Huth     tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
161fcf5ef2aSThomas Huth                         (dst & 1 ? 0 : 32), 32);
1628e7bbc75SRichard Henderson     tcg_temp_free_i64(t);
163fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, dst);
164fcf5ef2aSThomas Huth }
165fcf5ef2aSThomas Huth 
166fcf5ef2aSThomas Huth static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
167fcf5ef2aSThomas Huth {
168*36ab4623SRichard Henderson     return tcg_temp_new_i32();
169fcf5ef2aSThomas Huth }
170fcf5ef2aSThomas Huth 
171fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
172fcf5ef2aSThomas Huth {
173fcf5ef2aSThomas Huth     src = DFPREG(src);
174fcf5ef2aSThomas Huth     return cpu_fpr[src / 2];
175fcf5ef2aSThomas Huth }
176fcf5ef2aSThomas Huth 
177fcf5ef2aSThomas Huth static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
178fcf5ef2aSThomas Huth {
179fcf5ef2aSThomas Huth     dst = DFPREG(dst);
180fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
181fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, dst);
182fcf5ef2aSThomas Huth }
183fcf5ef2aSThomas Huth 
184fcf5ef2aSThomas Huth static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
185fcf5ef2aSThomas Huth {
186fcf5ef2aSThomas Huth     return cpu_fpr[DFPREG(dst) / 2];
187fcf5ef2aSThomas Huth }
188fcf5ef2aSThomas Huth 
189fcf5ef2aSThomas Huth static void gen_op_load_fpr_QT0(unsigned int src)
190fcf5ef2aSThomas Huth {
191fcf5ef2aSThomas Huth     tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
192fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.upper));
193fcf5ef2aSThomas Huth     tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
194fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.lower));
195fcf5ef2aSThomas Huth }
196fcf5ef2aSThomas Huth 
197fcf5ef2aSThomas Huth static void gen_op_load_fpr_QT1(unsigned int src)
198fcf5ef2aSThomas Huth {
199fcf5ef2aSThomas Huth     tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
200fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.upper));
201fcf5ef2aSThomas Huth     tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
202fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.lower));
203fcf5ef2aSThomas Huth }
204fcf5ef2aSThomas Huth 
205fcf5ef2aSThomas Huth static void gen_op_store_QT0_fpr(unsigned int dst)
206fcf5ef2aSThomas Huth {
207fcf5ef2aSThomas Huth     tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
208fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.upper));
209fcf5ef2aSThomas Huth     tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
210fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.lower));
211fcf5ef2aSThomas Huth }
212fcf5ef2aSThomas Huth 
213fcf5ef2aSThomas Huth static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
214fcf5ef2aSThomas Huth                             TCGv_i64 v1, TCGv_i64 v2)
215fcf5ef2aSThomas Huth {
216fcf5ef2aSThomas Huth     dst = QFPREG(dst);
217fcf5ef2aSThomas Huth 
218fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
219fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
220fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, dst);
221fcf5ef2aSThomas Huth }
222fcf5ef2aSThomas Huth 
223fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
224fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
225fcf5ef2aSThomas Huth {
226fcf5ef2aSThomas Huth     src = QFPREG(src);
227fcf5ef2aSThomas Huth     return cpu_fpr[src / 2];
228fcf5ef2aSThomas Huth }
229fcf5ef2aSThomas Huth 
230fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
231fcf5ef2aSThomas Huth {
232fcf5ef2aSThomas Huth     src = QFPREG(src);
233fcf5ef2aSThomas Huth     return cpu_fpr[src / 2 + 1];
234fcf5ef2aSThomas Huth }
235fcf5ef2aSThomas Huth 
236fcf5ef2aSThomas Huth static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
237fcf5ef2aSThomas Huth {
238fcf5ef2aSThomas Huth     rd = QFPREG(rd);
239fcf5ef2aSThomas Huth     rs = QFPREG(rs);
240fcf5ef2aSThomas Huth 
241fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
242fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
243fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, rd);
244fcf5ef2aSThomas Huth }
245fcf5ef2aSThomas Huth #endif
246fcf5ef2aSThomas Huth 
247fcf5ef2aSThomas Huth /* moves */
248fcf5ef2aSThomas Huth #ifdef CONFIG_USER_ONLY
249fcf5ef2aSThomas Huth #define supervisor(dc) 0
250fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
251fcf5ef2aSThomas Huth #define hypervisor(dc) 0
252fcf5ef2aSThomas Huth #endif
253fcf5ef2aSThomas Huth #else
254fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
255c9b459aaSArtyom Tarasenko #define hypervisor(dc) (dc->hypervisor)
256c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor | dc->hypervisor)
257fcf5ef2aSThomas Huth #else
258c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor)
259fcf5ef2aSThomas Huth #endif
260fcf5ef2aSThomas Huth #endif
261fcf5ef2aSThomas Huth 
262fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
263fcf5ef2aSThomas Huth #ifndef TARGET_ABI32
264fcf5ef2aSThomas Huth #define AM_CHECK(dc) ((dc)->address_mask_32bit)
265fcf5ef2aSThomas Huth #else
266fcf5ef2aSThomas Huth #define AM_CHECK(dc) (1)
267fcf5ef2aSThomas Huth #endif
268fcf5ef2aSThomas Huth #endif
269fcf5ef2aSThomas Huth 
270fcf5ef2aSThomas Huth static inline void gen_address_mask(DisasContext *dc, TCGv addr)
271fcf5ef2aSThomas Huth {
272fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
273fcf5ef2aSThomas Huth     if (AM_CHECK(dc))
274fcf5ef2aSThomas Huth         tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
275fcf5ef2aSThomas Huth #endif
276fcf5ef2aSThomas Huth }
277fcf5ef2aSThomas Huth 
278fcf5ef2aSThomas Huth static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
279fcf5ef2aSThomas Huth {
280fcf5ef2aSThomas Huth     if (reg > 0) {
281fcf5ef2aSThomas Huth         assert(reg < 32);
282fcf5ef2aSThomas Huth         return cpu_regs[reg];
283fcf5ef2aSThomas Huth     } else {
28452123f14SRichard Henderson         TCGv t = tcg_temp_new();
285fcf5ef2aSThomas Huth         tcg_gen_movi_tl(t, 0);
286fcf5ef2aSThomas Huth         return t;
287fcf5ef2aSThomas Huth     }
288fcf5ef2aSThomas Huth }
289fcf5ef2aSThomas Huth 
290fcf5ef2aSThomas Huth static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
291fcf5ef2aSThomas Huth {
292fcf5ef2aSThomas Huth     if (reg > 0) {
293fcf5ef2aSThomas Huth         assert(reg < 32);
294fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_regs[reg], v);
295fcf5ef2aSThomas Huth     }
296fcf5ef2aSThomas Huth }
297fcf5ef2aSThomas Huth 
298fcf5ef2aSThomas Huth static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
299fcf5ef2aSThomas Huth {
300fcf5ef2aSThomas Huth     if (reg > 0) {
301fcf5ef2aSThomas Huth         assert(reg < 32);
302fcf5ef2aSThomas Huth         return cpu_regs[reg];
303fcf5ef2aSThomas Huth     } else {
30452123f14SRichard Henderson         return tcg_temp_new();
305fcf5ef2aSThomas Huth     }
306fcf5ef2aSThomas Huth }
307fcf5ef2aSThomas Huth 
3085645aa2eSRichard Henderson static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
309fcf5ef2aSThomas Huth {
3105645aa2eSRichard Henderson     return translator_use_goto_tb(&s->base, pc) &&
3115645aa2eSRichard Henderson            translator_use_goto_tb(&s->base, npc);
312fcf5ef2aSThomas Huth }
313fcf5ef2aSThomas Huth 
3145645aa2eSRichard Henderson static void gen_goto_tb(DisasContext *s, int tb_num,
315fcf5ef2aSThomas Huth                         target_ulong pc, target_ulong npc)
316fcf5ef2aSThomas Huth {
317fcf5ef2aSThomas Huth     if (use_goto_tb(s, pc, npc))  {
318fcf5ef2aSThomas Huth         /* jump to same page: we can use a direct jump */
319fcf5ef2aSThomas Huth         tcg_gen_goto_tb(tb_num);
320fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_pc, pc);
321fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, npc);
32207ea28b4SRichard Henderson         tcg_gen_exit_tb(s->base.tb, tb_num);
323fcf5ef2aSThomas Huth     } else {
324fcf5ef2aSThomas Huth         /* jump to another page: currently not optimized */
325fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_pc, pc);
326fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, npc);
32707ea28b4SRichard Henderson         tcg_gen_exit_tb(NULL, 0);
328fcf5ef2aSThomas Huth     }
329fcf5ef2aSThomas Huth }
330fcf5ef2aSThomas Huth 
331fcf5ef2aSThomas Huth // XXX suboptimal
332fcf5ef2aSThomas Huth static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
333fcf5ef2aSThomas Huth {
334fcf5ef2aSThomas Huth     tcg_gen_extu_i32_tl(reg, src);
3350b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
336fcf5ef2aSThomas Huth }
337fcf5ef2aSThomas Huth 
338fcf5ef2aSThomas Huth static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
339fcf5ef2aSThomas Huth {
340fcf5ef2aSThomas Huth     tcg_gen_extu_i32_tl(reg, src);
3410b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
342fcf5ef2aSThomas Huth }
343fcf5ef2aSThomas Huth 
344fcf5ef2aSThomas Huth static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
345fcf5ef2aSThomas Huth {
346fcf5ef2aSThomas Huth     tcg_gen_extu_i32_tl(reg, src);
3470b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
348fcf5ef2aSThomas Huth }
349fcf5ef2aSThomas Huth 
350fcf5ef2aSThomas Huth static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
351fcf5ef2aSThomas Huth {
352fcf5ef2aSThomas Huth     tcg_gen_extu_i32_tl(reg, src);
3530b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
354fcf5ef2aSThomas Huth }
355fcf5ef2aSThomas Huth 
356fcf5ef2aSThomas Huth static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
357fcf5ef2aSThomas Huth {
358fcf5ef2aSThomas Huth     tcg_gen_mov_tl(cpu_cc_src, src1);
359fcf5ef2aSThomas Huth     tcg_gen_mov_tl(cpu_cc_src2, src2);
360fcf5ef2aSThomas Huth     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
361fcf5ef2aSThomas Huth     tcg_gen_mov_tl(dst, cpu_cc_dst);
362fcf5ef2aSThomas Huth }
363fcf5ef2aSThomas Huth 
364fcf5ef2aSThomas Huth static TCGv_i32 gen_add32_carry32(void)
365fcf5ef2aSThomas Huth {
366fcf5ef2aSThomas Huth     TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
367fcf5ef2aSThomas Huth 
368fcf5ef2aSThomas Huth     /* Carry is computed from a previous add: (dst < src)  */
369fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
370fcf5ef2aSThomas Huth     cc_src1_32 = tcg_temp_new_i32();
371fcf5ef2aSThomas Huth     cc_src2_32 = tcg_temp_new_i32();
372fcf5ef2aSThomas Huth     tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
373fcf5ef2aSThomas Huth     tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
374fcf5ef2aSThomas Huth #else
375fcf5ef2aSThomas Huth     cc_src1_32 = cpu_cc_dst;
376fcf5ef2aSThomas Huth     cc_src2_32 = cpu_cc_src;
377fcf5ef2aSThomas Huth #endif
378fcf5ef2aSThomas Huth 
379fcf5ef2aSThomas Huth     carry_32 = tcg_temp_new_i32();
380fcf5ef2aSThomas Huth     tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
381fcf5ef2aSThomas Huth 
382fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
383fcf5ef2aSThomas Huth     tcg_temp_free_i32(cc_src1_32);
384fcf5ef2aSThomas Huth     tcg_temp_free_i32(cc_src2_32);
385fcf5ef2aSThomas Huth #endif
386fcf5ef2aSThomas Huth 
387fcf5ef2aSThomas Huth     return carry_32;
388fcf5ef2aSThomas Huth }
389fcf5ef2aSThomas Huth 
390fcf5ef2aSThomas Huth static TCGv_i32 gen_sub32_carry32(void)
391fcf5ef2aSThomas Huth {
392fcf5ef2aSThomas Huth     TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
393fcf5ef2aSThomas Huth 
394fcf5ef2aSThomas Huth     /* Carry is computed from a previous borrow: (src1 < src2)  */
395fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
396fcf5ef2aSThomas Huth     cc_src1_32 = tcg_temp_new_i32();
397fcf5ef2aSThomas Huth     cc_src2_32 = tcg_temp_new_i32();
398fcf5ef2aSThomas Huth     tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
399fcf5ef2aSThomas Huth     tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
400fcf5ef2aSThomas Huth #else
401fcf5ef2aSThomas Huth     cc_src1_32 = cpu_cc_src;
402fcf5ef2aSThomas Huth     cc_src2_32 = cpu_cc_src2;
403fcf5ef2aSThomas Huth #endif
404fcf5ef2aSThomas Huth 
405fcf5ef2aSThomas Huth     carry_32 = tcg_temp_new_i32();
406fcf5ef2aSThomas Huth     tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
407fcf5ef2aSThomas Huth 
408fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
409fcf5ef2aSThomas Huth     tcg_temp_free_i32(cc_src1_32);
410fcf5ef2aSThomas Huth     tcg_temp_free_i32(cc_src2_32);
411fcf5ef2aSThomas Huth #endif
412fcf5ef2aSThomas Huth 
413fcf5ef2aSThomas Huth     return carry_32;
414fcf5ef2aSThomas Huth }
415fcf5ef2aSThomas Huth 
416fcf5ef2aSThomas Huth static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
417fcf5ef2aSThomas Huth                             TCGv src2, int update_cc)
418fcf5ef2aSThomas Huth {
419fcf5ef2aSThomas Huth     TCGv_i32 carry_32;
420fcf5ef2aSThomas Huth     TCGv carry;
421fcf5ef2aSThomas Huth 
422fcf5ef2aSThomas Huth     switch (dc->cc_op) {
423fcf5ef2aSThomas Huth     case CC_OP_DIV:
424fcf5ef2aSThomas Huth     case CC_OP_LOGIC:
425fcf5ef2aSThomas Huth         /* Carry is known to be zero.  Fall back to plain ADD.  */
426fcf5ef2aSThomas Huth         if (update_cc) {
427fcf5ef2aSThomas Huth             gen_op_add_cc(dst, src1, src2);
428fcf5ef2aSThomas Huth         } else {
429fcf5ef2aSThomas Huth             tcg_gen_add_tl(dst, src1, src2);
430fcf5ef2aSThomas Huth         }
431fcf5ef2aSThomas Huth         return;
432fcf5ef2aSThomas Huth 
433fcf5ef2aSThomas Huth     case CC_OP_ADD:
434fcf5ef2aSThomas Huth     case CC_OP_TADD:
435fcf5ef2aSThomas Huth     case CC_OP_TADDTV:
436fcf5ef2aSThomas Huth         if (TARGET_LONG_BITS == 32) {
437fcf5ef2aSThomas Huth             /* We can re-use the host's hardware carry generation by using
438fcf5ef2aSThomas Huth                an ADD2 opcode.  We discard the low part of the output.
439fcf5ef2aSThomas Huth                Ideally we'd combine this operation with the add that
440fcf5ef2aSThomas Huth                generated the carry in the first place.  */
441fcf5ef2aSThomas Huth             carry = tcg_temp_new();
442fcf5ef2aSThomas Huth             tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
443fcf5ef2aSThomas Huth             tcg_temp_free(carry);
444fcf5ef2aSThomas Huth             goto add_done;
445fcf5ef2aSThomas Huth         }
446fcf5ef2aSThomas Huth         carry_32 = gen_add32_carry32();
447fcf5ef2aSThomas Huth         break;
448fcf5ef2aSThomas Huth 
449fcf5ef2aSThomas Huth     case CC_OP_SUB:
450fcf5ef2aSThomas Huth     case CC_OP_TSUB:
451fcf5ef2aSThomas Huth     case CC_OP_TSUBTV:
452fcf5ef2aSThomas Huth         carry_32 = gen_sub32_carry32();
453fcf5ef2aSThomas Huth         break;
454fcf5ef2aSThomas Huth 
455fcf5ef2aSThomas Huth     default:
456fcf5ef2aSThomas Huth         /* We need external help to produce the carry.  */
457fcf5ef2aSThomas Huth         carry_32 = tcg_temp_new_i32();
458fcf5ef2aSThomas Huth         gen_helper_compute_C_icc(carry_32, cpu_env);
459fcf5ef2aSThomas Huth         break;
460fcf5ef2aSThomas Huth     }
461fcf5ef2aSThomas Huth 
462fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
463fcf5ef2aSThomas Huth     carry = tcg_temp_new();
464fcf5ef2aSThomas Huth     tcg_gen_extu_i32_i64(carry, carry_32);
465fcf5ef2aSThomas Huth #else
466fcf5ef2aSThomas Huth     carry = carry_32;
467fcf5ef2aSThomas Huth #endif
468fcf5ef2aSThomas Huth 
469fcf5ef2aSThomas Huth     tcg_gen_add_tl(dst, src1, src2);
470fcf5ef2aSThomas Huth     tcg_gen_add_tl(dst, dst, carry);
471fcf5ef2aSThomas Huth 
472fcf5ef2aSThomas Huth     tcg_temp_free_i32(carry_32);
473fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
474fcf5ef2aSThomas Huth     tcg_temp_free(carry);
475fcf5ef2aSThomas Huth #endif
476fcf5ef2aSThomas Huth 
477fcf5ef2aSThomas Huth  add_done:
478fcf5ef2aSThomas Huth     if (update_cc) {
479fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src, src1);
480fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src2, src2);
481fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_dst, dst);
482fcf5ef2aSThomas Huth         tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
483fcf5ef2aSThomas Huth         dc->cc_op = CC_OP_ADDX;
484fcf5ef2aSThomas Huth     }
485fcf5ef2aSThomas Huth }
486fcf5ef2aSThomas Huth 
487fcf5ef2aSThomas Huth static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
488fcf5ef2aSThomas Huth {
489fcf5ef2aSThomas Huth     tcg_gen_mov_tl(cpu_cc_src, src1);
490fcf5ef2aSThomas Huth     tcg_gen_mov_tl(cpu_cc_src2, src2);
491fcf5ef2aSThomas Huth     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
492fcf5ef2aSThomas Huth     tcg_gen_mov_tl(dst, cpu_cc_dst);
493fcf5ef2aSThomas Huth }
494fcf5ef2aSThomas Huth 
495fcf5ef2aSThomas Huth static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
496fcf5ef2aSThomas Huth                             TCGv src2, int update_cc)
497fcf5ef2aSThomas Huth {
498fcf5ef2aSThomas Huth     TCGv_i32 carry_32;
499fcf5ef2aSThomas Huth     TCGv carry;
500fcf5ef2aSThomas Huth 
501fcf5ef2aSThomas Huth     switch (dc->cc_op) {
502fcf5ef2aSThomas Huth     case CC_OP_DIV:
503fcf5ef2aSThomas Huth     case CC_OP_LOGIC:
504fcf5ef2aSThomas Huth         /* Carry is known to be zero.  Fall back to plain SUB.  */
505fcf5ef2aSThomas Huth         if (update_cc) {
506fcf5ef2aSThomas Huth             gen_op_sub_cc(dst, src1, src2);
507fcf5ef2aSThomas Huth         } else {
508fcf5ef2aSThomas Huth             tcg_gen_sub_tl(dst, src1, src2);
509fcf5ef2aSThomas Huth         }
510fcf5ef2aSThomas Huth         return;
511fcf5ef2aSThomas Huth 
512fcf5ef2aSThomas Huth     case CC_OP_ADD:
513fcf5ef2aSThomas Huth     case CC_OP_TADD:
514fcf5ef2aSThomas Huth     case CC_OP_TADDTV:
515fcf5ef2aSThomas Huth         carry_32 = gen_add32_carry32();
516fcf5ef2aSThomas Huth         break;
517fcf5ef2aSThomas Huth 
518fcf5ef2aSThomas Huth     case CC_OP_SUB:
519fcf5ef2aSThomas Huth     case CC_OP_TSUB:
520fcf5ef2aSThomas Huth     case CC_OP_TSUBTV:
521fcf5ef2aSThomas Huth         if (TARGET_LONG_BITS == 32) {
522fcf5ef2aSThomas Huth             /* We can re-use the host's hardware carry generation by using
523fcf5ef2aSThomas Huth                a SUB2 opcode.  We discard the low part of the output.
524fcf5ef2aSThomas Huth                Ideally we'd combine this operation with the add that
525fcf5ef2aSThomas Huth                generated the carry in the first place.  */
526fcf5ef2aSThomas Huth             carry = tcg_temp_new();
527fcf5ef2aSThomas Huth             tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
528fcf5ef2aSThomas Huth             tcg_temp_free(carry);
529fcf5ef2aSThomas Huth             goto sub_done;
530fcf5ef2aSThomas Huth         }
531fcf5ef2aSThomas Huth         carry_32 = gen_sub32_carry32();
532fcf5ef2aSThomas Huth         break;
533fcf5ef2aSThomas Huth 
534fcf5ef2aSThomas Huth     default:
535fcf5ef2aSThomas Huth         /* We need external help to produce the carry.  */
536fcf5ef2aSThomas Huth         carry_32 = tcg_temp_new_i32();
537fcf5ef2aSThomas Huth         gen_helper_compute_C_icc(carry_32, cpu_env);
538fcf5ef2aSThomas Huth         break;
539fcf5ef2aSThomas Huth     }
540fcf5ef2aSThomas Huth 
541fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
542fcf5ef2aSThomas Huth     carry = tcg_temp_new();
543fcf5ef2aSThomas Huth     tcg_gen_extu_i32_i64(carry, carry_32);
544fcf5ef2aSThomas Huth #else
545fcf5ef2aSThomas Huth     carry = carry_32;
546fcf5ef2aSThomas Huth #endif
547fcf5ef2aSThomas Huth 
548fcf5ef2aSThomas Huth     tcg_gen_sub_tl(dst, src1, src2);
549fcf5ef2aSThomas Huth     tcg_gen_sub_tl(dst, dst, carry);
550fcf5ef2aSThomas Huth 
551fcf5ef2aSThomas Huth     tcg_temp_free_i32(carry_32);
552fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 64
553fcf5ef2aSThomas Huth     tcg_temp_free(carry);
554fcf5ef2aSThomas Huth #endif
555fcf5ef2aSThomas Huth 
556fcf5ef2aSThomas Huth  sub_done:
557fcf5ef2aSThomas Huth     if (update_cc) {
558fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src, src1);
559fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src2, src2);
560fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_dst, dst);
561fcf5ef2aSThomas Huth         tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
562fcf5ef2aSThomas Huth         dc->cc_op = CC_OP_SUBX;
563fcf5ef2aSThomas Huth     }
564fcf5ef2aSThomas Huth }
565fcf5ef2aSThomas Huth 
566fcf5ef2aSThomas Huth static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
567fcf5ef2aSThomas Huth {
568fcf5ef2aSThomas Huth     TCGv r_temp, zero, t0;
569fcf5ef2aSThomas Huth 
570fcf5ef2aSThomas Huth     r_temp = tcg_temp_new();
571fcf5ef2aSThomas Huth     t0 = tcg_temp_new();
572fcf5ef2aSThomas Huth 
573fcf5ef2aSThomas Huth     /* old op:
574fcf5ef2aSThomas Huth     if (!(env->y & 1))
575fcf5ef2aSThomas Huth         T1 = 0;
576fcf5ef2aSThomas Huth     */
577fcf5ef2aSThomas Huth     zero = tcg_const_tl(0);
578fcf5ef2aSThomas Huth     tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
579fcf5ef2aSThomas Huth     tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
580fcf5ef2aSThomas Huth     tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
581fcf5ef2aSThomas Huth     tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
582fcf5ef2aSThomas Huth                        zero, cpu_cc_src2);
583fcf5ef2aSThomas Huth     tcg_temp_free(zero);
584fcf5ef2aSThomas Huth 
585fcf5ef2aSThomas Huth     // b2 = T0 & 1;
586fcf5ef2aSThomas Huth     // env->y = (b2 << 31) | (env->y >> 1);
5870b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(t0, cpu_y, 1, 31);
58808d64e0dSPhilippe Mathieu-Daudé     tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
589fcf5ef2aSThomas Huth 
590fcf5ef2aSThomas Huth     // b1 = N ^ V;
591fcf5ef2aSThomas Huth     gen_mov_reg_N(t0, cpu_psr);
592fcf5ef2aSThomas Huth     gen_mov_reg_V(r_temp, cpu_psr);
593fcf5ef2aSThomas Huth     tcg_gen_xor_tl(t0, t0, r_temp);
594fcf5ef2aSThomas Huth     tcg_temp_free(r_temp);
595fcf5ef2aSThomas Huth 
596fcf5ef2aSThomas Huth     // T0 = (b1 << 31) | (T0 >> 1);
597fcf5ef2aSThomas Huth     // src1 = T0;
598fcf5ef2aSThomas Huth     tcg_gen_shli_tl(t0, t0, 31);
599fcf5ef2aSThomas Huth     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
600fcf5ef2aSThomas Huth     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
601fcf5ef2aSThomas Huth     tcg_temp_free(t0);
602fcf5ef2aSThomas Huth 
603fcf5ef2aSThomas Huth     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
604fcf5ef2aSThomas Huth 
605fcf5ef2aSThomas Huth     tcg_gen_mov_tl(dst, cpu_cc_dst);
606fcf5ef2aSThomas Huth }
607fcf5ef2aSThomas Huth 
608fcf5ef2aSThomas Huth static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
609fcf5ef2aSThomas Huth {
610fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 32
611fcf5ef2aSThomas Huth     if (sign_ext) {
612fcf5ef2aSThomas Huth         tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
613fcf5ef2aSThomas Huth     } else {
614fcf5ef2aSThomas Huth         tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
615fcf5ef2aSThomas Huth     }
616fcf5ef2aSThomas Huth #else
617fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new_i64();
618fcf5ef2aSThomas Huth     TCGv t1 = tcg_temp_new_i64();
619fcf5ef2aSThomas Huth 
620fcf5ef2aSThomas Huth     if (sign_ext) {
621fcf5ef2aSThomas Huth         tcg_gen_ext32s_i64(t0, src1);
622fcf5ef2aSThomas Huth         tcg_gen_ext32s_i64(t1, src2);
623fcf5ef2aSThomas Huth     } else {
624fcf5ef2aSThomas Huth         tcg_gen_ext32u_i64(t0, src1);
625fcf5ef2aSThomas Huth         tcg_gen_ext32u_i64(t1, src2);
626fcf5ef2aSThomas Huth     }
627fcf5ef2aSThomas Huth 
628fcf5ef2aSThomas Huth     tcg_gen_mul_i64(dst, t0, t1);
629fcf5ef2aSThomas Huth     tcg_temp_free(t0);
630fcf5ef2aSThomas Huth     tcg_temp_free(t1);
631fcf5ef2aSThomas Huth 
632fcf5ef2aSThomas Huth     tcg_gen_shri_i64(cpu_y, dst, 32);
633fcf5ef2aSThomas Huth #endif
634fcf5ef2aSThomas Huth }
635fcf5ef2aSThomas Huth 
636fcf5ef2aSThomas Huth static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
637fcf5ef2aSThomas Huth {
638fcf5ef2aSThomas Huth     /* zero-extend truncated operands before multiplication */
639fcf5ef2aSThomas Huth     gen_op_multiply(dst, src1, src2, 0);
640fcf5ef2aSThomas Huth }
641fcf5ef2aSThomas Huth 
642fcf5ef2aSThomas Huth static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
643fcf5ef2aSThomas Huth {
644fcf5ef2aSThomas Huth     /* sign-extend truncated operands before multiplication */
645fcf5ef2aSThomas Huth     gen_op_multiply(dst, src1, src2, 1);
646fcf5ef2aSThomas Huth }
647fcf5ef2aSThomas Huth 
648fcf5ef2aSThomas Huth // 1
649fcf5ef2aSThomas Huth static inline void gen_op_eval_ba(TCGv dst)
650fcf5ef2aSThomas Huth {
651fcf5ef2aSThomas Huth     tcg_gen_movi_tl(dst, 1);
652fcf5ef2aSThomas Huth }
653fcf5ef2aSThomas Huth 
654fcf5ef2aSThomas Huth // Z
655fcf5ef2aSThomas Huth static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
656fcf5ef2aSThomas Huth {
657fcf5ef2aSThomas Huth     gen_mov_reg_Z(dst, src);
658fcf5ef2aSThomas Huth }
659fcf5ef2aSThomas Huth 
660fcf5ef2aSThomas Huth // Z | (N ^ V)
661fcf5ef2aSThomas Huth static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
662fcf5ef2aSThomas Huth {
663fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
664fcf5ef2aSThomas Huth     gen_mov_reg_N(t0, src);
665fcf5ef2aSThomas Huth     gen_mov_reg_V(dst, src);
666fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
667fcf5ef2aSThomas Huth     gen_mov_reg_Z(t0, src);
668fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
669fcf5ef2aSThomas Huth     tcg_temp_free(t0);
670fcf5ef2aSThomas Huth }
671fcf5ef2aSThomas Huth 
672fcf5ef2aSThomas Huth // N ^ V
673fcf5ef2aSThomas Huth static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
674fcf5ef2aSThomas Huth {
675fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
676fcf5ef2aSThomas Huth     gen_mov_reg_V(t0, src);
677fcf5ef2aSThomas Huth     gen_mov_reg_N(dst, src);
678fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
679fcf5ef2aSThomas Huth     tcg_temp_free(t0);
680fcf5ef2aSThomas Huth }
681fcf5ef2aSThomas Huth 
682fcf5ef2aSThomas Huth // C | Z
683fcf5ef2aSThomas Huth static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
684fcf5ef2aSThomas Huth {
685fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
686fcf5ef2aSThomas Huth     gen_mov_reg_Z(t0, src);
687fcf5ef2aSThomas Huth     gen_mov_reg_C(dst, src);
688fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
689fcf5ef2aSThomas Huth     tcg_temp_free(t0);
690fcf5ef2aSThomas Huth }
691fcf5ef2aSThomas Huth 
692fcf5ef2aSThomas Huth // C
693fcf5ef2aSThomas Huth static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
694fcf5ef2aSThomas Huth {
695fcf5ef2aSThomas Huth     gen_mov_reg_C(dst, src);
696fcf5ef2aSThomas Huth }
697fcf5ef2aSThomas Huth 
698fcf5ef2aSThomas Huth // V
699fcf5ef2aSThomas Huth static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
700fcf5ef2aSThomas Huth {
701fcf5ef2aSThomas Huth     gen_mov_reg_V(dst, src);
702fcf5ef2aSThomas Huth }
703fcf5ef2aSThomas Huth 
704fcf5ef2aSThomas Huth // 0
705fcf5ef2aSThomas Huth static inline void gen_op_eval_bn(TCGv dst)
706fcf5ef2aSThomas Huth {
707fcf5ef2aSThomas Huth     tcg_gen_movi_tl(dst, 0);
708fcf5ef2aSThomas Huth }
709fcf5ef2aSThomas Huth 
710fcf5ef2aSThomas Huth // N
711fcf5ef2aSThomas Huth static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
712fcf5ef2aSThomas Huth {
713fcf5ef2aSThomas Huth     gen_mov_reg_N(dst, src);
714fcf5ef2aSThomas Huth }
715fcf5ef2aSThomas Huth 
716fcf5ef2aSThomas Huth // !Z
717fcf5ef2aSThomas Huth static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
718fcf5ef2aSThomas Huth {
719fcf5ef2aSThomas Huth     gen_mov_reg_Z(dst, src);
720fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
721fcf5ef2aSThomas Huth }
722fcf5ef2aSThomas Huth 
723fcf5ef2aSThomas Huth // !(Z | (N ^ V))
724fcf5ef2aSThomas Huth static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
725fcf5ef2aSThomas Huth {
726fcf5ef2aSThomas Huth     gen_op_eval_ble(dst, src);
727fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
728fcf5ef2aSThomas Huth }
729fcf5ef2aSThomas Huth 
730fcf5ef2aSThomas Huth // !(N ^ V)
731fcf5ef2aSThomas Huth static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
732fcf5ef2aSThomas Huth {
733fcf5ef2aSThomas Huth     gen_op_eval_bl(dst, src);
734fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
735fcf5ef2aSThomas Huth }
736fcf5ef2aSThomas Huth 
737fcf5ef2aSThomas Huth // !(C | Z)
738fcf5ef2aSThomas Huth static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
739fcf5ef2aSThomas Huth {
740fcf5ef2aSThomas Huth     gen_op_eval_bleu(dst, src);
741fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
742fcf5ef2aSThomas Huth }
743fcf5ef2aSThomas Huth 
744fcf5ef2aSThomas Huth // !C
745fcf5ef2aSThomas Huth static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
746fcf5ef2aSThomas Huth {
747fcf5ef2aSThomas Huth     gen_mov_reg_C(dst, src);
748fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
749fcf5ef2aSThomas Huth }
750fcf5ef2aSThomas Huth 
751fcf5ef2aSThomas Huth // !N
752fcf5ef2aSThomas Huth static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
753fcf5ef2aSThomas Huth {
754fcf5ef2aSThomas Huth     gen_mov_reg_N(dst, src);
755fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
756fcf5ef2aSThomas Huth }
757fcf5ef2aSThomas Huth 
758fcf5ef2aSThomas Huth // !V
759fcf5ef2aSThomas Huth static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
760fcf5ef2aSThomas Huth {
761fcf5ef2aSThomas Huth     gen_mov_reg_V(dst, src);
762fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
763fcf5ef2aSThomas Huth }
764fcf5ef2aSThomas Huth 
765fcf5ef2aSThomas Huth /*
766fcf5ef2aSThomas Huth   FPSR bit field FCC1 | FCC0:
767fcf5ef2aSThomas Huth    0 =
768fcf5ef2aSThomas Huth    1 <
769fcf5ef2aSThomas Huth    2 >
770fcf5ef2aSThomas Huth    3 unordered
771fcf5ef2aSThomas Huth */
772fcf5ef2aSThomas Huth static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
773fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
774fcf5ef2aSThomas Huth {
775fcf5ef2aSThomas Huth     tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
776fcf5ef2aSThomas Huth     tcg_gen_andi_tl(reg, reg, 0x1);
777fcf5ef2aSThomas Huth }
778fcf5ef2aSThomas Huth 
779fcf5ef2aSThomas Huth static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
780fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
781fcf5ef2aSThomas Huth {
782fcf5ef2aSThomas Huth     tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
783fcf5ef2aSThomas Huth     tcg_gen_andi_tl(reg, reg, 0x1);
784fcf5ef2aSThomas Huth }
785fcf5ef2aSThomas Huth 
786fcf5ef2aSThomas Huth // !0: FCC0 | FCC1
787fcf5ef2aSThomas Huth static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
788fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
789fcf5ef2aSThomas Huth {
790fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
791fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
792fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
793fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
794fcf5ef2aSThomas Huth     tcg_temp_free(t0);
795fcf5ef2aSThomas Huth }
796fcf5ef2aSThomas Huth 
797fcf5ef2aSThomas Huth // 1 or 2: FCC0 ^ FCC1
798fcf5ef2aSThomas Huth static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
799fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
800fcf5ef2aSThomas Huth {
801fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
802fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
803fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
804fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
805fcf5ef2aSThomas Huth     tcg_temp_free(t0);
806fcf5ef2aSThomas Huth }
807fcf5ef2aSThomas Huth 
808fcf5ef2aSThomas Huth // 1 or 3: FCC0
809fcf5ef2aSThomas Huth static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
810fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
811fcf5ef2aSThomas Huth {
812fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
813fcf5ef2aSThomas Huth }
814fcf5ef2aSThomas Huth 
815fcf5ef2aSThomas Huth // 1: FCC0 & !FCC1
816fcf5ef2aSThomas Huth static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
817fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
818fcf5ef2aSThomas Huth {
819fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
820fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
821fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
822fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, dst, t0);
823fcf5ef2aSThomas Huth     tcg_temp_free(t0);
824fcf5ef2aSThomas Huth }
825fcf5ef2aSThomas Huth 
826fcf5ef2aSThomas Huth // 2 or 3: FCC1
827fcf5ef2aSThomas Huth static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
828fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
829fcf5ef2aSThomas Huth {
830fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(dst, src, fcc_offset);
831fcf5ef2aSThomas Huth }
832fcf5ef2aSThomas Huth 
833fcf5ef2aSThomas Huth // 2: !FCC0 & FCC1
834fcf5ef2aSThomas Huth static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
835fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
836fcf5ef2aSThomas Huth {
837fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
838fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
839fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
840fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, t0, dst);
841fcf5ef2aSThomas Huth     tcg_temp_free(t0);
842fcf5ef2aSThomas Huth }
843fcf5ef2aSThomas Huth 
844fcf5ef2aSThomas Huth // 3: FCC0 & FCC1
845fcf5ef2aSThomas Huth static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
846fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
847fcf5ef2aSThomas Huth {
848fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
849fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
850fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
851fcf5ef2aSThomas Huth     tcg_gen_and_tl(dst, dst, t0);
852fcf5ef2aSThomas Huth     tcg_temp_free(t0);
853fcf5ef2aSThomas Huth }
854fcf5ef2aSThomas Huth 
855fcf5ef2aSThomas Huth // 0: !(FCC0 | FCC1)
856fcf5ef2aSThomas Huth static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
857fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
858fcf5ef2aSThomas Huth {
859fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
860fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
861fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
862fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
863fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
864fcf5ef2aSThomas Huth     tcg_temp_free(t0);
865fcf5ef2aSThomas Huth }
866fcf5ef2aSThomas Huth 
867fcf5ef2aSThomas Huth // 0 or 3: !(FCC0 ^ FCC1)
868fcf5ef2aSThomas Huth static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
869fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
870fcf5ef2aSThomas Huth {
871fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
872fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
873fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
874fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
875fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
876fcf5ef2aSThomas Huth     tcg_temp_free(t0);
877fcf5ef2aSThomas Huth }
878fcf5ef2aSThomas Huth 
879fcf5ef2aSThomas Huth // 0 or 2: !FCC0
880fcf5ef2aSThomas Huth static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
881fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
882fcf5ef2aSThomas Huth {
883fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
884fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
885fcf5ef2aSThomas Huth }
886fcf5ef2aSThomas Huth 
887fcf5ef2aSThomas Huth // !1: !(FCC0 & !FCC1)
888fcf5ef2aSThomas Huth static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
889fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
890fcf5ef2aSThomas Huth {
891fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
892fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
893fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
894fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, dst, t0);
895fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
896fcf5ef2aSThomas Huth     tcg_temp_free(t0);
897fcf5ef2aSThomas Huth }
898fcf5ef2aSThomas Huth 
899fcf5ef2aSThomas Huth // 0 or 1: !FCC1
900fcf5ef2aSThomas Huth static inline void gen_op_eval_fble(TCGv dst, TCGv src,
901fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
902fcf5ef2aSThomas Huth {
903fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(dst, src, fcc_offset);
904fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
905fcf5ef2aSThomas Huth }
906fcf5ef2aSThomas Huth 
907fcf5ef2aSThomas Huth // !2: !(!FCC0 & FCC1)
908fcf5ef2aSThomas Huth static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
909fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
910fcf5ef2aSThomas Huth {
911fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
912fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
913fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
914fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, t0, dst);
915fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
916fcf5ef2aSThomas Huth     tcg_temp_free(t0);
917fcf5ef2aSThomas Huth }
918fcf5ef2aSThomas Huth 
919fcf5ef2aSThomas Huth // !3: !(FCC0 & FCC1)
920fcf5ef2aSThomas Huth static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
921fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
922fcf5ef2aSThomas Huth {
923fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
924fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
925fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
926fcf5ef2aSThomas Huth     tcg_gen_and_tl(dst, dst, t0);
927fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
928fcf5ef2aSThomas Huth     tcg_temp_free(t0);
929fcf5ef2aSThomas Huth }
930fcf5ef2aSThomas Huth 
931fcf5ef2aSThomas Huth static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
932fcf5ef2aSThomas Huth                                target_ulong pc2, TCGv r_cond)
933fcf5ef2aSThomas Huth {
934fcf5ef2aSThomas Huth     TCGLabel *l1 = gen_new_label();
935fcf5ef2aSThomas Huth 
936fcf5ef2aSThomas Huth     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
937fcf5ef2aSThomas Huth 
938fcf5ef2aSThomas Huth     gen_goto_tb(dc, 0, pc1, pc1 + 4);
939fcf5ef2aSThomas Huth 
940fcf5ef2aSThomas Huth     gen_set_label(l1);
941fcf5ef2aSThomas Huth     gen_goto_tb(dc, 1, pc2, pc2 + 4);
942fcf5ef2aSThomas Huth }
943fcf5ef2aSThomas Huth 
944fcf5ef2aSThomas Huth static void gen_branch_a(DisasContext *dc, target_ulong pc1)
945fcf5ef2aSThomas Huth {
946fcf5ef2aSThomas Huth     TCGLabel *l1 = gen_new_label();
947fcf5ef2aSThomas Huth     target_ulong npc = dc->npc;
948fcf5ef2aSThomas Huth 
949fcf5ef2aSThomas Huth     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
950fcf5ef2aSThomas Huth 
951fcf5ef2aSThomas Huth     gen_goto_tb(dc, 0, npc, pc1);
952fcf5ef2aSThomas Huth 
953fcf5ef2aSThomas Huth     gen_set_label(l1);
954fcf5ef2aSThomas Huth     gen_goto_tb(dc, 1, npc + 4, npc + 8);
955fcf5ef2aSThomas Huth 
956af00be49SEmilio G. Cota     dc->base.is_jmp = DISAS_NORETURN;
957fcf5ef2aSThomas Huth }
958fcf5ef2aSThomas Huth 
959fcf5ef2aSThomas Huth static void gen_branch_n(DisasContext *dc, target_ulong pc1)
960fcf5ef2aSThomas Huth {
961fcf5ef2aSThomas Huth     target_ulong npc = dc->npc;
962fcf5ef2aSThomas Huth 
963fcf5ef2aSThomas Huth     if (likely(npc != DYNAMIC_PC)) {
964fcf5ef2aSThomas Huth         dc->pc = npc;
965fcf5ef2aSThomas Huth         dc->jump_pc[0] = pc1;
966fcf5ef2aSThomas Huth         dc->jump_pc[1] = npc + 4;
967fcf5ef2aSThomas Huth         dc->npc = JUMP_PC;
968fcf5ef2aSThomas Huth     } else {
969fcf5ef2aSThomas Huth         TCGv t, z;
970fcf5ef2aSThomas Huth 
971fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_pc, cpu_npc);
972fcf5ef2aSThomas Huth 
973fcf5ef2aSThomas Huth         tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
974fcf5ef2aSThomas Huth         t = tcg_const_tl(pc1);
975fcf5ef2aSThomas Huth         z = tcg_const_tl(0);
976fcf5ef2aSThomas Huth         tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
977fcf5ef2aSThomas Huth         tcg_temp_free(t);
978fcf5ef2aSThomas Huth         tcg_temp_free(z);
979fcf5ef2aSThomas Huth 
980fcf5ef2aSThomas Huth         dc->pc = DYNAMIC_PC;
981fcf5ef2aSThomas Huth     }
982fcf5ef2aSThomas Huth }
983fcf5ef2aSThomas Huth 
984fcf5ef2aSThomas Huth static inline void gen_generic_branch(DisasContext *dc)
985fcf5ef2aSThomas Huth {
986fcf5ef2aSThomas Huth     TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
987fcf5ef2aSThomas Huth     TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
988fcf5ef2aSThomas Huth     TCGv zero = tcg_const_tl(0);
989fcf5ef2aSThomas Huth 
990fcf5ef2aSThomas Huth     tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
991fcf5ef2aSThomas Huth 
992fcf5ef2aSThomas Huth     tcg_temp_free(npc0);
993fcf5ef2aSThomas Huth     tcg_temp_free(npc1);
994fcf5ef2aSThomas Huth     tcg_temp_free(zero);
995fcf5ef2aSThomas Huth }
996fcf5ef2aSThomas Huth 
997fcf5ef2aSThomas Huth /* call this function before using the condition register as it may
998fcf5ef2aSThomas Huth    have been set for a jump */
999fcf5ef2aSThomas Huth static inline void flush_cond(DisasContext *dc)
1000fcf5ef2aSThomas Huth {
1001fcf5ef2aSThomas Huth     if (dc->npc == JUMP_PC) {
1002fcf5ef2aSThomas Huth         gen_generic_branch(dc);
1003fcf5ef2aSThomas Huth         dc->npc = DYNAMIC_PC;
1004fcf5ef2aSThomas Huth     }
1005fcf5ef2aSThomas Huth }
1006fcf5ef2aSThomas Huth 
1007fcf5ef2aSThomas Huth static inline void save_npc(DisasContext *dc)
1008fcf5ef2aSThomas Huth {
1009fcf5ef2aSThomas Huth     if (dc->npc == JUMP_PC) {
1010fcf5ef2aSThomas Huth         gen_generic_branch(dc);
1011fcf5ef2aSThomas Huth         dc->npc = DYNAMIC_PC;
1012fcf5ef2aSThomas Huth     } else if (dc->npc != DYNAMIC_PC) {
1013fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, dc->npc);
1014fcf5ef2aSThomas Huth     }
1015fcf5ef2aSThomas Huth }
1016fcf5ef2aSThomas Huth 
1017fcf5ef2aSThomas Huth static inline void update_psr(DisasContext *dc)
1018fcf5ef2aSThomas Huth {
1019fcf5ef2aSThomas Huth     if (dc->cc_op != CC_OP_FLAGS) {
1020fcf5ef2aSThomas Huth         dc->cc_op = CC_OP_FLAGS;
1021fcf5ef2aSThomas Huth         gen_helper_compute_psr(cpu_env);
1022fcf5ef2aSThomas Huth     }
1023fcf5ef2aSThomas Huth }
1024fcf5ef2aSThomas Huth 
1025fcf5ef2aSThomas Huth static inline void save_state(DisasContext *dc)
1026fcf5ef2aSThomas Huth {
1027fcf5ef2aSThomas Huth     tcg_gen_movi_tl(cpu_pc, dc->pc);
1028fcf5ef2aSThomas Huth     save_npc(dc);
1029fcf5ef2aSThomas Huth }
1030fcf5ef2aSThomas Huth 
1031fcf5ef2aSThomas Huth static void gen_exception(DisasContext *dc, int which)
1032fcf5ef2aSThomas Huth {
1033fcf5ef2aSThomas Huth     TCGv_i32 t;
1034fcf5ef2aSThomas Huth 
1035fcf5ef2aSThomas Huth     save_state(dc);
1036fcf5ef2aSThomas Huth     t = tcg_const_i32(which);
1037fcf5ef2aSThomas Huth     gen_helper_raise_exception(cpu_env, t);
1038fcf5ef2aSThomas Huth     tcg_temp_free_i32(t);
1039af00be49SEmilio G. Cota     dc->base.is_jmp = DISAS_NORETURN;
1040fcf5ef2aSThomas Huth }
1041fcf5ef2aSThomas Huth 
1042fcf5ef2aSThomas Huth static void gen_check_align(TCGv addr, int mask)
1043fcf5ef2aSThomas Huth {
1044fcf5ef2aSThomas Huth     TCGv_i32 r_mask = tcg_const_i32(mask);
1045fcf5ef2aSThomas Huth     gen_helper_check_align(cpu_env, addr, r_mask);
1046fcf5ef2aSThomas Huth     tcg_temp_free_i32(r_mask);
1047fcf5ef2aSThomas Huth }
1048fcf5ef2aSThomas Huth 
1049fcf5ef2aSThomas Huth static inline void gen_mov_pc_npc(DisasContext *dc)
1050fcf5ef2aSThomas Huth {
1051fcf5ef2aSThomas Huth     if (dc->npc == JUMP_PC) {
1052fcf5ef2aSThomas Huth         gen_generic_branch(dc);
1053fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1054fcf5ef2aSThomas Huth         dc->pc = DYNAMIC_PC;
1055fcf5ef2aSThomas Huth     } else if (dc->npc == DYNAMIC_PC) {
1056fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1057fcf5ef2aSThomas Huth         dc->pc = DYNAMIC_PC;
1058fcf5ef2aSThomas Huth     } else {
1059fcf5ef2aSThomas Huth         dc->pc = dc->npc;
1060fcf5ef2aSThomas Huth     }
1061fcf5ef2aSThomas Huth }
1062fcf5ef2aSThomas Huth 
1063fcf5ef2aSThomas Huth static inline void gen_op_next_insn(void)
1064fcf5ef2aSThomas Huth {
1065fcf5ef2aSThomas Huth     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1066fcf5ef2aSThomas Huth     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1067fcf5ef2aSThomas Huth }
1068fcf5ef2aSThomas Huth 
1069fcf5ef2aSThomas Huth static void free_compare(DisasCompare *cmp)
1070fcf5ef2aSThomas Huth {
1071fcf5ef2aSThomas Huth     if (!cmp->g1) {
1072fcf5ef2aSThomas Huth         tcg_temp_free(cmp->c1);
1073fcf5ef2aSThomas Huth     }
1074fcf5ef2aSThomas Huth     if (!cmp->g2) {
1075fcf5ef2aSThomas Huth         tcg_temp_free(cmp->c2);
1076fcf5ef2aSThomas Huth     }
1077fcf5ef2aSThomas Huth }
1078fcf5ef2aSThomas Huth 
1079fcf5ef2aSThomas Huth static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
1080fcf5ef2aSThomas Huth                         DisasContext *dc)
1081fcf5ef2aSThomas Huth {
1082fcf5ef2aSThomas Huth     static int subcc_cond[16] = {
1083fcf5ef2aSThomas Huth         TCG_COND_NEVER,
1084fcf5ef2aSThomas Huth         TCG_COND_EQ,
1085fcf5ef2aSThomas Huth         TCG_COND_LE,
1086fcf5ef2aSThomas Huth         TCG_COND_LT,
1087fcf5ef2aSThomas Huth         TCG_COND_LEU,
1088fcf5ef2aSThomas Huth         TCG_COND_LTU,
1089fcf5ef2aSThomas Huth         -1, /* neg */
1090fcf5ef2aSThomas Huth         -1, /* overflow */
1091fcf5ef2aSThomas Huth         TCG_COND_ALWAYS,
1092fcf5ef2aSThomas Huth         TCG_COND_NE,
1093fcf5ef2aSThomas Huth         TCG_COND_GT,
1094fcf5ef2aSThomas Huth         TCG_COND_GE,
1095fcf5ef2aSThomas Huth         TCG_COND_GTU,
1096fcf5ef2aSThomas Huth         TCG_COND_GEU,
1097fcf5ef2aSThomas Huth         -1, /* pos */
1098fcf5ef2aSThomas Huth         -1, /* no overflow */
1099fcf5ef2aSThomas Huth     };
1100fcf5ef2aSThomas Huth 
1101fcf5ef2aSThomas Huth     static int logic_cond[16] = {
1102fcf5ef2aSThomas Huth         TCG_COND_NEVER,
1103fcf5ef2aSThomas Huth         TCG_COND_EQ,     /* eq:  Z */
1104fcf5ef2aSThomas Huth         TCG_COND_LE,     /* le:  Z | (N ^ V) -> Z | N */
1105fcf5ef2aSThomas Huth         TCG_COND_LT,     /* lt:  N ^ V -> N */
1106fcf5ef2aSThomas Huth         TCG_COND_EQ,     /* leu: C | Z -> Z */
1107fcf5ef2aSThomas Huth         TCG_COND_NEVER,  /* ltu: C -> 0 */
1108fcf5ef2aSThomas Huth         TCG_COND_LT,     /* neg: N */
1109fcf5ef2aSThomas Huth         TCG_COND_NEVER,  /* vs:  V -> 0 */
1110fcf5ef2aSThomas Huth         TCG_COND_ALWAYS,
1111fcf5ef2aSThomas Huth         TCG_COND_NE,     /* ne:  !Z */
1112fcf5ef2aSThomas Huth         TCG_COND_GT,     /* gt:  !(Z | (N ^ V)) -> !(Z | N) */
1113fcf5ef2aSThomas Huth         TCG_COND_GE,     /* ge:  !(N ^ V) -> !N */
1114fcf5ef2aSThomas Huth         TCG_COND_NE,     /* gtu: !(C | Z) -> !Z */
1115fcf5ef2aSThomas Huth         TCG_COND_ALWAYS, /* geu: !C -> 1 */
1116fcf5ef2aSThomas Huth         TCG_COND_GE,     /* pos: !N */
1117fcf5ef2aSThomas Huth         TCG_COND_ALWAYS, /* vc:  !V -> 1 */
1118fcf5ef2aSThomas Huth     };
1119fcf5ef2aSThomas Huth 
1120fcf5ef2aSThomas Huth     TCGv_i32 r_src;
1121fcf5ef2aSThomas Huth     TCGv r_dst;
1122fcf5ef2aSThomas Huth 
1123fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1124fcf5ef2aSThomas Huth     if (xcc) {
1125fcf5ef2aSThomas Huth         r_src = cpu_xcc;
1126fcf5ef2aSThomas Huth     } else {
1127fcf5ef2aSThomas Huth         r_src = cpu_psr;
1128fcf5ef2aSThomas Huth     }
1129fcf5ef2aSThomas Huth #else
1130fcf5ef2aSThomas Huth     r_src = cpu_psr;
1131fcf5ef2aSThomas Huth #endif
1132fcf5ef2aSThomas Huth 
1133fcf5ef2aSThomas Huth     switch (dc->cc_op) {
1134fcf5ef2aSThomas Huth     case CC_OP_LOGIC:
1135fcf5ef2aSThomas Huth         cmp->cond = logic_cond[cond];
1136fcf5ef2aSThomas Huth     do_compare_dst_0:
1137fcf5ef2aSThomas Huth         cmp->is_bool = false;
1138fcf5ef2aSThomas Huth         cmp->g2 = false;
1139fcf5ef2aSThomas Huth         cmp->c2 = tcg_const_tl(0);
1140fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1141fcf5ef2aSThomas Huth         if (!xcc) {
1142fcf5ef2aSThomas Huth             cmp->g1 = false;
1143fcf5ef2aSThomas Huth             cmp->c1 = tcg_temp_new();
1144fcf5ef2aSThomas Huth             tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1145fcf5ef2aSThomas Huth             break;
1146fcf5ef2aSThomas Huth         }
1147fcf5ef2aSThomas Huth #endif
1148fcf5ef2aSThomas Huth         cmp->g1 = true;
1149fcf5ef2aSThomas Huth         cmp->c1 = cpu_cc_dst;
1150fcf5ef2aSThomas Huth         break;
1151fcf5ef2aSThomas Huth 
1152fcf5ef2aSThomas Huth     case CC_OP_SUB:
1153fcf5ef2aSThomas Huth         switch (cond) {
1154fcf5ef2aSThomas Huth         case 6:  /* neg */
1155fcf5ef2aSThomas Huth         case 14: /* pos */
1156fcf5ef2aSThomas Huth             cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
1157fcf5ef2aSThomas Huth             goto do_compare_dst_0;
1158fcf5ef2aSThomas Huth 
1159fcf5ef2aSThomas Huth         case 7: /* overflow */
1160fcf5ef2aSThomas Huth         case 15: /* !overflow */
1161fcf5ef2aSThomas Huth             goto do_dynamic;
1162fcf5ef2aSThomas Huth 
1163fcf5ef2aSThomas Huth         default:
1164fcf5ef2aSThomas Huth             cmp->cond = subcc_cond[cond];
1165fcf5ef2aSThomas Huth             cmp->is_bool = false;
1166fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1167fcf5ef2aSThomas Huth             if (!xcc) {
1168fcf5ef2aSThomas Huth                 /* Note that sign-extension works for unsigned compares as
1169fcf5ef2aSThomas Huth                    long as both operands are sign-extended.  */
1170fcf5ef2aSThomas Huth                 cmp->g1 = cmp->g2 = false;
1171fcf5ef2aSThomas Huth                 cmp->c1 = tcg_temp_new();
1172fcf5ef2aSThomas Huth                 cmp->c2 = tcg_temp_new();
1173fcf5ef2aSThomas Huth                 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1174fcf5ef2aSThomas Huth                 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
1175fcf5ef2aSThomas Huth                 break;
1176fcf5ef2aSThomas Huth             }
1177fcf5ef2aSThomas Huth #endif
1178fcf5ef2aSThomas Huth             cmp->g1 = cmp->g2 = true;
1179fcf5ef2aSThomas Huth             cmp->c1 = cpu_cc_src;
1180fcf5ef2aSThomas Huth             cmp->c2 = cpu_cc_src2;
1181fcf5ef2aSThomas Huth             break;
1182fcf5ef2aSThomas Huth         }
1183fcf5ef2aSThomas Huth         break;
1184fcf5ef2aSThomas Huth 
1185fcf5ef2aSThomas Huth     default:
1186fcf5ef2aSThomas Huth     do_dynamic:
1187fcf5ef2aSThomas Huth         gen_helper_compute_psr(cpu_env);
1188fcf5ef2aSThomas Huth         dc->cc_op = CC_OP_FLAGS;
1189fcf5ef2aSThomas Huth         /* FALLTHRU */
1190fcf5ef2aSThomas Huth 
1191fcf5ef2aSThomas Huth     case CC_OP_FLAGS:
1192fcf5ef2aSThomas Huth         /* We're going to generate a boolean result.  */
1193fcf5ef2aSThomas Huth         cmp->cond = TCG_COND_NE;
1194fcf5ef2aSThomas Huth         cmp->is_bool = true;
1195fcf5ef2aSThomas Huth         cmp->g1 = cmp->g2 = false;
1196fcf5ef2aSThomas Huth         cmp->c1 = r_dst = tcg_temp_new();
1197fcf5ef2aSThomas Huth         cmp->c2 = tcg_const_tl(0);
1198fcf5ef2aSThomas Huth 
1199fcf5ef2aSThomas Huth         switch (cond) {
1200fcf5ef2aSThomas Huth         case 0x0:
1201fcf5ef2aSThomas Huth             gen_op_eval_bn(r_dst);
1202fcf5ef2aSThomas Huth             break;
1203fcf5ef2aSThomas Huth         case 0x1:
1204fcf5ef2aSThomas Huth             gen_op_eval_be(r_dst, r_src);
1205fcf5ef2aSThomas Huth             break;
1206fcf5ef2aSThomas Huth         case 0x2:
1207fcf5ef2aSThomas Huth             gen_op_eval_ble(r_dst, r_src);
1208fcf5ef2aSThomas Huth             break;
1209fcf5ef2aSThomas Huth         case 0x3:
1210fcf5ef2aSThomas Huth             gen_op_eval_bl(r_dst, r_src);
1211fcf5ef2aSThomas Huth             break;
1212fcf5ef2aSThomas Huth         case 0x4:
1213fcf5ef2aSThomas Huth             gen_op_eval_bleu(r_dst, r_src);
1214fcf5ef2aSThomas Huth             break;
1215fcf5ef2aSThomas Huth         case 0x5:
1216fcf5ef2aSThomas Huth             gen_op_eval_bcs(r_dst, r_src);
1217fcf5ef2aSThomas Huth             break;
1218fcf5ef2aSThomas Huth         case 0x6:
1219fcf5ef2aSThomas Huth             gen_op_eval_bneg(r_dst, r_src);
1220fcf5ef2aSThomas Huth             break;
1221fcf5ef2aSThomas Huth         case 0x7:
1222fcf5ef2aSThomas Huth             gen_op_eval_bvs(r_dst, r_src);
1223fcf5ef2aSThomas Huth             break;
1224fcf5ef2aSThomas Huth         case 0x8:
1225fcf5ef2aSThomas Huth             gen_op_eval_ba(r_dst);
1226fcf5ef2aSThomas Huth             break;
1227fcf5ef2aSThomas Huth         case 0x9:
1228fcf5ef2aSThomas Huth             gen_op_eval_bne(r_dst, r_src);
1229fcf5ef2aSThomas Huth             break;
1230fcf5ef2aSThomas Huth         case 0xa:
1231fcf5ef2aSThomas Huth             gen_op_eval_bg(r_dst, r_src);
1232fcf5ef2aSThomas Huth             break;
1233fcf5ef2aSThomas Huth         case 0xb:
1234fcf5ef2aSThomas Huth             gen_op_eval_bge(r_dst, r_src);
1235fcf5ef2aSThomas Huth             break;
1236fcf5ef2aSThomas Huth         case 0xc:
1237fcf5ef2aSThomas Huth             gen_op_eval_bgu(r_dst, r_src);
1238fcf5ef2aSThomas Huth             break;
1239fcf5ef2aSThomas Huth         case 0xd:
1240fcf5ef2aSThomas Huth             gen_op_eval_bcc(r_dst, r_src);
1241fcf5ef2aSThomas Huth             break;
1242fcf5ef2aSThomas Huth         case 0xe:
1243fcf5ef2aSThomas Huth             gen_op_eval_bpos(r_dst, r_src);
1244fcf5ef2aSThomas Huth             break;
1245fcf5ef2aSThomas Huth         case 0xf:
1246fcf5ef2aSThomas Huth             gen_op_eval_bvc(r_dst, r_src);
1247fcf5ef2aSThomas Huth             break;
1248fcf5ef2aSThomas Huth         }
1249fcf5ef2aSThomas Huth         break;
1250fcf5ef2aSThomas Huth     }
1251fcf5ef2aSThomas Huth }
1252fcf5ef2aSThomas Huth 
1253fcf5ef2aSThomas Huth static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
1254fcf5ef2aSThomas Huth {
1255fcf5ef2aSThomas Huth     unsigned int offset;
1256fcf5ef2aSThomas Huth     TCGv r_dst;
1257fcf5ef2aSThomas Huth 
1258fcf5ef2aSThomas Huth     /* For now we still generate a straight boolean result.  */
1259fcf5ef2aSThomas Huth     cmp->cond = TCG_COND_NE;
1260fcf5ef2aSThomas Huth     cmp->is_bool = true;
1261fcf5ef2aSThomas Huth     cmp->g1 = cmp->g2 = false;
1262fcf5ef2aSThomas Huth     cmp->c1 = r_dst = tcg_temp_new();
1263fcf5ef2aSThomas Huth     cmp->c2 = tcg_const_tl(0);
1264fcf5ef2aSThomas Huth 
1265fcf5ef2aSThomas Huth     switch (cc) {
1266fcf5ef2aSThomas Huth     default:
1267fcf5ef2aSThomas Huth     case 0x0:
1268fcf5ef2aSThomas Huth         offset = 0;
1269fcf5ef2aSThomas Huth         break;
1270fcf5ef2aSThomas Huth     case 0x1:
1271fcf5ef2aSThomas Huth         offset = 32 - 10;
1272fcf5ef2aSThomas Huth         break;
1273fcf5ef2aSThomas Huth     case 0x2:
1274fcf5ef2aSThomas Huth         offset = 34 - 10;
1275fcf5ef2aSThomas Huth         break;
1276fcf5ef2aSThomas Huth     case 0x3:
1277fcf5ef2aSThomas Huth         offset = 36 - 10;
1278fcf5ef2aSThomas Huth         break;
1279fcf5ef2aSThomas Huth     }
1280fcf5ef2aSThomas Huth 
1281fcf5ef2aSThomas Huth     switch (cond) {
1282fcf5ef2aSThomas Huth     case 0x0:
1283fcf5ef2aSThomas Huth         gen_op_eval_bn(r_dst);
1284fcf5ef2aSThomas Huth         break;
1285fcf5ef2aSThomas Huth     case 0x1:
1286fcf5ef2aSThomas Huth         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1287fcf5ef2aSThomas Huth         break;
1288fcf5ef2aSThomas Huth     case 0x2:
1289fcf5ef2aSThomas Huth         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1290fcf5ef2aSThomas Huth         break;
1291fcf5ef2aSThomas Huth     case 0x3:
1292fcf5ef2aSThomas Huth         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1293fcf5ef2aSThomas Huth         break;
1294fcf5ef2aSThomas Huth     case 0x4:
1295fcf5ef2aSThomas Huth         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1296fcf5ef2aSThomas Huth         break;
1297fcf5ef2aSThomas Huth     case 0x5:
1298fcf5ef2aSThomas Huth         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1299fcf5ef2aSThomas Huth         break;
1300fcf5ef2aSThomas Huth     case 0x6:
1301fcf5ef2aSThomas Huth         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1302fcf5ef2aSThomas Huth         break;
1303fcf5ef2aSThomas Huth     case 0x7:
1304fcf5ef2aSThomas Huth         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1305fcf5ef2aSThomas Huth         break;
1306fcf5ef2aSThomas Huth     case 0x8:
1307fcf5ef2aSThomas Huth         gen_op_eval_ba(r_dst);
1308fcf5ef2aSThomas Huth         break;
1309fcf5ef2aSThomas Huth     case 0x9:
1310fcf5ef2aSThomas Huth         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1311fcf5ef2aSThomas Huth         break;
1312fcf5ef2aSThomas Huth     case 0xa:
1313fcf5ef2aSThomas Huth         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1314fcf5ef2aSThomas Huth         break;
1315fcf5ef2aSThomas Huth     case 0xb:
1316fcf5ef2aSThomas Huth         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1317fcf5ef2aSThomas Huth         break;
1318fcf5ef2aSThomas Huth     case 0xc:
1319fcf5ef2aSThomas Huth         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1320fcf5ef2aSThomas Huth         break;
1321fcf5ef2aSThomas Huth     case 0xd:
1322fcf5ef2aSThomas Huth         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1323fcf5ef2aSThomas Huth         break;
1324fcf5ef2aSThomas Huth     case 0xe:
1325fcf5ef2aSThomas Huth         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1326fcf5ef2aSThomas Huth         break;
1327fcf5ef2aSThomas Huth     case 0xf:
1328fcf5ef2aSThomas Huth         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1329fcf5ef2aSThomas Huth         break;
1330fcf5ef2aSThomas Huth     }
1331fcf5ef2aSThomas Huth }
1332fcf5ef2aSThomas Huth 
1333fcf5ef2aSThomas Huth static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1334fcf5ef2aSThomas Huth                      DisasContext *dc)
1335fcf5ef2aSThomas Huth {
1336fcf5ef2aSThomas Huth     DisasCompare cmp;
1337fcf5ef2aSThomas Huth     gen_compare(&cmp, cc, cond, dc);
1338fcf5ef2aSThomas Huth 
1339fcf5ef2aSThomas Huth     /* The interface is to return a boolean in r_dst.  */
1340fcf5ef2aSThomas Huth     if (cmp.is_bool) {
1341fcf5ef2aSThomas Huth         tcg_gen_mov_tl(r_dst, cmp.c1);
1342fcf5ef2aSThomas Huth     } else {
1343fcf5ef2aSThomas Huth         tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1344fcf5ef2aSThomas Huth     }
1345fcf5ef2aSThomas Huth 
1346fcf5ef2aSThomas Huth     free_compare(&cmp);
1347fcf5ef2aSThomas Huth }
1348fcf5ef2aSThomas Huth 
1349fcf5ef2aSThomas Huth static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1350fcf5ef2aSThomas Huth {
1351fcf5ef2aSThomas Huth     DisasCompare cmp;
1352fcf5ef2aSThomas Huth     gen_fcompare(&cmp, cc, cond);
1353fcf5ef2aSThomas Huth 
1354fcf5ef2aSThomas Huth     /* The interface is to return a boolean in r_dst.  */
1355fcf5ef2aSThomas Huth     if (cmp.is_bool) {
1356fcf5ef2aSThomas Huth         tcg_gen_mov_tl(r_dst, cmp.c1);
1357fcf5ef2aSThomas Huth     } else {
1358fcf5ef2aSThomas Huth         tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1359fcf5ef2aSThomas Huth     }
1360fcf5ef2aSThomas Huth 
1361fcf5ef2aSThomas Huth     free_compare(&cmp);
1362fcf5ef2aSThomas Huth }
1363fcf5ef2aSThomas Huth 
1364fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1365fcf5ef2aSThomas Huth // Inverted logic
1366fcf5ef2aSThomas Huth static const int gen_tcg_cond_reg[8] = {
1367fcf5ef2aSThomas Huth     -1,
1368fcf5ef2aSThomas Huth     TCG_COND_NE,
1369fcf5ef2aSThomas Huth     TCG_COND_GT,
1370fcf5ef2aSThomas Huth     TCG_COND_GE,
1371fcf5ef2aSThomas Huth     -1,
1372fcf5ef2aSThomas Huth     TCG_COND_EQ,
1373fcf5ef2aSThomas Huth     TCG_COND_LE,
1374fcf5ef2aSThomas Huth     TCG_COND_LT,
1375fcf5ef2aSThomas Huth };
1376fcf5ef2aSThomas Huth 
1377fcf5ef2aSThomas Huth static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1378fcf5ef2aSThomas Huth {
1379fcf5ef2aSThomas Huth     cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1380fcf5ef2aSThomas Huth     cmp->is_bool = false;
1381fcf5ef2aSThomas Huth     cmp->g1 = true;
1382fcf5ef2aSThomas Huth     cmp->g2 = false;
1383fcf5ef2aSThomas Huth     cmp->c1 = r_src;
1384fcf5ef2aSThomas Huth     cmp->c2 = tcg_const_tl(0);
1385fcf5ef2aSThomas Huth }
1386fcf5ef2aSThomas Huth 
1387fcf5ef2aSThomas Huth static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1388fcf5ef2aSThomas Huth {
1389fcf5ef2aSThomas Huth     DisasCompare cmp;
1390fcf5ef2aSThomas Huth     gen_compare_reg(&cmp, cond, r_src);
1391fcf5ef2aSThomas Huth 
1392fcf5ef2aSThomas Huth     /* The interface is to return a boolean in r_dst.  */
1393fcf5ef2aSThomas Huth     tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1394fcf5ef2aSThomas Huth 
1395fcf5ef2aSThomas Huth     free_compare(&cmp);
1396fcf5ef2aSThomas Huth }
1397fcf5ef2aSThomas Huth #endif
1398fcf5ef2aSThomas Huth 
1399fcf5ef2aSThomas Huth static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
1400fcf5ef2aSThomas Huth {
1401fcf5ef2aSThomas Huth     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1402fcf5ef2aSThomas Huth     target_ulong target = dc->pc + offset;
1403fcf5ef2aSThomas Huth 
1404fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1405fcf5ef2aSThomas Huth     if (unlikely(AM_CHECK(dc))) {
1406fcf5ef2aSThomas Huth         target &= 0xffffffffULL;
1407fcf5ef2aSThomas Huth     }
1408fcf5ef2aSThomas Huth #endif
1409fcf5ef2aSThomas Huth     if (cond == 0x0) {
1410fcf5ef2aSThomas Huth         /* unconditional not taken */
1411fcf5ef2aSThomas Huth         if (a) {
1412fcf5ef2aSThomas Huth             dc->pc = dc->npc + 4;
1413fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1414fcf5ef2aSThomas Huth         } else {
1415fcf5ef2aSThomas Huth             dc->pc = dc->npc;
1416fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1417fcf5ef2aSThomas Huth         }
1418fcf5ef2aSThomas Huth     } else if (cond == 0x8) {
1419fcf5ef2aSThomas Huth         /* unconditional taken */
1420fcf5ef2aSThomas Huth         if (a) {
1421fcf5ef2aSThomas Huth             dc->pc = target;
1422fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1423fcf5ef2aSThomas Huth         } else {
1424fcf5ef2aSThomas Huth             dc->pc = dc->npc;
1425fcf5ef2aSThomas Huth             dc->npc = target;
1426fcf5ef2aSThomas Huth             tcg_gen_mov_tl(cpu_pc, cpu_npc);
1427fcf5ef2aSThomas Huth         }
1428fcf5ef2aSThomas Huth     } else {
1429fcf5ef2aSThomas Huth         flush_cond(dc);
1430fcf5ef2aSThomas Huth         gen_cond(cpu_cond, cc, cond, dc);
1431fcf5ef2aSThomas Huth         if (a) {
1432fcf5ef2aSThomas Huth             gen_branch_a(dc, target);
1433fcf5ef2aSThomas Huth         } else {
1434fcf5ef2aSThomas Huth             gen_branch_n(dc, target);
1435fcf5ef2aSThomas Huth         }
1436fcf5ef2aSThomas Huth     }
1437fcf5ef2aSThomas Huth }
1438fcf5ef2aSThomas Huth 
1439fcf5ef2aSThomas Huth static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
1440fcf5ef2aSThomas Huth {
1441fcf5ef2aSThomas Huth     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1442fcf5ef2aSThomas Huth     target_ulong target = dc->pc + offset;
1443fcf5ef2aSThomas Huth 
1444fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1445fcf5ef2aSThomas Huth     if (unlikely(AM_CHECK(dc))) {
1446fcf5ef2aSThomas Huth         target &= 0xffffffffULL;
1447fcf5ef2aSThomas Huth     }
1448fcf5ef2aSThomas Huth #endif
1449fcf5ef2aSThomas Huth     if (cond == 0x0) {
1450fcf5ef2aSThomas Huth         /* unconditional not taken */
1451fcf5ef2aSThomas Huth         if (a) {
1452fcf5ef2aSThomas Huth             dc->pc = dc->npc + 4;
1453fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1454fcf5ef2aSThomas Huth         } else {
1455fcf5ef2aSThomas Huth             dc->pc = dc->npc;
1456fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1457fcf5ef2aSThomas Huth         }
1458fcf5ef2aSThomas Huth     } else if (cond == 0x8) {
1459fcf5ef2aSThomas Huth         /* unconditional taken */
1460fcf5ef2aSThomas Huth         if (a) {
1461fcf5ef2aSThomas Huth             dc->pc = target;
1462fcf5ef2aSThomas Huth             dc->npc = dc->pc + 4;
1463fcf5ef2aSThomas Huth         } else {
1464fcf5ef2aSThomas Huth             dc->pc = dc->npc;
1465fcf5ef2aSThomas Huth             dc->npc = target;
1466fcf5ef2aSThomas Huth             tcg_gen_mov_tl(cpu_pc, cpu_npc);
1467fcf5ef2aSThomas Huth         }
1468fcf5ef2aSThomas Huth     } else {
1469fcf5ef2aSThomas Huth         flush_cond(dc);
1470fcf5ef2aSThomas Huth         gen_fcond(cpu_cond, cc, cond);
1471fcf5ef2aSThomas Huth         if (a) {
1472fcf5ef2aSThomas Huth             gen_branch_a(dc, target);
1473fcf5ef2aSThomas Huth         } else {
1474fcf5ef2aSThomas Huth             gen_branch_n(dc, target);
1475fcf5ef2aSThomas Huth         }
1476fcf5ef2aSThomas Huth     }
1477fcf5ef2aSThomas Huth }
1478fcf5ef2aSThomas Huth 
1479fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1480fcf5ef2aSThomas Huth static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1481fcf5ef2aSThomas Huth                           TCGv r_reg)
1482fcf5ef2aSThomas Huth {
1483fcf5ef2aSThomas Huth     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1484fcf5ef2aSThomas Huth     target_ulong target = dc->pc + offset;
1485fcf5ef2aSThomas Huth 
1486fcf5ef2aSThomas Huth     if (unlikely(AM_CHECK(dc))) {
1487fcf5ef2aSThomas Huth         target &= 0xffffffffULL;
1488fcf5ef2aSThomas Huth     }
1489fcf5ef2aSThomas Huth     flush_cond(dc);
1490fcf5ef2aSThomas Huth     gen_cond_reg(cpu_cond, cond, r_reg);
1491fcf5ef2aSThomas Huth     if (a) {
1492fcf5ef2aSThomas Huth         gen_branch_a(dc, target);
1493fcf5ef2aSThomas Huth     } else {
1494fcf5ef2aSThomas Huth         gen_branch_n(dc, target);
1495fcf5ef2aSThomas Huth     }
1496fcf5ef2aSThomas Huth }
1497fcf5ef2aSThomas Huth 
1498fcf5ef2aSThomas Huth static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1499fcf5ef2aSThomas Huth {
1500fcf5ef2aSThomas Huth     switch (fccno) {
1501fcf5ef2aSThomas Huth     case 0:
1502fcf5ef2aSThomas Huth         gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
1503fcf5ef2aSThomas Huth         break;
1504fcf5ef2aSThomas Huth     case 1:
1505fcf5ef2aSThomas Huth         gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
1506fcf5ef2aSThomas Huth         break;
1507fcf5ef2aSThomas Huth     case 2:
1508fcf5ef2aSThomas Huth         gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
1509fcf5ef2aSThomas Huth         break;
1510fcf5ef2aSThomas Huth     case 3:
1511fcf5ef2aSThomas Huth         gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
1512fcf5ef2aSThomas Huth         break;
1513fcf5ef2aSThomas Huth     }
1514fcf5ef2aSThomas Huth }
1515fcf5ef2aSThomas Huth 
1516fcf5ef2aSThomas Huth static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1517fcf5ef2aSThomas Huth {
1518fcf5ef2aSThomas Huth     switch (fccno) {
1519fcf5ef2aSThomas Huth     case 0:
1520fcf5ef2aSThomas Huth         gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
1521fcf5ef2aSThomas Huth         break;
1522fcf5ef2aSThomas Huth     case 1:
1523fcf5ef2aSThomas Huth         gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
1524fcf5ef2aSThomas Huth         break;
1525fcf5ef2aSThomas Huth     case 2:
1526fcf5ef2aSThomas Huth         gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
1527fcf5ef2aSThomas Huth         break;
1528fcf5ef2aSThomas Huth     case 3:
1529fcf5ef2aSThomas Huth         gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
1530fcf5ef2aSThomas Huth         break;
1531fcf5ef2aSThomas Huth     }
1532fcf5ef2aSThomas Huth }
1533fcf5ef2aSThomas Huth 
1534fcf5ef2aSThomas Huth static inline void gen_op_fcmpq(int fccno)
1535fcf5ef2aSThomas Huth {
1536fcf5ef2aSThomas Huth     switch (fccno) {
1537fcf5ef2aSThomas Huth     case 0:
1538fcf5ef2aSThomas Huth         gen_helper_fcmpq(cpu_fsr, cpu_env);
1539fcf5ef2aSThomas Huth         break;
1540fcf5ef2aSThomas Huth     case 1:
1541fcf5ef2aSThomas Huth         gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
1542fcf5ef2aSThomas Huth         break;
1543fcf5ef2aSThomas Huth     case 2:
1544fcf5ef2aSThomas Huth         gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
1545fcf5ef2aSThomas Huth         break;
1546fcf5ef2aSThomas Huth     case 3:
1547fcf5ef2aSThomas Huth         gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
1548fcf5ef2aSThomas Huth         break;
1549fcf5ef2aSThomas Huth     }
1550fcf5ef2aSThomas Huth }
1551fcf5ef2aSThomas Huth 
1552fcf5ef2aSThomas Huth static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1553fcf5ef2aSThomas Huth {
1554fcf5ef2aSThomas Huth     switch (fccno) {
1555fcf5ef2aSThomas Huth     case 0:
1556fcf5ef2aSThomas Huth         gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
1557fcf5ef2aSThomas Huth         break;
1558fcf5ef2aSThomas Huth     case 1:
1559fcf5ef2aSThomas Huth         gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
1560fcf5ef2aSThomas Huth         break;
1561fcf5ef2aSThomas Huth     case 2:
1562fcf5ef2aSThomas Huth         gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
1563fcf5ef2aSThomas Huth         break;
1564fcf5ef2aSThomas Huth     case 3:
1565fcf5ef2aSThomas Huth         gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
1566fcf5ef2aSThomas Huth         break;
1567fcf5ef2aSThomas Huth     }
1568fcf5ef2aSThomas Huth }
1569fcf5ef2aSThomas Huth 
1570fcf5ef2aSThomas Huth static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1571fcf5ef2aSThomas Huth {
1572fcf5ef2aSThomas Huth     switch (fccno) {
1573fcf5ef2aSThomas Huth     case 0:
1574fcf5ef2aSThomas Huth         gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
1575fcf5ef2aSThomas Huth         break;
1576fcf5ef2aSThomas Huth     case 1:
1577fcf5ef2aSThomas Huth         gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
1578fcf5ef2aSThomas Huth         break;
1579fcf5ef2aSThomas Huth     case 2:
1580fcf5ef2aSThomas Huth         gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
1581fcf5ef2aSThomas Huth         break;
1582fcf5ef2aSThomas Huth     case 3:
1583fcf5ef2aSThomas Huth         gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
1584fcf5ef2aSThomas Huth         break;
1585fcf5ef2aSThomas Huth     }
1586fcf5ef2aSThomas Huth }
1587fcf5ef2aSThomas Huth 
1588fcf5ef2aSThomas Huth static inline void gen_op_fcmpeq(int fccno)
1589fcf5ef2aSThomas Huth {
1590fcf5ef2aSThomas Huth     switch (fccno) {
1591fcf5ef2aSThomas Huth     case 0:
1592fcf5ef2aSThomas Huth         gen_helper_fcmpeq(cpu_fsr, cpu_env);
1593fcf5ef2aSThomas Huth         break;
1594fcf5ef2aSThomas Huth     case 1:
1595fcf5ef2aSThomas Huth         gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
1596fcf5ef2aSThomas Huth         break;
1597fcf5ef2aSThomas Huth     case 2:
1598fcf5ef2aSThomas Huth         gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
1599fcf5ef2aSThomas Huth         break;
1600fcf5ef2aSThomas Huth     case 3:
1601fcf5ef2aSThomas Huth         gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
1602fcf5ef2aSThomas Huth         break;
1603fcf5ef2aSThomas Huth     }
1604fcf5ef2aSThomas Huth }
1605fcf5ef2aSThomas Huth 
1606fcf5ef2aSThomas Huth #else
1607fcf5ef2aSThomas Huth 
1608fcf5ef2aSThomas Huth static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1609fcf5ef2aSThomas Huth {
1610fcf5ef2aSThomas Huth     gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
1611fcf5ef2aSThomas Huth }
1612fcf5ef2aSThomas Huth 
1613fcf5ef2aSThomas Huth static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1614fcf5ef2aSThomas Huth {
1615fcf5ef2aSThomas Huth     gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
1616fcf5ef2aSThomas Huth }
1617fcf5ef2aSThomas Huth 
1618fcf5ef2aSThomas Huth static inline void gen_op_fcmpq(int fccno)
1619fcf5ef2aSThomas Huth {
1620fcf5ef2aSThomas Huth     gen_helper_fcmpq(cpu_fsr, cpu_env);
1621fcf5ef2aSThomas Huth }
1622fcf5ef2aSThomas Huth 
1623fcf5ef2aSThomas Huth static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1624fcf5ef2aSThomas Huth {
1625fcf5ef2aSThomas Huth     gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
1626fcf5ef2aSThomas Huth }
1627fcf5ef2aSThomas Huth 
1628fcf5ef2aSThomas Huth static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1629fcf5ef2aSThomas Huth {
1630fcf5ef2aSThomas Huth     gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
1631fcf5ef2aSThomas Huth }
1632fcf5ef2aSThomas Huth 
1633fcf5ef2aSThomas Huth static inline void gen_op_fcmpeq(int fccno)
1634fcf5ef2aSThomas Huth {
1635fcf5ef2aSThomas Huth     gen_helper_fcmpeq(cpu_fsr, cpu_env);
1636fcf5ef2aSThomas Huth }
1637fcf5ef2aSThomas Huth #endif
1638fcf5ef2aSThomas Huth 
1639fcf5ef2aSThomas Huth static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
1640fcf5ef2aSThomas Huth {
1641fcf5ef2aSThomas Huth     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1642fcf5ef2aSThomas Huth     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1643fcf5ef2aSThomas Huth     gen_exception(dc, TT_FP_EXCP);
1644fcf5ef2aSThomas Huth }
1645fcf5ef2aSThomas Huth 
1646fcf5ef2aSThomas Huth static int gen_trap_ifnofpu(DisasContext *dc)
1647fcf5ef2aSThomas Huth {
1648fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
1649fcf5ef2aSThomas Huth     if (!dc->fpu_enabled) {
1650fcf5ef2aSThomas Huth         gen_exception(dc, TT_NFPU_INSN);
1651fcf5ef2aSThomas Huth         return 1;
1652fcf5ef2aSThomas Huth     }
1653fcf5ef2aSThomas Huth #endif
1654fcf5ef2aSThomas Huth     return 0;
1655fcf5ef2aSThomas Huth }
1656fcf5ef2aSThomas Huth 
1657fcf5ef2aSThomas Huth static inline void gen_op_clear_ieee_excp_and_FTT(void)
1658fcf5ef2aSThomas Huth {
1659fcf5ef2aSThomas Huth     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1660fcf5ef2aSThomas Huth }
1661fcf5ef2aSThomas Huth 
1662fcf5ef2aSThomas Huth static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1663fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1664fcf5ef2aSThomas Huth {
1665fcf5ef2aSThomas Huth     TCGv_i32 dst, src;
1666fcf5ef2aSThomas Huth 
1667fcf5ef2aSThomas Huth     src = gen_load_fpr_F(dc, rs);
1668fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1669fcf5ef2aSThomas Huth 
1670fcf5ef2aSThomas Huth     gen(dst, cpu_env, src);
1671fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1672fcf5ef2aSThomas Huth 
1673fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1674fcf5ef2aSThomas Huth }
1675fcf5ef2aSThomas Huth 
1676fcf5ef2aSThomas Huth static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1677fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_i32, TCGv_i32))
1678fcf5ef2aSThomas Huth {
1679fcf5ef2aSThomas Huth     TCGv_i32 dst, src;
1680fcf5ef2aSThomas Huth 
1681fcf5ef2aSThomas Huth     src = gen_load_fpr_F(dc, rs);
1682fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1683fcf5ef2aSThomas Huth 
1684fcf5ef2aSThomas Huth     gen(dst, src);
1685fcf5ef2aSThomas Huth 
1686fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1687fcf5ef2aSThomas Huth }
1688fcf5ef2aSThomas Huth 
1689fcf5ef2aSThomas Huth static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1690fcf5ef2aSThomas Huth                         void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1691fcf5ef2aSThomas Huth {
1692fcf5ef2aSThomas Huth     TCGv_i32 dst, src1, src2;
1693fcf5ef2aSThomas Huth 
1694fcf5ef2aSThomas Huth     src1 = gen_load_fpr_F(dc, rs1);
1695fcf5ef2aSThomas Huth     src2 = gen_load_fpr_F(dc, rs2);
1696fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1697fcf5ef2aSThomas Huth 
1698fcf5ef2aSThomas Huth     gen(dst, cpu_env, src1, src2);
1699fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1700fcf5ef2aSThomas Huth 
1701fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1702fcf5ef2aSThomas Huth }
1703fcf5ef2aSThomas Huth 
1704fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1705fcf5ef2aSThomas Huth static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1706fcf5ef2aSThomas Huth                                   void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1707fcf5ef2aSThomas Huth {
1708fcf5ef2aSThomas Huth     TCGv_i32 dst, src1, src2;
1709fcf5ef2aSThomas Huth 
1710fcf5ef2aSThomas Huth     src1 = gen_load_fpr_F(dc, rs1);
1711fcf5ef2aSThomas Huth     src2 = gen_load_fpr_F(dc, rs2);
1712fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1713fcf5ef2aSThomas Huth 
1714fcf5ef2aSThomas Huth     gen(dst, src1, src2);
1715fcf5ef2aSThomas Huth 
1716fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1717fcf5ef2aSThomas Huth }
1718fcf5ef2aSThomas Huth #endif
1719fcf5ef2aSThomas Huth 
1720fcf5ef2aSThomas Huth static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1721fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1722fcf5ef2aSThomas Huth {
1723fcf5ef2aSThomas Huth     TCGv_i64 dst, src;
1724fcf5ef2aSThomas Huth 
1725fcf5ef2aSThomas Huth     src = gen_load_fpr_D(dc, rs);
1726fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1727fcf5ef2aSThomas Huth 
1728fcf5ef2aSThomas Huth     gen(dst, cpu_env, src);
1729fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1730fcf5ef2aSThomas Huth 
1731fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1732fcf5ef2aSThomas Huth }
1733fcf5ef2aSThomas Huth 
1734fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1735fcf5ef2aSThomas Huth static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1736fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_i64, TCGv_i64))
1737fcf5ef2aSThomas Huth {
1738fcf5ef2aSThomas Huth     TCGv_i64 dst, src;
1739fcf5ef2aSThomas Huth 
1740fcf5ef2aSThomas Huth     src = gen_load_fpr_D(dc, rs);
1741fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1742fcf5ef2aSThomas Huth 
1743fcf5ef2aSThomas Huth     gen(dst, src);
1744fcf5ef2aSThomas Huth 
1745fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1746fcf5ef2aSThomas Huth }
1747fcf5ef2aSThomas Huth #endif
1748fcf5ef2aSThomas Huth 
1749fcf5ef2aSThomas Huth static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1750fcf5ef2aSThomas Huth                         void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1751fcf5ef2aSThomas Huth {
1752fcf5ef2aSThomas Huth     TCGv_i64 dst, src1, src2;
1753fcf5ef2aSThomas Huth 
1754fcf5ef2aSThomas Huth     src1 = gen_load_fpr_D(dc, rs1);
1755fcf5ef2aSThomas Huth     src2 = gen_load_fpr_D(dc, rs2);
1756fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1757fcf5ef2aSThomas Huth 
1758fcf5ef2aSThomas Huth     gen(dst, cpu_env, src1, src2);
1759fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1760fcf5ef2aSThomas Huth 
1761fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1762fcf5ef2aSThomas Huth }
1763fcf5ef2aSThomas Huth 
1764fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1765fcf5ef2aSThomas Huth static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1766fcf5ef2aSThomas Huth                                   void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1767fcf5ef2aSThomas Huth {
1768fcf5ef2aSThomas Huth     TCGv_i64 dst, src1, src2;
1769fcf5ef2aSThomas Huth 
1770fcf5ef2aSThomas Huth     src1 = gen_load_fpr_D(dc, rs1);
1771fcf5ef2aSThomas Huth     src2 = gen_load_fpr_D(dc, rs2);
1772fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1773fcf5ef2aSThomas Huth 
1774fcf5ef2aSThomas Huth     gen(dst, src1, src2);
1775fcf5ef2aSThomas Huth 
1776fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1777fcf5ef2aSThomas Huth }
1778fcf5ef2aSThomas Huth 
1779fcf5ef2aSThomas Huth static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1780fcf5ef2aSThomas Huth                            void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1781fcf5ef2aSThomas Huth {
1782fcf5ef2aSThomas Huth     TCGv_i64 dst, src1, src2;
1783fcf5ef2aSThomas Huth 
1784fcf5ef2aSThomas Huth     src1 = gen_load_fpr_D(dc, rs1);
1785fcf5ef2aSThomas Huth     src2 = gen_load_fpr_D(dc, rs2);
1786fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1787fcf5ef2aSThomas Huth 
1788fcf5ef2aSThomas Huth     gen(dst, cpu_gsr, src1, src2);
1789fcf5ef2aSThomas Huth 
1790fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1791fcf5ef2aSThomas Huth }
1792fcf5ef2aSThomas Huth 
1793fcf5ef2aSThomas Huth static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1794fcf5ef2aSThomas Huth                            void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1795fcf5ef2aSThomas Huth {
1796fcf5ef2aSThomas Huth     TCGv_i64 dst, src0, src1, src2;
1797fcf5ef2aSThomas Huth 
1798fcf5ef2aSThomas Huth     src1 = gen_load_fpr_D(dc, rs1);
1799fcf5ef2aSThomas Huth     src2 = gen_load_fpr_D(dc, rs2);
1800fcf5ef2aSThomas Huth     src0 = gen_load_fpr_D(dc, rd);
1801fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1802fcf5ef2aSThomas Huth 
1803fcf5ef2aSThomas Huth     gen(dst, src0, src1, src2);
1804fcf5ef2aSThomas Huth 
1805fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1806fcf5ef2aSThomas Huth }
1807fcf5ef2aSThomas Huth #endif
1808fcf5ef2aSThomas Huth 
1809fcf5ef2aSThomas Huth static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1810fcf5ef2aSThomas Huth                               void (*gen)(TCGv_ptr))
1811fcf5ef2aSThomas Huth {
1812fcf5ef2aSThomas Huth     gen_op_load_fpr_QT1(QFPREG(rs));
1813fcf5ef2aSThomas Huth 
1814fcf5ef2aSThomas Huth     gen(cpu_env);
1815fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1816fcf5ef2aSThomas Huth 
1817fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1818fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1819fcf5ef2aSThomas Huth }
1820fcf5ef2aSThomas Huth 
1821fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1822fcf5ef2aSThomas Huth static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1823fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_ptr))
1824fcf5ef2aSThomas Huth {
1825fcf5ef2aSThomas Huth     gen_op_load_fpr_QT1(QFPREG(rs));
1826fcf5ef2aSThomas Huth 
1827fcf5ef2aSThomas Huth     gen(cpu_env);
1828fcf5ef2aSThomas Huth 
1829fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1830fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1831fcf5ef2aSThomas Huth }
1832fcf5ef2aSThomas Huth #endif
1833fcf5ef2aSThomas Huth 
1834fcf5ef2aSThomas Huth static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1835fcf5ef2aSThomas Huth                                void (*gen)(TCGv_ptr))
1836fcf5ef2aSThomas Huth {
1837fcf5ef2aSThomas Huth     gen_op_load_fpr_QT0(QFPREG(rs1));
1838fcf5ef2aSThomas Huth     gen_op_load_fpr_QT1(QFPREG(rs2));
1839fcf5ef2aSThomas Huth 
1840fcf5ef2aSThomas Huth     gen(cpu_env);
1841fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1842fcf5ef2aSThomas Huth 
1843fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1844fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1845fcf5ef2aSThomas Huth }
1846fcf5ef2aSThomas Huth 
1847fcf5ef2aSThomas Huth static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1848fcf5ef2aSThomas Huth                         void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1849fcf5ef2aSThomas Huth {
1850fcf5ef2aSThomas Huth     TCGv_i64 dst;
1851fcf5ef2aSThomas Huth     TCGv_i32 src1, src2;
1852fcf5ef2aSThomas Huth 
1853fcf5ef2aSThomas Huth     src1 = gen_load_fpr_F(dc, rs1);
1854fcf5ef2aSThomas Huth     src2 = gen_load_fpr_F(dc, rs2);
1855fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1856fcf5ef2aSThomas Huth 
1857fcf5ef2aSThomas Huth     gen(dst, cpu_env, src1, src2);
1858fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1859fcf5ef2aSThomas Huth 
1860fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1861fcf5ef2aSThomas Huth }
1862fcf5ef2aSThomas Huth 
1863fcf5ef2aSThomas Huth static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1864fcf5ef2aSThomas Huth                                void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1865fcf5ef2aSThomas Huth {
1866fcf5ef2aSThomas Huth     TCGv_i64 src1, src2;
1867fcf5ef2aSThomas Huth 
1868fcf5ef2aSThomas Huth     src1 = gen_load_fpr_D(dc, rs1);
1869fcf5ef2aSThomas Huth     src2 = gen_load_fpr_D(dc, rs2);
1870fcf5ef2aSThomas Huth 
1871fcf5ef2aSThomas Huth     gen(cpu_env, src1, src2);
1872fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1873fcf5ef2aSThomas Huth 
1874fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1875fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1876fcf5ef2aSThomas Huth }
1877fcf5ef2aSThomas Huth 
1878fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1879fcf5ef2aSThomas Huth static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1880fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1881fcf5ef2aSThomas Huth {
1882fcf5ef2aSThomas Huth     TCGv_i64 dst;
1883fcf5ef2aSThomas Huth     TCGv_i32 src;
1884fcf5ef2aSThomas Huth 
1885fcf5ef2aSThomas Huth     src = gen_load_fpr_F(dc, rs);
1886fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1887fcf5ef2aSThomas Huth 
1888fcf5ef2aSThomas Huth     gen(dst, cpu_env, src);
1889fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1890fcf5ef2aSThomas Huth 
1891fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1892fcf5ef2aSThomas Huth }
1893fcf5ef2aSThomas Huth #endif
1894fcf5ef2aSThomas Huth 
1895fcf5ef2aSThomas Huth static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1896fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1897fcf5ef2aSThomas Huth {
1898fcf5ef2aSThomas Huth     TCGv_i64 dst;
1899fcf5ef2aSThomas Huth     TCGv_i32 src;
1900fcf5ef2aSThomas Huth 
1901fcf5ef2aSThomas Huth     src = gen_load_fpr_F(dc, rs);
1902fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1903fcf5ef2aSThomas Huth 
1904fcf5ef2aSThomas Huth     gen(dst, cpu_env, src);
1905fcf5ef2aSThomas Huth 
1906fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1907fcf5ef2aSThomas Huth }
1908fcf5ef2aSThomas Huth 
1909fcf5ef2aSThomas Huth static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1910fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1911fcf5ef2aSThomas Huth {
1912fcf5ef2aSThomas Huth     TCGv_i32 dst;
1913fcf5ef2aSThomas Huth     TCGv_i64 src;
1914fcf5ef2aSThomas Huth 
1915fcf5ef2aSThomas Huth     src = gen_load_fpr_D(dc, rs);
1916fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1917fcf5ef2aSThomas Huth 
1918fcf5ef2aSThomas Huth     gen(dst, cpu_env, src);
1919fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1920fcf5ef2aSThomas Huth 
1921fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1922fcf5ef2aSThomas Huth }
1923fcf5ef2aSThomas Huth 
1924fcf5ef2aSThomas Huth static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1925fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i32, TCGv_ptr))
1926fcf5ef2aSThomas Huth {
1927fcf5ef2aSThomas Huth     TCGv_i32 dst;
1928fcf5ef2aSThomas Huth 
1929fcf5ef2aSThomas Huth     gen_op_load_fpr_QT1(QFPREG(rs));
1930fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
1931fcf5ef2aSThomas Huth 
1932fcf5ef2aSThomas Huth     gen(dst, cpu_env);
1933fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1934fcf5ef2aSThomas Huth 
1935fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
1936fcf5ef2aSThomas Huth }
1937fcf5ef2aSThomas Huth 
1938fcf5ef2aSThomas Huth static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1939fcf5ef2aSThomas Huth                               void (*gen)(TCGv_i64, TCGv_ptr))
1940fcf5ef2aSThomas Huth {
1941fcf5ef2aSThomas Huth     TCGv_i64 dst;
1942fcf5ef2aSThomas Huth 
1943fcf5ef2aSThomas Huth     gen_op_load_fpr_QT1(QFPREG(rs));
1944fcf5ef2aSThomas Huth     dst = gen_dest_fpr_D(dc, rd);
1945fcf5ef2aSThomas Huth 
1946fcf5ef2aSThomas Huth     gen(dst, cpu_env);
1947fcf5ef2aSThomas Huth     gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
1948fcf5ef2aSThomas Huth 
1949fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
1950fcf5ef2aSThomas Huth }
1951fcf5ef2aSThomas Huth 
1952fcf5ef2aSThomas Huth static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1953fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_ptr, TCGv_i32))
1954fcf5ef2aSThomas Huth {
1955fcf5ef2aSThomas Huth     TCGv_i32 src;
1956fcf5ef2aSThomas Huth 
1957fcf5ef2aSThomas Huth     src = gen_load_fpr_F(dc, rs);
1958fcf5ef2aSThomas Huth 
1959fcf5ef2aSThomas Huth     gen(cpu_env, src);
1960fcf5ef2aSThomas Huth 
1961fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1962fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1963fcf5ef2aSThomas Huth }
1964fcf5ef2aSThomas Huth 
1965fcf5ef2aSThomas Huth static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1966fcf5ef2aSThomas Huth                                  void (*gen)(TCGv_ptr, TCGv_i64))
1967fcf5ef2aSThomas Huth {
1968fcf5ef2aSThomas Huth     TCGv_i64 src;
1969fcf5ef2aSThomas Huth 
1970fcf5ef2aSThomas Huth     src = gen_load_fpr_D(dc, rs);
1971fcf5ef2aSThomas Huth 
1972fcf5ef2aSThomas Huth     gen(cpu_env, src);
1973fcf5ef2aSThomas Huth 
1974fcf5ef2aSThomas Huth     gen_op_store_QT0_fpr(QFPREG(rd));
1975fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, QFPREG(rd));
1976fcf5ef2aSThomas Huth }
1977fcf5ef2aSThomas Huth 
1978fcf5ef2aSThomas Huth static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
197914776ab5STony Nguyen                      TCGv addr, int mmu_idx, MemOp memop)
1980fcf5ef2aSThomas Huth {
1981fcf5ef2aSThomas Huth     gen_address_mask(dc, addr);
1982fcf5ef2aSThomas Huth     tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
1983fcf5ef2aSThomas Huth }
1984fcf5ef2aSThomas Huth 
1985fcf5ef2aSThomas Huth static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
1986fcf5ef2aSThomas Huth {
1987fcf5ef2aSThomas Huth     TCGv m1 = tcg_const_tl(0xff);
1988fcf5ef2aSThomas Huth     gen_address_mask(dc, addr);
1989fcf5ef2aSThomas Huth     tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
1990fcf5ef2aSThomas Huth     tcg_temp_free(m1);
1991fcf5ef2aSThomas Huth }
1992fcf5ef2aSThomas Huth 
1993fcf5ef2aSThomas Huth /* asi moves */
1994fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1995fcf5ef2aSThomas Huth typedef enum {
1996fcf5ef2aSThomas Huth     GET_ASI_HELPER,
1997fcf5ef2aSThomas Huth     GET_ASI_EXCP,
1998fcf5ef2aSThomas Huth     GET_ASI_DIRECT,
1999fcf5ef2aSThomas Huth     GET_ASI_DTWINX,
2000fcf5ef2aSThomas Huth     GET_ASI_BLOCK,
2001fcf5ef2aSThomas Huth     GET_ASI_SHORT,
2002fcf5ef2aSThomas Huth     GET_ASI_BCOPY,
2003fcf5ef2aSThomas Huth     GET_ASI_BFILL,
2004fcf5ef2aSThomas Huth } ASIType;
2005fcf5ef2aSThomas Huth 
2006fcf5ef2aSThomas Huth typedef struct {
2007fcf5ef2aSThomas Huth     ASIType type;
2008fcf5ef2aSThomas Huth     int asi;
2009fcf5ef2aSThomas Huth     int mem_idx;
201014776ab5STony Nguyen     MemOp memop;
2011fcf5ef2aSThomas Huth } DisasASI;
2012fcf5ef2aSThomas Huth 
201314776ab5STony Nguyen static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
2014fcf5ef2aSThomas Huth {
2015fcf5ef2aSThomas Huth     int asi = GET_FIELD(insn, 19, 26);
2016fcf5ef2aSThomas Huth     ASIType type = GET_ASI_HELPER;
2017fcf5ef2aSThomas Huth     int mem_idx = dc->mem_idx;
2018fcf5ef2aSThomas Huth 
2019fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
2020fcf5ef2aSThomas Huth     /* Before v9, all asis are immediate and privileged.  */
2021fcf5ef2aSThomas Huth     if (IS_IMM) {
2022fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
2023fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
2024fcf5ef2aSThomas Huth     } else if (supervisor(dc)
2025fcf5ef2aSThomas Huth                /* Note that LEON accepts ASI_USERDATA in user mode, for
2026fcf5ef2aSThomas Huth                   use with CASA.  Also note that previous versions of
2027fcf5ef2aSThomas Huth                   QEMU allowed (and old versions of gcc emitted) ASI_P
2028fcf5ef2aSThomas Huth                   for LEON, which is incorrect.  */
2029fcf5ef2aSThomas Huth                || (asi == ASI_USERDATA
2030fcf5ef2aSThomas Huth                    && (dc->def->features & CPU_FEATURE_CASA))) {
2031fcf5ef2aSThomas Huth         switch (asi) {
2032fcf5ef2aSThomas Huth         case ASI_USERDATA:   /* User data access */
2033fcf5ef2aSThomas Huth             mem_idx = MMU_USER_IDX;
2034fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
2035fcf5ef2aSThomas Huth             break;
2036fcf5ef2aSThomas Huth         case ASI_KERNELDATA: /* Supervisor data access */
2037fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
2038fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
2039fcf5ef2aSThomas Huth             break;
2040fcf5ef2aSThomas Huth         case ASI_M_BYPASS:    /* MMU passthrough */
2041fcf5ef2aSThomas Huth         case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2042fcf5ef2aSThomas Huth             mem_idx = MMU_PHYS_IDX;
2043fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
2044fcf5ef2aSThomas Huth             break;
2045fcf5ef2aSThomas Huth         case ASI_M_BCOPY: /* Block copy, sta access */
2046fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
2047fcf5ef2aSThomas Huth             type = GET_ASI_BCOPY;
2048fcf5ef2aSThomas Huth             break;
2049fcf5ef2aSThomas Huth         case ASI_M_BFILL: /* Block fill, stda access */
2050fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
2051fcf5ef2aSThomas Huth             type = GET_ASI_BFILL;
2052fcf5ef2aSThomas Huth             break;
2053fcf5ef2aSThomas Huth         }
20546e10f37cSKONRAD Frederic 
20556e10f37cSKONRAD Frederic         /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
20566e10f37cSKONRAD Frederic          * permissions check in get_physical_address(..).
20576e10f37cSKONRAD Frederic          */
20586e10f37cSKONRAD Frederic         mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx;
2059fcf5ef2aSThomas Huth     } else {
2060fcf5ef2aSThomas Huth         gen_exception(dc, TT_PRIV_INSN);
2061fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
2062fcf5ef2aSThomas Huth     }
2063fcf5ef2aSThomas Huth #else
2064fcf5ef2aSThomas Huth     if (IS_IMM) {
2065fcf5ef2aSThomas Huth         asi = dc->asi;
2066fcf5ef2aSThomas Huth     }
2067fcf5ef2aSThomas Huth     /* With v9, all asis below 0x80 are privileged.  */
2068fcf5ef2aSThomas Huth     /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2069fcf5ef2aSThomas Huth        down that bit into DisasContext.  For the moment that's ok,
2070fcf5ef2aSThomas Huth        since the direct implementations below doesn't have any ASIs
2071fcf5ef2aSThomas Huth        in the restricted [0x30, 0x7f] range, and the check will be
2072fcf5ef2aSThomas Huth        done properly in the helper.  */
2073fcf5ef2aSThomas Huth     if (!supervisor(dc) && asi < 0x80) {
2074fcf5ef2aSThomas Huth         gen_exception(dc, TT_PRIV_ACT);
2075fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
2076fcf5ef2aSThomas Huth     } else {
2077fcf5ef2aSThomas Huth         switch (asi) {
2078fcf5ef2aSThomas Huth         case ASI_REAL:      /* Bypass */
2079fcf5ef2aSThomas Huth         case ASI_REAL_IO:   /* Bypass, non-cacheable */
2080fcf5ef2aSThomas Huth         case ASI_REAL_L:    /* Bypass LE */
2081fcf5ef2aSThomas Huth         case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2082fcf5ef2aSThomas Huth         case ASI_TWINX_REAL:   /* Real address, twinx */
2083fcf5ef2aSThomas Huth         case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
2084fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS:
2085fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS_L:
2086fcf5ef2aSThomas Huth             mem_idx = MMU_PHYS_IDX;
2087fcf5ef2aSThomas Huth             break;
2088fcf5ef2aSThomas Huth         case ASI_N:  /* Nucleus */
2089fcf5ef2aSThomas Huth         case ASI_NL: /* Nucleus LE */
2090fcf5ef2aSThomas Huth         case ASI_TWINX_N:
2091fcf5ef2aSThomas Huth         case ASI_TWINX_NL:
2092fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD:
2093fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD_L:
20949a10756dSArtyom Tarasenko             if (hypervisor(dc)) {
209584f8f587SArtyom Tarasenko                 mem_idx = MMU_PHYS_IDX;
20969a10756dSArtyom Tarasenko             } else {
2097fcf5ef2aSThomas Huth                 mem_idx = MMU_NUCLEUS_IDX;
20989a10756dSArtyom Tarasenko             }
2099fcf5ef2aSThomas Huth             break;
2100fcf5ef2aSThomas Huth         case ASI_AIUP:  /* As if user primary */
2101fcf5ef2aSThomas Huth         case ASI_AIUPL: /* As if user primary LE */
2102fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP:
2103fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP_L:
2104fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_4V:
2105fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_L_4V:
2106fcf5ef2aSThomas Huth         case ASI_BLK_AIUP:
2107fcf5ef2aSThomas Huth         case ASI_BLK_AIUPL:
2108fcf5ef2aSThomas Huth             mem_idx = MMU_USER_IDX;
2109fcf5ef2aSThomas Huth             break;
2110fcf5ef2aSThomas Huth         case ASI_AIUS:  /* As if user secondary */
2111fcf5ef2aSThomas Huth         case ASI_AIUSL: /* As if user secondary LE */
2112fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS:
2113fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS_L:
2114fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_4V:
2115fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_L_4V:
2116fcf5ef2aSThomas Huth         case ASI_BLK_AIUS:
2117fcf5ef2aSThomas Huth         case ASI_BLK_AIUSL:
2118fcf5ef2aSThomas Huth             mem_idx = MMU_USER_SECONDARY_IDX;
2119fcf5ef2aSThomas Huth             break;
2120fcf5ef2aSThomas Huth         case ASI_S:  /* Secondary */
2121fcf5ef2aSThomas Huth         case ASI_SL: /* Secondary LE */
2122fcf5ef2aSThomas Huth         case ASI_TWINX_S:
2123fcf5ef2aSThomas Huth         case ASI_TWINX_SL:
2124fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_S:
2125fcf5ef2aSThomas Huth         case ASI_BLK_S:
2126fcf5ef2aSThomas Huth         case ASI_BLK_SL:
2127fcf5ef2aSThomas Huth         case ASI_FL8_S:
2128fcf5ef2aSThomas Huth         case ASI_FL8_SL:
2129fcf5ef2aSThomas Huth         case ASI_FL16_S:
2130fcf5ef2aSThomas Huth         case ASI_FL16_SL:
2131fcf5ef2aSThomas Huth             if (mem_idx == MMU_USER_IDX) {
2132fcf5ef2aSThomas Huth                 mem_idx = MMU_USER_SECONDARY_IDX;
2133fcf5ef2aSThomas Huth             } else if (mem_idx == MMU_KERNEL_IDX) {
2134fcf5ef2aSThomas Huth                 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2135fcf5ef2aSThomas Huth             }
2136fcf5ef2aSThomas Huth             break;
2137fcf5ef2aSThomas Huth         case ASI_P:  /* Primary */
2138fcf5ef2aSThomas Huth         case ASI_PL: /* Primary LE */
2139fcf5ef2aSThomas Huth         case ASI_TWINX_P:
2140fcf5ef2aSThomas Huth         case ASI_TWINX_PL:
2141fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_P:
2142fcf5ef2aSThomas Huth         case ASI_BLK_P:
2143fcf5ef2aSThomas Huth         case ASI_BLK_PL:
2144fcf5ef2aSThomas Huth         case ASI_FL8_P:
2145fcf5ef2aSThomas Huth         case ASI_FL8_PL:
2146fcf5ef2aSThomas Huth         case ASI_FL16_P:
2147fcf5ef2aSThomas Huth         case ASI_FL16_PL:
2148fcf5ef2aSThomas Huth             break;
2149fcf5ef2aSThomas Huth         }
2150fcf5ef2aSThomas Huth         switch (asi) {
2151fcf5ef2aSThomas Huth         case ASI_REAL:
2152fcf5ef2aSThomas Huth         case ASI_REAL_IO:
2153fcf5ef2aSThomas Huth         case ASI_REAL_L:
2154fcf5ef2aSThomas Huth         case ASI_REAL_IO_L:
2155fcf5ef2aSThomas Huth         case ASI_N:
2156fcf5ef2aSThomas Huth         case ASI_NL:
2157fcf5ef2aSThomas Huth         case ASI_AIUP:
2158fcf5ef2aSThomas Huth         case ASI_AIUPL:
2159fcf5ef2aSThomas Huth         case ASI_AIUS:
2160fcf5ef2aSThomas Huth         case ASI_AIUSL:
2161fcf5ef2aSThomas Huth         case ASI_S:
2162fcf5ef2aSThomas Huth         case ASI_SL:
2163fcf5ef2aSThomas Huth         case ASI_P:
2164fcf5ef2aSThomas Huth         case ASI_PL:
2165fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
2166fcf5ef2aSThomas Huth             break;
2167fcf5ef2aSThomas Huth         case ASI_TWINX_REAL:
2168fcf5ef2aSThomas Huth         case ASI_TWINX_REAL_L:
2169fcf5ef2aSThomas Huth         case ASI_TWINX_N:
2170fcf5ef2aSThomas Huth         case ASI_TWINX_NL:
2171fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP:
2172fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP_L:
2173fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS:
2174fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS_L:
2175fcf5ef2aSThomas Huth         case ASI_TWINX_P:
2176fcf5ef2aSThomas Huth         case ASI_TWINX_PL:
2177fcf5ef2aSThomas Huth         case ASI_TWINX_S:
2178fcf5ef2aSThomas Huth         case ASI_TWINX_SL:
2179fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS:
2180fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS_L:
2181fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD:
2182fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD_L:
2183fcf5ef2aSThomas Huth             type = GET_ASI_DTWINX;
2184fcf5ef2aSThomas Huth             break;
2185fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_P:
2186fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_S:
2187fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_4V:
2188fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_L_4V:
2189fcf5ef2aSThomas Huth         case ASI_BLK_AIUP:
2190fcf5ef2aSThomas Huth         case ASI_BLK_AIUPL:
2191fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_4V:
2192fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_L_4V:
2193fcf5ef2aSThomas Huth         case ASI_BLK_AIUS:
2194fcf5ef2aSThomas Huth         case ASI_BLK_AIUSL:
2195fcf5ef2aSThomas Huth         case ASI_BLK_S:
2196fcf5ef2aSThomas Huth         case ASI_BLK_SL:
2197fcf5ef2aSThomas Huth         case ASI_BLK_P:
2198fcf5ef2aSThomas Huth         case ASI_BLK_PL:
2199fcf5ef2aSThomas Huth             type = GET_ASI_BLOCK;
2200fcf5ef2aSThomas Huth             break;
2201fcf5ef2aSThomas Huth         case ASI_FL8_S:
2202fcf5ef2aSThomas Huth         case ASI_FL8_SL:
2203fcf5ef2aSThomas Huth         case ASI_FL8_P:
2204fcf5ef2aSThomas Huth         case ASI_FL8_PL:
2205fcf5ef2aSThomas Huth             memop = MO_UB;
2206fcf5ef2aSThomas Huth             type = GET_ASI_SHORT;
2207fcf5ef2aSThomas Huth             break;
2208fcf5ef2aSThomas Huth         case ASI_FL16_S:
2209fcf5ef2aSThomas Huth         case ASI_FL16_SL:
2210fcf5ef2aSThomas Huth         case ASI_FL16_P:
2211fcf5ef2aSThomas Huth         case ASI_FL16_PL:
2212fcf5ef2aSThomas Huth             memop = MO_TEUW;
2213fcf5ef2aSThomas Huth             type = GET_ASI_SHORT;
2214fcf5ef2aSThomas Huth             break;
2215fcf5ef2aSThomas Huth         }
2216fcf5ef2aSThomas Huth         /* The little-endian asis all have bit 3 set.  */
2217fcf5ef2aSThomas Huth         if (asi & 8) {
2218fcf5ef2aSThomas Huth             memop ^= MO_BSWAP;
2219fcf5ef2aSThomas Huth         }
2220fcf5ef2aSThomas Huth     }
2221fcf5ef2aSThomas Huth #endif
2222fcf5ef2aSThomas Huth 
2223fcf5ef2aSThomas Huth     return (DisasASI){ type, asi, mem_idx, memop };
2224fcf5ef2aSThomas Huth }
2225fcf5ef2aSThomas Huth 
2226fcf5ef2aSThomas Huth static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
222714776ab5STony Nguyen                        int insn, MemOp memop)
2228fcf5ef2aSThomas Huth {
2229fcf5ef2aSThomas Huth     DisasASI da = get_asi(dc, insn, memop);
2230fcf5ef2aSThomas Huth 
2231fcf5ef2aSThomas Huth     switch (da.type) {
2232fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2233fcf5ef2aSThomas Huth         break;
2234fcf5ef2aSThomas Huth     case GET_ASI_DTWINX: /* Reserved for ldda.  */
2235fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
2236fcf5ef2aSThomas Huth         break;
2237fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2238fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2239fcf5ef2aSThomas Huth         tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2240fcf5ef2aSThomas Huth         break;
2241fcf5ef2aSThomas Huth     default:
2242fcf5ef2aSThomas Huth         {
2243fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2244fcf5ef2aSThomas Huth             TCGv_i32 r_mop = tcg_const_i32(memop);
2245fcf5ef2aSThomas Huth 
2246fcf5ef2aSThomas Huth             save_state(dc);
2247fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
2248fcf5ef2aSThomas Huth             gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
2249fcf5ef2aSThomas Huth #else
2250fcf5ef2aSThomas Huth             {
2251fcf5ef2aSThomas Huth                 TCGv_i64 t64 = tcg_temp_new_i64();
2252fcf5ef2aSThomas Huth                 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2253fcf5ef2aSThomas Huth                 tcg_gen_trunc_i64_tl(dst, t64);
2254fcf5ef2aSThomas Huth                 tcg_temp_free_i64(t64);
2255fcf5ef2aSThomas Huth             }
2256fcf5ef2aSThomas Huth #endif
2257fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2258fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2259fcf5ef2aSThomas Huth         }
2260fcf5ef2aSThomas Huth         break;
2261fcf5ef2aSThomas Huth     }
2262fcf5ef2aSThomas Huth }
2263fcf5ef2aSThomas Huth 
2264fcf5ef2aSThomas Huth static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
226514776ab5STony Nguyen                        int insn, MemOp memop)
2266fcf5ef2aSThomas Huth {
2267fcf5ef2aSThomas Huth     DisasASI da = get_asi(dc, insn, memop);
2268fcf5ef2aSThomas Huth 
2269fcf5ef2aSThomas Huth     switch (da.type) {
2270fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2271fcf5ef2aSThomas Huth         break;
2272fcf5ef2aSThomas Huth     case GET_ASI_DTWINX: /* Reserved for stda.  */
22733390537bSArtyom Tarasenko #ifndef TARGET_SPARC64
2274fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
2275fcf5ef2aSThomas Huth         break;
22763390537bSArtyom Tarasenko #else
22773390537bSArtyom Tarasenko         if (!(dc->def->features & CPU_FEATURE_HYPV)) {
22783390537bSArtyom Tarasenko             /* Pre OpenSPARC CPUs don't have these */
22793390537bSArtyom Tarasenko             gen_exception(dc, TT_ILL_INSN);
22803390537bSArtyom Tarasenko             return;
22813390537bSArtyom Tarasenko         }
22823390537bSArtyom Tarasenko         /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
22833390537bSArtyom Tarasenko          * are ST_BLKINIT_ ASIs */
22843390537bSArtyom Tarasenko #endif
2285fc0cd867SChen Qun         /* fall through */
2286fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2287fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2288fcf5ef2aSThomas Huth         tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2289fcf5ef2aSThomas Huth         break;
2290fcf5ef2aSThomas Huth #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2291fcf5ef2aSThomas Huth     case GET_ASI_BCOPY:
2292fcf5ef2aSThomas Huth         /* Copy 32 bytes from the address in SRC to ADDR.  */
2293fcf5ef2aSThomas Huth         /* ??? The original qemu code suggests 4-byte alignment, dropping
2294fcf5ef2aSThomas Huth            the low bits, but the only place I can see this used is in the
2295fcf5ef2aSThomas Huth            Linux kernel with 32 byte alignment, which would make more sense
2296fcf5ef2aSThomas Huth            as a cacheline-style operation.  */
2297fcf5ef2aSThomas Huth         {
2298fcf5ef2aSThomas Huth             TCGv saddr = tcg_temp_new();
2299fcf5ef2aSThomas Huth             TCGv daddr = tcg_temp_new();
2300fcf5ef2aSThomas Huth             TCGv four = tcg_const_tl(4);
2301fcf5ef2aSThomas Huth             TCGv_i32 tmp = tcg_temp_new_i32();
2302fcf5ef2aSThomas Huth             int i;
2303fcf5ef2aSThomas Huth 
2304fcf5ef2aSThomas Huth             tcg_gen_andi_tl(saddr, src, -4);
2305fcf5ef2aSThomas Huth             tcg_gen_andi_tl(daddr, addr, -4);
2306fcf5ef2aSThomas Huth             for (i = 0; i < 32; i += 4) {
2307fcf5ef2aSThomas Huth                 /* Since the loads and stores are paired, allow the
2308fcf5ef2aSThomas Huth                    copy to happen in the host endianness.  */
2309fcf5ef2aSThomas Huth                 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2310fcf5ef2aSThomas Huth                 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2311fcf5ef2aSThomas Huth                 tcg_gen_add_tl(saddr, saddr, four);
2312fcf5ef2aSThomas Huth                 tcg_gen_add_tl(daddr, daddr, four);
2313fcf5ef2aSThomas Huth             }
2314fcf5ef2aSThomas Huth 
2315fcf5ef2aSThomas Huth             tcg_temp_free(saddr);
2316fcf5ef2aSThomas Huth             tcg_temp_free(daddr);
2317fcf5ef2aSThomas Huth             tcg_temp_free(four);
2318fcf5ef2aSThomas Huth             tcg_temp_free_i32(tmp);
2319fcf5ef2aSThomas Huth         }
2320fcf5ef2aSThomas Huth         break;
2321fcf5ef2aSThomas Huth #endif
2322fcf5ef2aSThomas Huth     default:
2323fcf5ef2aSThomas Huth         {
2324fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2325fcf5ef2aSThomas Huth             TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
2326fcf5ef2aSThomas Huth 
2327fcf5ef2aSThomas Huth             save_state(dc);
2328fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
2329fcf5ef2aSThomas Huth             gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
2330fcf5ef2aSThomas Huth #else
2331fcf5ef2aSThomas Huth             {
2332fcf5ef2aSThomas Huth                 TCGv_i64 t64 = tcg_temp_new_i64();
2333fcf5ef2aSThomas Huth                 tcg_gen_extu_tl_i64(t64, src);
2334fcf5ef2aSThomas Huth                 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2335fcf5ef2aSThomas Huth                 tcg_temp_free_i64(t64);
2336fcf5ef2aSThomas Huth             }
2337fcf5ef2aSThomas Huth #endif
2338fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2339fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2340fcf5ef2aSThomas Huth 
2341fcf5ef2aSThomas Huth             /* A write to a TLB register may alter page maps.  End the TB. */
2342fcf5ef2aSThomas Huth             dc->npc = DYNAMIC_PC;
2343fcf5ef2aSThomas Huth         }
2344fcf5ef2aSThomas Huth         break;
2345fcf5ef2aSThomas Huth     }
2346fcf5ef2aSThomas Huth }
2347fcf5ef2aSThomas Huth 
2348fcf5ef2aSThomas Huth static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2349fcf5ef2aSThomas Huth                          TCGv addr, int insn)
2350fcf5ef2aSThomas Huth {
2351fcf5ef2aSThomas Huth     DisasASI da = get_asi(dc, insn, MO_TEUL);
2352fcf5ef2aSThomas Huth 
2353fcf5ef2aSThomas Huth     switch (da.type) {
2354fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2355fcf5ef2aSThomas Huth         break;
2356fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2357fcf5ef2aSThomas Huth         gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2358fcf5ef2aSThomas Huth         break;
2359fcf5ef2aSThomas Huth     default:
2360fcf5ef2aSThomas Huth         /* ??? Should be DAE_invalid_asi.  */
2361fcf5ef2aSThomas Huth         gen_exception(dc, TT_DATA_ACCESS);
2362fcf5ef2aSThomas Huth         break;
2363fcf5ef2aSThomas Huth     }
2364fcf5ef2aSThomas Huth }
2365fcf5ef2aSThomas Huth 
2366fcf5ef2aSThomas Huth static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
2367fcf5ef2aSThomas Huth                         int insn, int rd)
2368fcf5ef2aSThomas Huth {
2369fcf5ef2aSThomas Huth     DisasASI da = get_asi(dc, insn, MO_TEUL);
2370fcf5ef2aSThomas Huth     TCGv oldv;
2371fcf5ef2aSThomas Huth 
2372fcf5ef2aSThomas Huth     switch (da.type) {
2373fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2374fcf5ef2aSThomas Huth         return;
2375fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2376fcf5ef2aSThomas Huth         oldv = tcg_temp_new();
2377fcf5ef2aSThomas Huth         tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2378fcf5ef2aSThomas Huth                                   da.mem_idx, da.memop);
2379fcf5ef2aSThomas Huth         gen_store_gpr(dc, rd, oldv);
2380fcf5ef2aSThomas Huth         tcg_temp_free(oldv);
2381fcf5ef2aSThomas Huth         break;
2382fcf5ef2aSThomas Huth     default:
2383fcf5ef2aSThomas Huth         /* ??? Should be DAE_invalid_asi.  */
2384fcf5ef2aSThomas Huth         gen_exception(dc, TT_DATA_ACCESS);
2385fcf5ef2aSThomas Huth         break;
2386fcf5ef2aSThomas Huth     }
2387fcf5ef2aSThomas Huth }
2388fcf5ef2aSThomas Huth 
2389fcf5ef2aSThomas Huth static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2390fcf5ef2aSThomas Huth {
2391fcf5ef2aSThomas Huth     DisasASI da = get_asi(dc, insn, MO_UB);
2392fcf5ef2aSThomas Huth 
2393fcf5ef2aSThomas Huth     switch (da.type) {
2394fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2395fcf5ef2aSThomas Huth         break;
2396fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2397fcf5ef2aSThomas Huth         gen_ldstub(dc, dst, addr, da.mem_idx);
2398fcf5ef2aSThomas Huth         break;
2399fcf5ef2aSThomas Huth     default:
24003db010c3SRichard Henderson         /* ??? In theory, this should be raise DAE_invalid_asi.
24013db010c3SRichard Henderson            But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1.  */
2402af00be49SEmilio G. Cota         if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
24033db010c3SRichard Henderson             gen_helper_exit_atomic(cpu_env);
24043db010c3SRichard Henderson         } else {
24053db010c3SRichard Henderson             TCGv_i32 r_asi = tcg_const_i32(da.asi);
24063db010c3SRichard Henderson             TCGv_i32 r_mop = tcg_const_i32(MO_UB);
24073db010c3SRichard Henderson             TCGv_i64 s64, t64;
24083db010c3SRichard Henderson 
24093db010c3SRichard Henderson             save_state(dc);
24103db010c3SRichard Henderson             t64 = tcg_temp_new_i64();
24113db010c3SRichard Henderson             gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
24123db010c3SRichard Henderson 
24133db010c3SRichard Henderson             s64 = tcg_const_i64(0xff);
24143db010c3SRichard Henderson             gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
24153db010c3SRichard Henderson             tcg_temp_free_i64(s64);
24163db010c3SRichard Henderson             tcg_temp_free_i32(r_mop);
24173db010c3SRichard Henderson             tcg_temp_free_i32(r_asi);
24183db010c3SRichard Henderson 
24193db010c3SRichard Henderson             tcg_gen_trunc_i64_tl(dst, t64);
24203db010c3SRichard Henderson             tcg_temp_free_i64(t64);
24213db010c3SRichard Henderson 
24223db010c3SRichard Henderson             /* End the TB.  */
24233db010c3SRichard Henderson             dc->npc = DYNAMIC_PC;
24243db010c3SRichard Henderson         }
2425fcf5ef2aSThomas Huth         break;
2426fcf5ef2aSThomas Huth     }
2427fcf5ef2aSThomas Huth }
2428fcf5ef2aSThomas Huth #endif
2429fcf5ef2aSThomas Huth 
2430fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
2431fcf5ef2aSThomas Huth static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2432fcf5ef2aSThomas Huth                         int insn, int size, int rd)
2433fcf5ef2aSThomas Huth {
2434fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
2435fcf5ef2aSThomas Huth     TCGv_i32 d32;
2436fcf5ef2aSThomas Huth     TCGv_i64 d64;
2437fcf5ef2aSThomas Huth 
2438fcf5ef2aSThomas Huth     switch (da.type) {
2439fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2440fcf5ef2aSThomas Huth         break;
2441fcf5ef2aSThomas Huth 
2442fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2443fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2444fcf5ef2aSThomas Huth         switch (size) {
2445fcf5ef2aSThomas Huth         case 4:
2446fcf5ef2aSThomas Huth             d32 = gen_dest_fpr_F(dc);
2447fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2448fcf5ef2aSThomas Huth             gen_store_fpr_F(dc, rd, d32);
2449fcf5ef2aSThomas Huth             break;
2450fcf5ef2aSThomas Huth         case 8:
2451fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2452fcf5ef2aSThomas Huth                                 da.memop | MO_ALIGN_4);
2453fcf5ef2aSThomas Huth             break;
2454fcf5ef2aSThomas Huth         case 16:
2455fcf5ef2aSThomas Huth             d64 = tcg_temp_new_i64();
2456fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
2457fcf5ef2aSThomas Huth             tcg_gen_addi_tl(addr, addr, 8);
2458fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2459fcf5ef2aSThomas Huth                                 da.memop | MO_ALIGN_4);
2460fcf5ef2aSThomas Huth             tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2461fcf5ef2aSThomas Huth             tcg_temp_free_i64(d64);
2462fcf5ef2aSThomas Huth             break;
2463fcf5ef2aSThomas Huth         default:
2464fcf5ef2aSThomas Huth             g_assert_not_reached();
2465fcf5ef2aSThomas Huth         }
2466fcf5ef2aSThomas Huth         break;
2467fcf5ef2aSThomas Huth 
2468fcf5ef2aSThomas Huth     case GET_ASI_BLOCK:
2469fcf5ef2aSThomas Huth         /* Valid for lddfa on aligned registers only.  */
2470fcf5ef2aSThomas Huth         if (size == 8 && (rd & 7) == 0) {
247114776ab5STony Nguyen             MemOp memop;
2472fcf5ef2aSThomas Huth             TCGv eight;
2473fcf5ef2aSThomas Huth             int i;
2474fcf5ef2aSThomas Huth 
2475fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2476fcf5ef2aSThomas Huth 
2477fcf5ef2aSThomas Huth             /* The first operation checks required alignment.  */
2478fcf5ef2aSThomas Huth             memop = da.memop | MO_ALIGN_64;
2479fcf5ef2aSThomas Huth             eight = tcg_const_tl(8);
2480fcf5ef2aSThomas Huth             for (i = 0; ; ++i) {
2481fcf5ef2aSThomas Huth                 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
2482fcf5ef2aSThomas Huth                                     da.mem_idx, memop);
2483fcf5ef2aSThomas Huth                 if (i == 7) {
2484fcf5ef2aSThomas Huth                     break;
2485fcf5ef2aSThomas Huth                 }
2486fcf5ef2aSThomas Huth                 tcg_gen_add_tl(addr, addr, eight);
2487fcf5ef2aSThomas Huth                 memop = da.memop;
2488fcf5ef2aSThomas Huth             }
2489fcf5ef2aSThomas Huth             tcg_temp_free(eight);
2490fcf5ef2aSThomas Huth         } else {
2491fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2492fcf5ef2aSThomas Huth         }
2493fcf5ef2aSThomas Huth         break;
2494fcf5ef2aSThomas Huth 
2495fcf5ef2aSThomas Huth     case GET_ASI_SHORT:
2496fcf5ef2aSThomas Huth         /* Valid for lddfa only.  */
2497fcf5ef2aSThomas Huth         if (size == 8) {
2498fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2499fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2500fcf5ef2aSThomas Huth         } else {
2501fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2502fcf5ef2aSThomas Huth         }
2503fcf5ef2aSThomas Huth         break;
2504fcf5ef2aSThomas Huth 
2505fcf5ef2aSThomas Huth     default:
2506fcf5ef2aSThomas Huth         {
2507fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2508fcf5ef2aSThomas Huth             TCGv_i32 r_mop = tcg_const_i32(da.memop);
2509fcf5ef2aSThomas Huth 
2510fcf5ef2aSThomas Huth             save_state(dc);
2511fcf5ef2aSThomas Huth             /* According to the table in the UA2011 manual, the only
2512fcf5ef2aSThomas Huth                other asis that are valid for ldfa/lddfa/ldqfa are
2513fcf5ef2aSThomas Huth                the NO_FAULT asis.  We still need a helper for these,
2514fcf5ef2aSThomas Huth                but we can just use the integer asi helper for them.  */
2515fcf5ef2aSThomas Huth             switch (size) {
2516fcf5ef2aSThomas Huth             case 4:
2517fcf5ef2aSThomas Huth                 d64 = tcg_temp_new_i64();
2518fcf5ef2aSThomas Huth                 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2519fcf5ef2aSThomas Huth                 d32 = gen_dest_fpr_F(dc);
2520fcf5ef2aSThomas Huth                 tcg_gen_extrl_i64_i32(d32, d64);
2521fcf5ef2aSThomas Huth                 tcg_temp_free_i64(d64);
2522fcf5ef2aSThomas Huth                 gen_store_fpr_F(dc, rd, d32);
2523fcf5ef2aSThomas Huth                 break;
2524fcf5ef2aSThomas Huth             case 8:
2525fcf5ef2aSThomas Huth                 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2526fcf5ef2aSThomas Huth                 break;
2527fcf5ef2aSThomas Huth             case 16:
2528fcf5ef2aSThomas Huth                 d64 = tcg_temp_new_i64();
2529fcf5ef2aSThomas Huth                 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2530fcf5ef2aSThomas Huth                 tcg_gen_addi_tl(addr, addr, 8);
2531fcf5ef2aSThomas Huth                 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
2532fcf5ef2aSThomas Huth                 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2533fcf5ef2aSThomas Huth                 tcg_temp_free_i64(d64);
2534fcf5ef2aSThomas Huth                 break;
2535fcf5ef2aSThomas Huth             default:
2536fcf5ef2aSThomas Huth                 g_assert_not_reached();
2537fcf5ef2aSThomas Huth             }
2538fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2539fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2540fcf5ef2aSThomas Huth         }
2541fcf5ef2aSThomas Huth         break;
2542fcf5ef2aSThomas Huth     }
2543fcf5ef2aSThomas Huth }
2544fcf5ef2aSThomas Huth 
2545fcf5ef2aSThomas Huth static void gen_stf_asi(DisasContext *dc, TCGv addr,
2546fcf5ef2aSThomas Huth                         int insn, int size, int rd)
2547fcf5ef2aSThomas Huth {
2548fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
2549fcf5ef2aSThomas Huth     TCGv_i32 d32;
2550fcf5ef2aSThomas Huth 
2551fcf5ef2aSThomas Huth     switch (da.type) {
2552fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2553fcf5ef2aSThomas Huth         break;
2554fcf5ef2aSThomas Huth 
2555fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2556fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2557fcf5ef2aSThomas Huth         switch (size) {
2558fcf5ef2aSThomas Huth         case 4:
2559fcf5ef2aSThomas Huth             d32 = gen_load_fpr_F(dc, rd);
2560fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2561fcf5ef2aSThomas Huth             break;
2562fcf5ef2aSThomas Huth         case 8:
2563fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2564fcf5ef2aSThomas Huth                                 da.memop | MO_ALIGN_4);
2565fcf5ef2aSThomas Huth             break;
2566fcf5ef2aSThomas Huth         case 16:
2567fcf5ef2aSThomas Huth             /* Only 4-byte alignment required.  However, it is legal for the
2568fcf5ef2aSThomas Huth                cpu to signal the alignment fault, and the OS trap handler is
2569fcf5ef2aSThomas Huth                required to fix it up.  Requiring 16-byte alignment here avoids
2570fcf5ef2aSThomas Huth                having to probe the second page before performing the first
2571fcf5ef2aSThomas Huth                write.  */
2572fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2573fcf5ef2aSThomas Huth                                 da.memop | MO_ALIGN_16);
2574fcf5ef2aSThomas Huth             tcg_gen_addi_tl(addr, addr, 8);
2575fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2576fcf5ef2aSThomas Huth             break;
2577fcf5ef2aSThomas Huth         default:
2578fcf5ef2aSThomas Huth             g_assert_not_reached();
2579fcf5ef2aSThomas Huth         }
2580fcf5ef2aSThomas Huth         break;
2581fcf5ef2aSThomas Huth 
2582fcf5ef2aSThomas Huth     case GET_ASI_BLOCK:
2583fcf5ef2aSThomas Huth         /* Valid for stdfa on aligned registers only.  */
2584fcf5ef2aSThomas Huth         if (size == 8 && (rd & 7) == 0) {
258514776ab5STony Nguyen             MemOp memop;
2586fcf5ef2aSThomas Huth             TCGv eight;
2587fcf5ef2aSThomas Huth             int i;
2588fcf5ef2aSThomas Huth 
2589fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2590fcf5ef2aSThomas Huth 
2591fcf5ef2aSThomas Huth             /* The first operation checks required alignment.  */
2592fcf5ef2aSThomas Huth             memop = da.memop | MO_ALIGN_64;
2593fcf5ef2aSThomas Huth             eight = tcg_const_tl(8);
2594fcf5ef2aSThomas Huth             for (i = 0; ; ++i) {
2595fcf5ef2aSThomas Huth                 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
2596fcf5ef2aSThomas Huth                                     da.mem_idx, memop);
2597fcf5ef2aSThomas Huth                 if (i == 7) {
2598fcf5ef2aSThomas Huth                     break;
2599fcf5ef2aSThomas Huth                 }
2600fcf5ef2aSThomas Huth                 tcg_gen_add_tl(addr, addr, eight);
2601fcf5ef2aSThomas Huth                 memop = da.memop;
2602fcf5ef2aSThomas Huth             }
2603fcf5ef2aSThomas Huth             tcg_temp_free(eight);
2604fcf5ef2aSThomas Huth         } else {
2605fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2606fcf5ef2aSThomas Huth         }
2607fcf5ef2aSThomas Huth         break;
2608fcf5ef2aSThomas Huth 
2609fcf5ef2aSThomas Huth     case GET_ASI_SHORT:
2610fcf5ef2aSThomas Huth         /* Valid for stdfa only.  */
2611fcf5ef2aSThomas Huth         if (size == 8) {
2612fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2613fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2614fcf5ef2aSThomas Huth         } else {
2615fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2616fcf5ef2aSThomas Huth         }
2617fcf5ef2aSThomas Huth         break;
2618fcf5ef2aSThomas Huth 
2619fcf5ef2aSThomas Huth     default:
2620fcf5ef2aSThomas Huth         /* According to the table in the UA2011 manual, the only
2621fcf5ef2aSThomas Huth            other asis that are valid for ldfa/lddfa/ldqfa are
2622fcf5ef2aSThomas Huth            the PST* asis, which aren't currently handled.  */
2623fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
2624fcf5ef2aSThomas Huth         break;
2625fcf5ef2aSThomas Huth     }
2626fcf5ef2aSThomas Huth }
2627fcf5ef2aSThomas Huth 
2628fcf5ef2aSThomas Huth static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
2629fcf5ef2aSThomas Huth {
2630fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, MO_TEUQ);
2631fcf5ef2aSThomas Huth     TCGv_i64 hi = gen_dest_gpr(dc, rd);
2632fcf5ef2aSThomas Huth     TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
2633fcf5ef2aSThomas Huth 
2634fcf5ef2aSThomas Huth     switch (da.type) {
2635fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2636fcf5ef2aSThomas Huth         return;
2637fcf5ef2aSThomas Huth 
2638fcf5ef2aSThomas Huth     case GET_ASI_DTWINX:
2639fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2640fcf5ef2aSThomas Huth         tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
2641fcf5ef2aSThomas Huth         tcg_gen_addi_tl(addr, addr, 8);
2642fcf5ef2aSThomas Huth         tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
2643fcf5ef2aSThomas Huth         break;
2644fcf5ef2aSThomas Huth 
2645fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2646fcf5ef2aSThomas Huth         {
2647fcf5ef2aSThomas Huth             TCGv_i64 tmp = tcg_temp_new_i64();
2648fcf5ef2aSThomas Huth 
2649fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2650fcf5ef2aSThomas Huth             tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2651fcf5ef2aSThomas Huth 
2652fcf5ef2aSThomas Huth             /* Note that LE ldda acts as if each 32-bit register
2653fcf5ef2aSThomas Huth                result is byte swapped.  Having just performed one
2654fcf5ef2aSThomas Huth                64-bit bswap, we need now to swap the writebacks.  */
2655fcf5ef2aSThomas Huth             if ((da.memop & MO_BSWAP) == MO_TE) {
2656fcf5ef2aSThomas Huth                 tcg_gen_extr32_i64(lo, hi, tmp);
2657fcf5ef2aSThomas Huth             } else {
2658fcf5ef2aSThomas Huth                 tcg_gen_extr32_i64(hi, lo, tmp);
2659fcf5ef2aSThomas Huth             }
2660fcf5ef2aSThomas Huth             tcg_temp_free_i64(tmp);
2661fcf5ef2aSThomas Huth         }
2662fcf5ef2aSThomas Huth         break;
2663fcf5ef2aSThomas Huth 
2664fcf5ef2aSThomas Huth     default:
2665fcf5ef2aSThomas Huth         /* ??? In theory we've handled all of the ASIs that are valid
2666fcf5ef2aSThomas Huth            for ldda, and this should raise DAE_invalid_asi.  However,
2667fcf5ef2aSThomas Huth            real hardware allows others.  This can be seen with e.g.
2668fcf5ef2aSThomas Huth            FreeBSD 10.3 wrt ASI_IC_TAG.  */
2669fcf5ef2aSThomas Huth         {
2670fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2671fcf5ef2aSThomas Huth             TCGv_i32 r_mop = tcg_const_i32(da.memop);
2672fcf5ef2aSThomas Huth             TCGv_i64 tmp = tcg_temp_new_i64();
2673fcf5ef2aSThomas Huth 
2674fcf5ef2aSThomas Huth             save_state(dc);
2675fcf5ef2aSThomas Huth             gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
2676fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2677fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2678fcf5ef2aSThomas Huth 
2679fcf5ef2aSThomas Huth             /* See above.  */
2680fcf5ef2aSThomas Huth             if ((da.memop & MO_BSWAP) == MO_TE) {
2681fcf5ef2aSThomas Huth                 tcg_gen_extr32_i64(lo, hi, tmp);
2682fcf5ef2aSThomas Huth             } else {
2683fcf5ef2aSThomas Huth                 tcg_gen_extr32_i64(hi, lo, tmp);
2684fcf5ef2aSThomas Huth             }
2685fcf5ef2aSThomas Huth             tcg_temp_free_i64(tmp);
2686fcf5ef2aSThomas Huth         }
2687fcf5ef2aSThomas Huth         break;
2688fcf5ef2aSThomas Huth     }
2689fcf5ef2aSThomas Huth 
2690fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd, hi);
2691fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd + 1, lo);
2692fcf5ef2aSThomas Huth }
2693fcf5ef2aSThomas Huth 
2694fcf5ef2aSThomas Huth static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2695fcf5ef2aSThomas Huth                          int insn, int rd)
2696fcf5ef2aSThomas Huth {
2697fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, MO_TEUQ);
2698fcf5ef2aSThomas Huth     TCGv lo = gen_load_gpr(dc, rd + 1);
2699fcf5ef2aSThomas Huth 
2700fcf5ef2aSThomas Huth     switch (da.type) {
2701fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2702fcf5ef2aSThomas Huth         break;
2703fcf5ef2aSThomas Huth 
2704fcf5ef2aSThomas Huth     case GET_ASI_DTWINX:
2705fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2706fcf5ef2aSThomas Huth         tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
2707fcf5ef2aSThomas Huth         tcg_gen_addi_tl(addr, addr, 8);
2708fcf5ef2aSThomas Huth         tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2709fcf5ef2aSThomas Huth         break;
2710fcf5ef2aSThomas Huth 
2711fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2712fcf5ef2aSThomas Huth         {
2713fcf5ef2aSThomas Huth             TCGv_i64 t64 = tcg_temp_new_i64();
2714fcf5ef2aSThomas Huth 
2715fcf5ef2aSThomas Huth             /* Note that LE stda acts as if each 32-bit register result is
2716fcf5ef2aSThomas Huth                byte swapped.  We will perform one 64-bit LE store, so now
2717fcf5ef2aSThomas Huth                we must swap the order of the construction.  */
2718fcf5ef2aSThomas Huth             if ((da.memop & MO_BSWAP) == MO_TE) {
2719fcf5ef2aSThomas Huth                 tcg_gen_concat32_i64(t64, lo, hi);
2720fcf5ef2aSThomas Huth             } else {
2721fcf5ef2aSThomas Huth                 tcg_gen_concat32_i64(t64, hi, lo);
2722fcf5ef2aSThomas Huth             }
2723fcf5ef2aSThomas Huth             gen_address_mask(dc, addr);
2724fcf5ef2aSThomas Huth             tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2725fcf5ef2aSThomas Huth             tcg_temp_free_i64(t64);
2726fcf5ef2aSThomas Huth         }
2727fcf5ef2aSThomas Huth         break;
2728fcf5ef2aSThomas Huth 
2729fcf5ef2aSThomas Huth     default:
2730fcf5ef2aSThomas Huth         /* ??? In theory we've handled all of the ASIs that are valid
2731fcf5ef2aSThomas Huth            for stda, and this should raise DAE_invalid_asi.  */
2732fcf5ef2aSThomas Huth         {
2733fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2734fcf5ef2aSThomas Huth             TCGv_i32 r_mop = tcg_const_i32(da.memop);
2735fcf5ef2aSThomas Huth             TCGv_i64 t64 = tcg_temp_new_i64();
2736fcf5ef2aSThomas Huth 
2737fcf5ef2aSThomas Huth             /* See above.  */
2738fcf5ef2aSThomas Huth             if ((da.memop & MO_BSWAP) == MO_TE) {
2739fcf5ef2aSThomas Huth                 tcg_gen_concat32_i64(t64, lo, hi);
2740fcf5ef2aSThomas Huth             } else {
2741fcf5ef2aSThomas Huth                 tcg_gen_concat32_i64(t64, hi, lo);
2742fcf5ef2aSThomas Huth             }
2743fcf5ef2aSThomas Huth 
2744fcf5ef2aSThomas Huth             save_state(dc);
2745fcf5ef2aSThomas Huth             gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2746fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2747fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2748fcf5ef2aSThomas Huth             tcg_temp_free_i64(t64);
2749fcf5ef2aSThomas Huth         }
2750fcf5ef2aSThomas Huth         break;
2751fcf5ef2aSThomas Huth     }
2752fcf5ef2aSThomas Huth }
2753fcf5ef2aSThomas Huth 
2754fcf5ef2aSThomas Huth static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
2755fcf5ef2aSThomas Huth                          int insn, int rd)
2756fcf5ef2aSThomas Huth {
2757fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, MO_TEUQ);
2758fcf5ef2aSThomas Huth     TCGv oldv;
2759fcf5ef2aSThomas Huth 
2760fcf5ef2aSThomas Huth     switch (da.type) {
2761fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2762fcf5ef2aSThomas Huth         return;
2763fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2764fcf5ef2aSThomas Huth         oldv = tcg_temp_new();
2765fcf5ef2aSThomas Huth         tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2766fcf5ef2aSThomas Huth                                   da.mem_idx, da.memop);
2767fcf5ef2aSThomas Huth         gen_store_gpr(dc, rd, oldv);
2768fcf5ef2aSThomas Huth         tcg_temp_free(oldv);
2769fcf5ef2aSThomas Huth         break;
2770fcf5ef2aSThomas Huth     default:
2771fcf5ef2aSThomas Huth         /* ??? Should be DAE_invalid_asi.  */
2772fcf5ef2aSThomas Huth         gen_exception(dc, TT_DATA_ACCESS);
2773fcf5ef2aSThomas Huth         break;
2774fcf5ef2aSThomas Huth     }
2775fcf5ef2aSThomas Huth }
2776fcf5ef2aSThomas Huth 
2777fcf5ef2aSThomas Huth #elif !defined(CONFIG_USER_ONLY)
2778fcf5ef2aSThomas Huth static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
2779fcf5ef2aSThomas Huth {
2780fcf5ef2aSThomas Huth     /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2781fcf5ef2aSThomas Huth        whereby "rd + 1" elicits "error: array subscript is above array".
2782fcf5ef2aSThomas Huth        Since we have already asserted that rd is even, the semantics
2783fcf5ef2aSThomas Huth        are unchanged.  */
2784fcf5ef2aSThomas Huth     TCGv lo = gen_dest_gpr(dc, rd | 1);
2785fcf5ef2aSThomas Huth     TCGv hi = gen_dest_gpr(dc, rd);
2786fcf5ef2aSThomas Huth     TCGv_i64 t64 = tcg_temp_new_i64();
2787fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, MO_TEUQ);
2788fcf5ef2aSThomas Huth 
2789fcf5ef2aSThomas Huth     switch (da.type) {
2790fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2791fcf5ef2aSThomas Huth         tcg_temp_free_i64(t64);
2792fcf5ef2aSThomas Huth         return;
2793fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2794fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2795fcf5ef2aSThomas Huth         tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2796fcf5ef2aSThomas Huth         break;
2797fcf5ef2aSThomas Huth     default:
2798fcf5ef2aSThomas Huth         {
2799fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2800fc313c64SFrédéric Pétrot             TCGv_i32 r_mop = tcg_const_i32(MO_UQ);
2801fcf5ef2aSThomas Huth 
2802fcf5ef2aSThomas Huth             save_state(dc);
2803fcf5ef2aSThomas Huth             gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2804fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2805fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2806fcf5ef2aSThomas Huth         }
2807fcf5ef2aSThomas Huth         break;
2808fcf5ef2aSThomas Huth     }
2809fcf5ef2aSThomas Huth 
2810fcf5ef2aSThomas Huth     tcg_gen_extr_i64_i32(lo, hi, t64);
2811fcf5ef2aSThomas Huth     tcg_temp_free_i64(t64);
2812fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd | 1, lo);
2813fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd, hi);
2814fcf5ef2aSThomas Huth }
2815fcf5ef2aSThomas Huth 
2816fcf5ef2aSThomas Huth static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2817fcf5ef2aSThomas Huth                          int insn, int rd)
2818fcf5ef2aSThomas Huth {
2819fc313c64SFrédéric Pétrot     DisasASI da = get_asi(dc, insn, MO_TEUQ);
2820fcf5ef2aSThomas Huth     TCGv lo = gen_load_gpr(dc, rd + 1);
2821fcf5ef2aSThomas Huth     TCGv_i64 t64 = tcg_temp_new_i64();
2822fcf5ef2aSThomas Huth 
2823fcf5ef2aSThomas Huth     tcg_gen_concat_tl_i64(t64, lo, hi);
2824fcf5ef2aSThomas Huth 
2825fcf5ef2aSThomas Huth     switch (da.type) {
2826fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2827fcf5ef2aSThomas Huth         break;
2828fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2829fcf5ef2aSThomas Huth         gen_address_mask(dc, addr);
2830fcf5ef2aSThomas Huth         tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2831fcf5ef2aSThomas Huth         break;
2832fcf5ef2aSThomas Huth     case GET_ASI_BFILL:
2833fcf5ef2aSThomas Huth         /* Store 32 bytes of T64 to ADDR.  */
2834fcf5ef2aSThomas Huth         /* ??? The original qemu code suggests 8-byte alignment, dropping
2835fcf5ef2aSThomas Huth            the low bits, but the only place I can see this used is in the
2836fcf5ef2aSThomas Huth            Linux kernel with 32 byte alignment, which would make more sense
2837fcf5ef2aSThomas Huth            as a cacheline-style operation.  */
2838fcf5ef2aSThomas Huth         {
2839fcf5ef2aSThomas Huth             TCGv d_addr = tcg_temp_new();
2840fcf5ef2aSThomas Huth             TCGv eight = tcg_const_tl(8);
2841fcf5ef2aSThomas Huth             int i;
2842fcf5ef2aSThomas Huth 
2843fcf5ef2aSThomas Huth             tcg_gen_andi_tl(d_addr, addr, -8);
2844fcf5ef2aSThomas Huth             for (i = 0; i < 32; i += 8) {
2845fcf5ef2aSThomas Huth                 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2846fcf5ef2aSThomas Huth                 tcg_gen_add_tl(d_addr, d_addr, eight);
2847fcf5ef2aSThomas Huth             }
2848fcf5ef2aSThomas Huth 
2849fcf5ef2aSThomas Huth             tcg_temp_free(d_addr);
2850fcf5ef2aSThomas Huth             tcg_temp_free(eight);
2851fcf5ef2aSThomas Huth         }
2852fcf5ef2aSThomas Huth         break;
2853fcf5ef2aSThomas Huth     default:
2854fcf5ef2aSThomas Huth         {
2855fcf5ef2aSThomas Huth             TCGv_i32 r_asi = tcg_const_i32(da.asi);
2856fc313c64SFrédéric Pétrot             TCGv_i32 r_mop = tcg_const_i32(MO_UQ);
2857fcf5ef2aSThomas Huth 
2858fcf5ef2aSThomas Huth             save_state(dc);
2859fcf5ef2aSThomas Huth             gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2860fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_mop);
2861fcf5ef2aSThomas Huth             tcg_temp_free_i32(r_asi);
2862fcf5ef2aSThomas Huth         }
2863fcf5ef2aSThomas Huth         break;
2864fcf5ef2aSThomas Huth     }
2865fcf5ef2aSThomas Huth 
2866fcf5ef2aSThomas Huth     tcg_temp_free_i64(t64);
2867fcf5ef2aSThomas Huth }
2868fcf5ef2aSThomas Huth #endif
2869fcf5ef2aSThomas Huth 
2870fcf5ef2aSThomas Huth static TCGv get_src1(DisasContext *dc, unsigned int insn)
2871fcf5ef2aSThomas Huth {
2872fcf5ef2aSThomas Huth     unsigned int rs1 = GET_FIELD(insn, 13, 17);
2873fcf5ef2aSThomas Huth     return gen_load_gpr(dc, rs1);
2874fcf5ef2aSThomas Huth }
2875fcf5ef2aSThomas Huth 
2876fcf5ef2aSThomas Huth static TCGv get_src2(DisasContext *dc, unsigned int insn)
2877fcf5ef2aSThomas Huth {
2878fcf5ef2aSThomas Huth     if (IS_IMM) { /* immediate */
2879fcf5ef2aSThomas Huth         target_long simm = GET_FIELDs(insn, 19, 31);
288052123f14SRichard Henderson         TCGv t = tcg_temp_new();
2881fcf5ef2aSThomas Huth         tcg_gen_movi_tl(t, simm);
2882fcf5ef2aSThomas Huth         return t;
2883fcf5ef2aSThomas Huth     } else {      /* register */
2884fcf5ef2aSThomas Huth         unsigned int rs2 = GET_FIELD(insn, 27, 31);
2885fcf5ef2aSThomas Huth         return gen_load_gpr(dc, rs2);
2886fcf5ef2aSThomas Huth     }
2887fcf5ef2aSThomas Huth }
2888fcf5ef2aSThomas Huth 
2889fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
2890fcf5ef2aSThomas Huth static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2891fcf5ef2aSThomas Huth {
2892fcf5ef2aSThomas Huth     TCGv_i32 c32, zero, dst, s1, s2;
2893fcf5ef2aSThomas Huth 
2894fcf5ef2aSThomas Huth     /* We have two choices here: extend the 32 bit data and use movcond_i64,
2895fcf5ef2aSThomas Huth        or fold the comparison down to 32 bits and use movcond_i32.  Choose
2896fcf5ef2aSThomas Huth        the later.  */
2897fcf5ef2aSThomas Huth     c32 = tcg_temp_new_i32();
2898fcf5ef2aSThomas Huth     if (cmp->is_bool) {
2899fcf5ef2aSThomas Huth         tcg_gen_extrl_i64_i32(c32, cmp->c1);
2900fcf5ef2aSThomas Huth     } else {
2901fcf5ef2aSThomas Huth         TCGv_i64 c64 = tcg_temp_new_i64();
2902fcf5ef2aSThomas Huth         tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
2903fcf5ef2aSThomas Huth         tcg_gen_extrl_i64_i32(c32, c64);
2904fcf5ef2aSThomas Huth         tcg_temp_free_i64(c64);
2905fcf5ef2aSThomas Huth     }
2906fcf5ef2aSThomas Huth 
2907fcf5ef2aSThomas Huth     s1 = gen_load_fpr_F(dc, rs);
2908fcf5ef2aSThomas Huth     s2 = gen_load_fpr_F(dc, rd);
2909fcf5ef2aSThomas Huth     dst = gen_dest_fpr_F(dc);
2910fcf5ef2aSThomas Huth     zero = tcg_const_i32(0);
2911fcf5ef2aSThomas Huth 
2912fcf5ef2aSThomas Huth     tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2913fcf5ef2aSThomas Huth 
2914fcf5ef2aSThomas Huth     tcg_temp_free_i32(c32);
2915fcf5ef2aSThomas Huth     tcg_temp_free_i32(zero);
2916fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
2917fcf5ef2aSThomas Huth }
2918fcf5ef2aSThomas Huth 
2919fcf5ef2aSThomas Huth static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2920fcf5ef2aSThomas Huth {
2921fcf5ef2aSThomas Huth     TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
2922fcf5ef2aSThomas Huth     tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2923fcf5ef2aSThomas Huth                         gen_load_fpr_D(dc, rs),
2924fcf5ef2aSThomas Huth                         gen_load_fpr_D(dc, rd));
2925fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
2926fcf5ef2aSThomas Huth }
2927fcf5ef2aSThomas Huth 
2928fcf5ef2aSThomas Huth static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2929fcf5ef2aSThomas Huth {
2930fcf5ef2aSThomas Huth     int qd = QFPREG(rd);
2931fcf5ef2aSThomas Huth     int qs = QFPREG(rs);
2932fcf5ef2aSThomas Huth 
2933fcf5ef2aSThomas Huth     tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2934fcf5ef2aSThomas Huth                         cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2935fcf5ef2aSThomas Huth     tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2936fcf5ef2aSThomas Huth                         cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2937fcf5ef2aSThomas Huth 
2938fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, qd);
2939fcf5ef2aSThomas Huth }
2940fcf5ef2aSThomas Huth 
2941fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY
2942fcf5ef2aSThomas Huth static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
2943fcf5ef2aSThomas Huth {
2944fcf5ef2aSThomas Huth     TCGv_i32 r_tl = tcg_temp_new_i32();
2945fcf5ef2aSThomas Huth 
2946fcf5ef2aSThomas Huth     /* load env->tl into r_tl */
2947fcf5ef2aSThomas Huth     tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
2948fcf5ef2aSThomas Huth 
2949fcf5ef2aSThomas Huth     /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2950fcf5ef2aSThomas Huth     tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
2951fcf5ef2aSThomas Huth 
2952fcf5ef2aSThomas Huth     /* calculate offset to current trap state from env->ts, reuse r_tl */
2953fcf5ef2aSThomas Huth     tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
2954fcf5ef2aSThomas Huth     tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
2955fcf5ef2aSThomas Huth 
2956fcf5ef2aSThomas Huth     /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2957fcf5ef2aSThomas Huth     {
2958fcf5ef2aSThomas Huth         TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2959fcf5ef2aSThomas Huth         tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2960fcf5ef2aSThomas Huth         tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
2961fcf5ef2aSThomas Huth         tcg_temp_free_ptr(r_tl_tmp);
2962fcf5ef2aSThomas Huth     }
2963fcf5ef2aSThomas Huth 
2964fcf5ef2aSThomas Huth     tcg_temp_free_i32(r_tl);
2965fcf5ef2aSThomas Huth }
2966fcf5ef2aSThomas Huth #endif
2967fcf5ef2aSThomas Huth 
2968fcf5ef2aSThomas Huth static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2969fcf5ef2aSThomas Huth                      int width, bool cc, bool left)
2970fcf5ef2aSThomas Huth {
2971fcf5ef2aSThomas Huth     TCGv lo1, lo2, t1, t2;
2972fcf5ef2aSThomas Huth     uint64_t amask, tabl, tabr;
2973fcf5ef2aSThomas Huth     int shift, imask, omask;
2974fcf5ef2aSThomas Huth 
2975fcf5ef2aSThomas Huth     if (cc) {
2976fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src, s1);
2977fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_cc_src2, s2);
2978fcf5ef2aSThomas Huth         tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2979fcf5ef2aSThomas Huth         tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2980fcf5ef2aSThomas Huth         dc->cc_op = CC_OP_SUB;
2981fcf5ef2aSThomas Huth     }
2982fcf5ef2aSThomas Huth 
2983fcf5ef2aSThomas Huth     /* Theory of operation: there are two tables, left and right (not to
2984fcf5ef2aSThomas Huth        be confused with the left and right versions of the opcode).  These
2985fcf5ef2aSThomas Huth        are indexed by the low 3 bits of the inputs.  To make things "easy",
2986fcf5ef2aSThomas Huth        these tables are loaded into two constants, TABL and TABR below.
2987fcf5ef2aSThomas Huth        The operation index = (input & imask) << shift calculates the index
2988fcf5ef2aSThomas Huth        into the constant, while val = (table >> index) & omask calculates
2989fcf5ef2aSThomas Huth        the value we're looking for.  */
2990fcf5ef2aSThomas Huth     switch (width) {
2991fcf5ef2aSThomas Huth     case 8:
2992fcf5ef2aSThomas Huth         imask = 0x7;
2993fcf5ef2aSThomas Huth         shift = 3;
2994fcf5ef2aSThomas Huth         omask = 0xff;
2995fcf5ef2aSThomas Huth         if (left) {
2996fcf5ef2aSThomas Huth             tabl = 0x80c0e0f0f8fcfeffULL;
2997fcf5ef2aSThomas Huth             tabr = 0xff7f3f1f0f070301ULL;
2998fcf5ef2aSThomas Huth         } else {
2999fcf5ef2aSThomas Huth             tabl = 0x0103070f1f3f7fffULL;
3000fcf5ef2aSThomas Huth             tabr = 0xfffefcf8f0e0c080ULL;
3001fcf5ef2aSThomas Huth         }
3002fcf5ef2aSThomas Huth         break;
3003fcf5ef2aSThomas Huth     case 16:
3004fcf5ef2aSThomas Huth         imask = 0x6;
3005fcf5ef2aSThomas Huth         shift = 1;
3006fcf5ef2aSThomas Huth         omask = 0xf;
3007fcf5ef2aSThomas Huth         if (left) {
3008fcf5ef2aSThomas Huth             tabl = 0x8cef;
3009fcf5ef2aSThomas Huth             tabr = 0xf731;
3010fcf5ef2aSThomas Huth         } else {
3011fcf5ef2aSThomas Huth             tabl = 0x137f;
3012fcf5ef2aSThomas Huth             tabr = 0xfec8;
3013fcf5ef2aSThomas Huth         }
3014fcf5ef2aSThomas Huth         break;
3015fcf5ef2aSThomas Huth     case 32:
3016fcf5ef2aSThomas Huth         imask = 0x4;
3017fcf5ef2aSThomas Huth         shift = 0;
3018fcf5ef2aSThomas Huth         omask = 0x3;
3019fcf5ef2aSThomas Huth         if (left) {
3020fcf5ef2aSThomas Huth             tabl = (2 << 2) | 3;
3021fcf5ef2aSThomas Huth             tabr = (3 << 2) | 1;
3022fcf5ef2aSThomas Huth         } else {
3023fcf5ef2aSThomas Huth             tabl = (1 << 2) | 3;
3024fcf5ef2aSThomas Huth             tabr = (3 << 2) | 2;
3025fcf5ef2aSThomas Huth         }
3026fcf5ef2aSThomas Huth         break;
3027fcf5ef2aSThomas Huth     default:
3028fcf5ef2aSThomas Huth         abort();
3029fcf5ef2aSThomas Huth     }
3030fcf5ef2aSThomas Huth 
3031fcf5ef2aSThomas Huth     lo1 = tcg_temp_new();
3032fcf5ef2aSThomas Huth     lo2 = tcg_temp_new();
3033fcf5ef2aSThomas Huth     tcg_gen_andi_tl(lo1, s1, imask);
3034fcf5ef2aSThomas Huth     tcg_gen_andi_tl(lo2, s2, imask);
3035fcf5ef2aSThomas Huth     tcg_gen_shli_tl(lo1, lo1, shift);
3036fcf5ef2aSThomas Huth     tcg_gen_shli_tl(lo2, lo2, shift);
3037fcf5ef2aSThomas Huth 
3038fcf5ef2aSThomas Huth     t1 = tcg_const_tl(tabl);
3039fcf5ef2aSThomas Huth     t2 = tcg_const_tl(tabr);
3040fcf5ef2aSThomas Huth     tcg_gen_shr_tl(lo1, t1, lo1);
3041fcf5ef2aSThomas Huth     tcg_gen_shr_tl(lo2, t2, lo2);
3042fcf5ef2aSThomas Huth     tcg_gen_andi_tl(dst, lo1, omask);
3043fcf5ef2aSThomas Huth     tcg_gen_andi_tl(lo2, lo2, omask);
3044fcf5ef2aSThomas Huth 
3045fcf5ef2aSThomas Huth     amask = -8;
3046fcf5ef2aSThomas Huth     if (AM_CHECK(dc)) {
3047fcf5ef2aSThomas Huth         amask &= 0xffffffffULL;
3048fcf5ef2aSThomas Huth     }
3049fcf5ef2aSThomas Huth     tcg_gen_andi_tl(s1, s1, amask);
3050fcf5ef2aSThomas Huth     tcg_gen_andi_tl(s2, s2, amask);
3051fcf5ef2aSThomas Huth 
3052fcf5ef2aSThomas Huth     /* We want to compute
3053fcf5ef2aSThomas Huth         dst = (s1 == s2 ? lo1 : lo1 & lo2).
3054fcf5ef2aSThomas Huth        We've already done dst = lo1, so this reduces to
3055fcf5ef2aSThomas Huth         dst &= (s1 == s2 ? -1 : lo2)
3056fcf5ef2aSThomas Huth        Which we perform by
3057fcf5ef2aSThomas Huth         lo2 |= -(s1 == s2)
3058fcf5ef2aSThomas Huth         dst &= lo2
3059fcf5ef2aSThomas Huth     */
3060fcf5ef2aSThomas Huth     tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3061fcf5ef2aSThomas Huth     tcg_gen_neg_tl(t1, t1);
3062fcf5ef2aSThomas Huth     tcg_gen_or_tl(lo2, lo2, t1);
3063fcf5ef2aSThomas Huth     tcg_gen_and_tl(dst, dst, lo2);
3064fcf5ef2aSThomas Huth 
3065fcf5ef2aSThomas Huth     tcg_temp_free(lo1);
3066fcf5ef2aSThomas Huth     tcg_temp_free(lo2);
3067fcf5ef2aSThomas Huth     tcg_temp_free(t1);
3068fcf5ef2aSThomas Huth     tcg_temp_free(t2);
3069fcf5ef2aSThomas Huth }
3070fcf5ef2aSThomas Huth 
3071fcf5ef2aSThomas Huth static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3072fcf5ef2aSThomas Huth {
3073fcf5ef2aSThomas Huth     TCGv tmp = tcg_temp_new();
3074fcf5ef2aSThomas Huth 
3075fcf5ef2aSThomas Huth     tcg_gen_add_tl(tmp, s1, s2);
3076fcf5ef2aSThomas Huth     tcg_gen_andi_tl(dst, tmp, -8);
3077fcf5ef2aSThomas Huth     if (left) {
3078fcf5ef2aSThomas Huth         tcg_gen_neg_tl(tmp, tmp);
3079fcf5ef2aSThomas Huth     }
3080fcf5ef2aSThomas Huth     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3081fcf5ef2aSThomas Huth 
3082fcf5ef2aSThomas Huth     tcg_temp_free(tmp);
3083fcf5ef2aSThomas Huth }
3084fcf5ef2aSThomas Huth 
3085fcf5ef2aSThomas Huth static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3086fcf5ef2aSThomas Huth {
3087fcf5ef2aSThomas Huth     TCGv t1, t2, shift;
3088fcf5ef2aSThomas Huth 
3089fcf5ef2aSThomas Huth     t1 = tcg_temp_new();
3090fcf5ef2aSThomas Huth     t2 = tcg_temp_new();
3091fcf5ef2aSThomas Huth     shift = tcg_temp_new();
3092fcf5ef2aSThomas Huth 
3093fcf5ef2aSThomas Huth     tcg_gen_andi_tl(shift, gsr, 7);
3094fcf5ef2aSThomas Huth     tcg_gen_shli_tl(shift, shift, 3);
3095fcf5ef2aSThomas Huth     tcg_gen_shl_tl(t1, s1, shift);
3096fcf5ef2aSThomas Huth 
3097fcf5ef2aSThomas Huth     /* A shift of 64 does not produce 0 in TCG.  Divide this into a
3098fcf5ef2aSThomas Huth        shift of (up to 63) followed by a constant shift of 1.  */
3099fcf5ef2aSThomas Huth     tcg_gen_xori_tl(shift, shift, 63);
3100fcf5ef2aSThomas Huth     tcg_gen_shr_tl(t2, s2, shift);
3101fcf5ef2aSThomas Huth     tcg_gen_shri_tl(t2, t2, 1);
3102fcf5ef2aSThomas Huth 
3103fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, t1, t2);
3104fcf5ef2aSThomas Huth 
3105fcf5ef2aSThomas Huth     tcg_temp_free(t1);
3106fcf5ef2aSThomas Huth     tcg_temp_free(t2);
3107fcf5ef2aSThomas Huth     tcg_temp_free(shift);
3108fcf5ef2aSThomas Huth }
3109fcf5ef2aSThomas Huth #endif
3110fcf5ef2aSThomas Huth 
3111fcf5ef2aSThomas Huth #define CHECK_IU_FEATURE(dc, FEATURE)                      \
3112fcf5ef2aSThomas Huth     if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE))  \
3113fcf5ef2aSThomas Huth         goto illegal_insn;
3114fcf5ef2aSThomas Huth #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
3115fcf5ef2aSThomas Huth     if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE))  \
3116fcf5ef2aSThomas Huth         goto nfpu_insn;
3117fcf5ef2aSThomas Huth 
3118fcf5ef2aSThomas Huth /* before an instruction, dc->pc must be static */
3119fcf5ef2aSThomas Huth static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
3120fcf5ef2aSThomas Huth {
3121fcf5ef2aSThomas Huth     unsigned int opc, rs1, rs2, rd;
3122fcf5ef2aSThomas Huth     TCGv cpu_src1, cpu_src2;
3123fcf5ef2aSThomas Huth     TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
3124fcf5ef2aSThomas Huth     TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
3125fcf5ef2aSThomas Huth     target_long simm;
3126fcf5ef2aSThomas Huth 
3127fcf5ef2aSThomas Huth     opc = GET_FIELD(insn, 0, 1);
3128fcf5ef2aSThomas Huth     rd = GET_FIELD(insn, 2, 6);
3129fcf5ef2aSThomas Huth 
3130fcf5ef2aSThomas Huth     switch (opc) {
3131fcf5ef2aSThomas Huth     case 0:                     /* branches/sethi */
3132fcf5ef2aSThomas Huth         {
3133fcf5ef2aSThomas Huth             unsigned int xop = GET_FIELD(insn, 7, 9);
3134fcf5ef2aSThomas Huth             int32_t target;
3135fcf5ef2aSThomas Huth             switch (xop) {
3136fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3137fcf5ef2aSThomas Huth             case 0x1:           /* V9 BPcc */
3138fcf5ef2aSThomas Huth                 {
3139fcf5ef2aSThomas Huth                     int cc;
3140fcf5ef2aSThomas Huth 
3141fcf5ef2aSThomas Huth                     target = GET_FIELD_SP(insn, 0, 18);
3142fcf5ef2aSThomas Huth                     target = sign_extend(target, 19);
3143fcf5ef2aSThomas Huth                     target <<= 2;
3144fcf5ef2aSThomas Huth                     cc = GET_FIELD_SP(insn, 20, 21);
3145fcf5ef2aSThomas Huth                     if (cc == 0)
3146fcf5ef2aSThomas Huth                         do_branch(dc, target, insn, 0);
3147fcf5ef2aSThomas Huth                     else if (cc == 2)
3148fcf5ef2aSThomas Huth                         do_branch(dc, target, insn, 1);
3149fcf5ef2aSThomas Huth                     else
3150fcf5ef2aSThomas Huth                         goto illegal_insn;
3151fcf5ef2aSThomas Huth                     goto jmp_insn;
3152fcf5ef2aSThomas Huth                 }
3153fcf5ef2aSThomas Huth             case 0x3:           /* V9 BPr */
3154fcf5ef2aSThomas Huth                 {
3155fcf5ef2aSThomas Huth                     target = GET_FIELD_SP(insn, 0, 13) |
3156fcf5ef2aSThomas Huth                         (GET_FIELD_SP(insn, 20, 21) << 14);
3157fcf5ef2aSThomas Huth                     target = sign_extend(target, 16);
3158fcf5ef2aSThomas Huth                     target <<= 2;
3159fcf5ef2aSThomas Huth                     cpu_src1 = get_src1(dc, insn);
3160fcf5ef2aSThomas Huth                     do_branch_reg(dc, target, insn, cpu_src1);
3161fcf5ef2aSThomas Huth                     goto jmp_insn;
3162fcf5ef2aSThomas Huth                 }
3163fcf5ef2aSThomas Huth             case 0x5:           /* V9 FBPcc */
3164fcf5ef2aSThomas Huth                 {
3165fcf5ef2aSThomas Huth                     int cc = GET_FIELD_SP(insn, 20, 21);
3166fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
3167fcf5ef2aSThomas Huth                         goto jmp_insn;
3168fcf5ef2aSThomas Huth                     }
3169fcf5ef2aSThomas Huth                     target = GET_FIELD_SP(insn, 0, 18);
3170fcf5ef2aSThomas Huth                     target = sign_extend(target, 19);
3171fcf5ef2aSThomas Huth                     target <<= 2;
3172fcf5ef2aSThomas Huth                     do_fbranch(dc, target, insn, cc);
3173fcf5ef2aSThomas Huth                     goto jmp_insn;
3174fcf5ef2aSThomas Huth                 }
3175fcf5ef2aSThomas Huth #else
3176fcf5ef2aSThomas Huth             case 0x7:           /* CBN+x */
3177fcf5ef2aSThomas Huth                 {
3178fcf5ef2aSThomas Huth                     goto ncp_insn;
3179fcf5ef2aSThomas Huth                 }
3180fcf5ef2aSThomas Huth #endif
3181fcf5ef2aSThomas Huth             case 0x2:           /* BN+x */
3182fcf5ef2aSThomas Huth                 {
3183fcf5ef2aSThomas Huth                     target = GET_FIELD(insn, 10, 31);
3184fcf5ef2aSThomas Huth                     target = sign_extend(target, 22);
3185fcf5ef2aSThomas Huth                     target <<= 2;
3186fcf5ef2aSThomas Huth                     do_branch(dc, target, insn, 0);
3187fcf5ef2aSThomas Huth                     goto jmp_insn;
3188fcf5ef2aSThomas Huth                 }
3189fcf5ef2aSThomas Huth             case 0x6:           /* FBN+x */
3190fcf5ef2aSThomas Huth                 {
3191fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
3192fcf5ef2aSThomas Huth                         goto jmp_insn;
3193fcf5ef2aSThomas Huth                     }
3194fcf5ef2aSThomas Huth                     target = GET_FIELD(insn, 10, 31);
3195fcf5ef2aSThomas Huth                     target = sign_extend(target, 22);
3196fcf5ef2aSThomas Huth                     target <<= 2;
3197fcf5ef2aSThomas Huth                     do_fbranch(dc, target, insn, 0);
3198fcf5ef2aSThomas Huth                     goto jmp_insn;
3199fcf5ef2aSThomas Huth                 }
3200fcf5ef2aSThomas Huth             case 0x4:           /* SETHI */
3201fcf5ef2aSThomas Huth                 /* Special-case %g0 because that's the canonical nop.  */
3202fcf5ef2aSThomas Huth                 if (rd) {
3203fcf5ef2aSThomas Huth                     uint32_t value = GET_FIELD(insn, 10, 31);
3204fcf5ef2aSThomas Huth                     TCGv t = gen_dest_gpr(dc, rd);
3205fcf5ef2aSThomas Huth                     tcg_gen_movi_tl(t, value << 10);
3206fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, t);
3207fcf5ef2aSThomas Huth                 }
3208fcf5ef2aSThomas Huth                 break;
3209fcf5ef2aSThomas Huth             case 0x0:           /* UNIMPL */
3210fcf5ef2aSThomas Huth             default:
3211fcf5ef2aSThomas Huth                 goto illegal_insn;
3212fcf5ef2aSThomas Huth             }
3213fcf5ef2aSThomas Huth             break;
3214fcf5ef2aSThomas Huth         }
3215fcf5ef2aSThomas Huth         break;
3216fcf5ef2aSThomas Huth     case 1:                     /*CALL*/
3217fcf5ef2aSThomas Huth         {
3218fcf5ef2aSThomas Huth             target_long target = GET_FIELDs(insn, 2, 31) << 2;
3219fcf5ef2aSThomas Huth             TCGv o7 = gen_dest_gpr(dc, 15);
3220fcf5ef2aSThomas Huth 
3221fcf5ef2aSThomas Huth             tcg_gen_movi_tl(o7, dc->pc);
3222fcf5ef2aSThomas Huth             gen_store_gpr(dc, 15, o7);
3223fcf5ef2aSThomas Huth             target += dc->pc;
3224fcf5ef2aSThomas Huth             gen_mov_pc_npc(dc);
3225fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3226fcf5ef2aSThomas Huth             if (unlikely(AM_CHECK(dc))) {
3227fcf5ef2aSThomas Huth                 target &= 0xffffffffULL;
3228fcf5ef2aSThomas Huth             }
3229fcf5ef2aSThomas Huth #endif
3230fcf5ef2aSThomas Huth             dc->npc = target;
3231fcf5ef2aSThomas Huth         }
3232fcf5ef2aSThomas Huth         goto jmp_insn;
3233fcf5ef2aSThomas Huth     case 2:                     /* FPU & Logical Operations */
3234fcf5ef2aSThomas Huth         {
3235fcf5ef2aSThomas Huth             unsigned int xop = GET_FIELD(insn, 7, 12);
323652123f14SRichard Henderson             TCGv cpu_dst = tcg_temp_new();
3237fcf5ef2aSThomas Huth             TCGv cpu_tmp0;
3238fcf5ef2aSThomas Huth 
3239fcf5ef2aSThomas Huth             if (xop == 0x3a) {  /* generate trap */
3240fcf5ef2aSThomas Huth                 int cond = GET_FIELD(insn, 3, 6);
3241fcf5ef2aSThomas Huth                 TCGv_i32 trap;
3242fcf5ef2aSThomas Huth                 TCGLabel *l1 = NULL;
3243fcf5ef2aSThomas Huth                 int mask;
3244fcf5ef2aSThomas Huth 
3245fcf5ef2aSThomas Huth                 if (cond == 0) {
3246fcf5ef2aSThomas Huth                     /* Trap never.  */
3247fcf5ef2aSThomas Huth                     break;
3248fcf5ef2aSThomas Huth                 }
3249fcf5ef2aSThomas Huth 
3250fcf5ef2aSThomas Huth                 save_state(dc);
3251fcf5ef2aSThomas Huth 
3252fcf5ef2aSThomas Huth                 if (cond != 8) {
3253fcf5ef2aSThomas Huth                     /* Conditional trap.  */
3254fcf5ef2aSThomas Huth                     DisasCompare cmp;
3255fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3256fcf5ef2aSThomas Huth                     /* V9 icc/xcc */
3257fcf5ef2aSThomas Huth                     int cc = GET_FIELD_SP(insn, 11, 12);
3258fcf5ef2aSThomas Huth                     if (cc == 0) {
3259fcf5ef2aSThomas Huth                         gen_compare(&cmp, 0, cond, dc);
3260fcf5ef2aSThomas Huth                     } else if (cc == 2) {
3261fcf5ef2aSThomas Huth                         gen_compare(&cmp, 1, cond, dc);
3262fcf5ef2aSThomas Huth                     } else {
3263fcf5ef2aSThomas Huth                         goto illegal_insn;
3264fcf5ef2aSThomas Huth                     }
3265fcf5ef2aSThomas Huth #else
3266fcf5ef2aSThomas Huth                     gen_compare(&cmp, 0, cond, dc);
3267fcf5ef2aSThomas Huth #endif
3268fcf5ef2aSThomas Huth                     l1 = gen_new_label();
3269fcf5ef2aSThomas Huth                     tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3270fcf5ef2aSThomas Huth                                       cmp.c1, cmp.c2, l1);
3271fcf5ef2aSThomas Huth                     free_compare(&cmp);
3272fcf5ef2aSThomas Huth                 }
3273fcf5ef2aSThomas Huth 
3274fcf5ef2aSThomas Huth                 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3275fcf5ef2aSThomas Huth                         ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3276fcf5ef2aSThomas Huth 
3277fcf5ef2aSThomas Huth                 /* Don't use the normal temporaries, as they may well have
3278fcf5ef2aSThomas Huth                    gone out of scope with the branch above.  While we're
3279fcf5ef2aSThomas Huth                    doing that we might as well pre-truncate to 32-bit.  */
3280fcf5ef2aSThomas Huth                 trap = tcg_temp_new_i32();
3281fcf5ef2aSThomas Huth 
3282fcf5ef2aSThomas Huth                 rs1 = GET_FIELD_SP(insn, 14, 18);
3283fcf5ef2aSThomas Huth                 if (IS_IMM) {
32845c65df36SArtyom Tarasenko                     rs2 = GET_FIELD_SP(insn, 0, 7);
3285fcf5ef2aSThomas Huth                     if (rs1 == 0) {
3286fcf5ef2aSThomas Huth                         tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3287fcf5ef2aSThomas Huth                         /* Signal that the trap value is fully constant.  */
3288fcf5ef2aSThomas Huth                         mask = 0;
3289fcf5ef2aSThomas Huth                     } else {
3290fcf5ef2aSThomas Huth                         TCGv t1 = gen_load_gpr(dc, rs1);
3291fcf5ef2aSThomas Huth                         tcg_gen_trunc_tl_i32(trap, t1);
3292fcf5ef2aSThomas Huth                         tcg_gen_addi_i32(trap, trap, rs2);
3293fcf5ef2aSThomas Huth                     }
3294fcf5ef2aSThomas Huth                 } else {
3295fcf5ef2aSThomas Huth                     TCGv t1, t2;
3296fcf5ef2aSThomas Huth                     rs2 = GET_FIELD_SP(insn, 0, 4);
3297fcf5ef2aSThomas Huth                     t1 = gen_load_gpr(dc, rs1);
3298fcf5ef2aSThomas Huth                     t2 = gen_load_gpr(dc, rs2);
3299fcf5ef2aSThomas Huth                     tcg_gen_add_tl(t1, t1, t2);
3300fcf5ef2aSThomas Huth                     tcg_gen_trunc_tl_i32(trap, t1);
3301fcf5ef2aSThomas Huth                 }
3302fcf5ef2aSThomas Huth                 if (mask != 0) {
3303fcf5ef2aSThomas Huth                     tcg_gen_andi_i32(trap, trap, mask);
3304fcf5ef2aSThomas Huth                     tcg_gen_addi_i32(trap, trap, TT_TRAP);
3305fcf5ef2aSThomas Huth                 }
3306fcf5ef2aSThomas Huth 
3307fcf5ef2aSThomas Huth                 gen_helper_raise_exception(cpu_env, trap);
3308fcf5ef2aSThomas Huth                 tcg_temp_free_i32(trap);
3309fcf5ef2aSThomas Huth 
3310fcf5ef2aSThomas Huth                 if (cond == 8) {
3311fcf5ef2aSThomas Huth                     /* An unconditional trap ends the TB.  */
3312af00be49SEmilio G. Cota                     dc->base.is_jmp = DISAS_NORETURN;
3313fcf5ef2aSThomas Huth                     goto jmp_insn;
3314fcf5ef2aSThomas Huth                 } else {
3315fcf5ef2aSThomas Huth                     /* A conditional trap falls through to the next insn.  */
3316fcf5ef2aSThomas Huth                     gen_set_label(l1);
3317fcf5ef2aSThomas Huth                     break;
3318fcf5ef2aSThomas Huth                 }
3319fcf5ef2aSThomas Huth             } else if (xop == 0x28) {
3320fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3321fcf5ef2aSThomas Huth                 switch(rs1) {
3322fcf5ef2aSThomas Huth                 case 0: /* rdy */
3323fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
3324fcf5ef2aSThomas Huth                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3325fcf5ef2aSThomas Huth                                        manual, rdy on the microSPARC
3326fcf5ef2aSThomas Huth                                        II */
3327fcf5ef2aSThomas Huth                 case 0x0f:          /* stbar in the SPARCv8 manual,
3328fcf5ef2aSThomas Huth                                        rdy on the microSPARC II */
3329fcf5ef2aSThomas Huth                 case 0x10 ... 0x1f: /* implementation-dependent in the
3330fcf5ef2aSThomas Huth                                        SPARCv8 manual, rdy on the
3331fcf5ef2aSThomas Huth                                        microSPARC II */
3332fcf5ef2aSThomas Huth                     /* Read Asr17 */
3333fcf5ef2aSThomas Huth                     if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
3334fcf5ef2aSThomas Huth                         TCGv t = gen_dest_gpr(dc, rd);
3335fcf5ef2aSThomas Huth                         /* Read Asr17 for a Leon3 monoprocessor */
3336fcf5ef2aSThomas Huth                         tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3337fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, t);
3338fcf5ef2aSThomas Huth                         break;
3339fcf5ef2aSThomas Huth                     }
3340fcf5ef2aSThomas Huth #endif
3341fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_y);
3342fcf5ef2aSThomas Huth                     break;
3343fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3344fcf5ef2aSThomas Huth                 case 0x2: /* V9 rdccr */
3345fcf5ef2aSThomas Huth                     update_psr(dc);
3346fcf5ef2aSThomas Huth                     gen_helper_rdccr(cpu_dst, cpu_env);
3347fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
3348fcf5ef2aSThomas Huth                     break;
3349fcf5ef2aSThomas Huth                 case 0x3: /* V9 rdasi */
3350fcf5ef2aSThomas Huth                     tcg_gen_movi_tl(cpu_dst, dc->asi);
3351fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
3352fcf5ef2aSThomas Huth                     break;
3353fcf5ef2aSThomas Huth                 case 0x4: /* V9 rdtick */
3354fcf5ef2aSThomas Huth                     {
3355fcf5ef2aSThomas Huth                         TCGv_ptr r_tickptr;
3356fcf5ef2aSThomas Huth                         TCGv_i32 r_const;
3357fcf5ef2aSThomas Huth 
3358fcf5ef2aSThomas Huth                         r_tickptr = tcg_temp_new_ptr();
3359fcf5ef2aSThomas Huth                         r_const = tcg_const_i32(dc->mem_idx);
3360fcf5ef2aSThomas Huth                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
3361fcf5ef2aSThomas Huth                                        offsetof(CPUSPARCState, tick));
336246bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
336346bb0137SMark Cave-Ayland                             gen_io_start();
336446bb0137SMark Cave-Ayland                         }
3365fcf5ef2aSThomas Huth                         gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3366fcf5ef2aSThomas Huth                                                   r_const);
3367fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tickptr);
3368fcf5ef2aSThomas Huth                         tcg_temp_free_i32(r_const);
3369fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
337046bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3371b5328172SPeter Maydell                             /* I/O operations in icount mode must end the TB */
3372b5328172SPeter Maydell                             dc->base.is_jmp = DISAS_EXIT;
337346bb0137SMark Cave-Ayland                         }
3374fcf5ef2aSThomas Huth                     }
3375fcf5ef2aSThomas Huth                     break;
3376fcf5ef2aSThomas Huth                 case 0x5: /* V9 rdpc */
3377fcf5ef2aSThomas Huth                     {
3378fcf5ef2aSThomas Huth                         TCGv t = gen_dest_gpr(dc, rd);
3379fcf5ef2aSThomas Huth                         if (unlikely(AM_CHECK(dc))) {
3380fcf5ef2aSThomas Huth                             tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
3381fcf5ef2aSThomas Huth                         } else {
3382fcf5ef2aSThomas Huth                             tcg_gen_movi_tl(t, dc->pc);
3383fcf5ef2aSThomas Huth                         }
3384fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, t);
3385fcf5ef2aSThomas Huth                     }
3386fcf5ef2aSThomas Huth                     break;
3387fcf5ef2aSThomas Huth                 case 0x6: /* V9 rdfprs */
3388fcf5ef2aSThomas Huth                     tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
3389fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
3390fcf5ef2aSThomas Huth                     break;
3391fcf5ef2aSThomas Huth                 case 0xf: /* V9 membar */
3392fcf5ef2aSThomas Huth                     break; /* no effect */
3393fcf5ef2aSThomas Huth                 case 0x13: /* Graphics Status */
3394fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
3395fcf5ef2aSThomas Huth                         goto jmp_insn;
3396fcf5ef2aSThomas Huth                     }
3397fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_gsr);
3398fcf5ef2aSThomas Huth                     break;
3399fcf5ef2aSThomas Huth                 case 0x16: /* Softint */
3400fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3401fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, softint));
3402fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
3403fcf5ef2aSThomas Huth                     break;
3404fcf5ef2aSThomas Huth                 case 0x17: /* Tick compare */
3405fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_tick_cmpr);
3406fcf5ef2aSThomas Huth                     break;
3407fcf5ef2aSThomas Huth                 case 0x18: /* System tick */
3408fcf5ef2aSThomas Huth                     {
3409fcf5ef2aSThomas Huth                         TCGv_ptr r_tickptr;
3410fcf5ef2aSThomas Huth                         TCGv_i32 r_const;
3411fcf5ef2aSThomas Huth 
3412fcf5ef2aSThomas Huth                         r_tickptr = tcg_temp_new_ptr();
3413fcf5ef2aSThomas Huth                         r_const = tcg_const_i32(dc->mem_idx);
3414fcf5ef2aSThomas Huth                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
3415fcf5ef2aSThomas Huth                                        offsetof(CPUSPARCState, stick));
341646bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
341746bb0137SMark Cave-Ayland                             gen_io_start();
341846bb0137SMark Cave-Ayland                         }
3419fcf5ef2aSThomas Huth                         gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3420fcf5ef2aSThomas Huth                                                   r_const);
3421fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tickptr);
3422fcf5ef2aSThomas Huth                         tcg_temp_free_i32(r_const);
3423fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
342446bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3425b5328172SPeter Maydell                             /* I/O operations in icount mode must end the TB */
3426b5328172SPeter Maydell                             dc->base.is_jmp = DISAS_EXIT;
342746bb0137SMark Cave-Ayland                         }
3428fcf5ef2aSThomas Huth                     }
3429fcf5ef2aSThomas Huth                     break;
3430fcf5ef2aSThomas Huth                 case 0x19: /* System tick compare */
3431fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_stick_cmpr);
3432fcf5ef2aSThomas Huth                     break;
3433b8e31b3cSArtyom Tarasenko                 case 0x1a: /* UltraSPARC-T1 Strand status */
3434b8e31b3cSArtyom Tarasenko                     /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3435b8e31b3cSArtyom Tarasenko                      * this ASR as impl. dep
3436b8e31b3cSArtyom Tarasenko                      */
3437b8e31b3cSArtyom Tarasenko                     CHECK_IU_FEATURE(dc, HYPV);
3438b8e31b3cSArtyom Tarasenko                     {
3439b8e31b3cSArtyom Tarasenko                         TCGv t = gen_dest_gpr(dc, rd);
3440b8e31b3cSArtyom Tarasenko                         tcg_gen_movi_tl(t, 1UL);
3441b8e31b3cSArtyom Tarasenko                         gen_store_gpr(dc, rd, t);
3442b8e31b3cSArtyom Tarasenko                     }
3443b8e31b3cSArtyom Tarasenko                     break;
3444fcf5ef2aSThomas Huth                 case 0x10: /* Performance Control */
3445fcf5ef2aSThomas Huth                 case 0x11: /* Performance Instrumentation Counter */
3446fcf5ef2aSThomas Huth                 case 0x12: /* Dispatch Control */
3447fcf5ef2aSThomas Huth                 case 0x14: /* Softint set, WO */
3448fcf5ef2aSThomas Huth                 case 0x15: /* Softint clear, WO */
3449fcf5ef2aSThomas Huth #endif
3450fcf5ef2aSThomas Huth                 default:
3451fcf5ef2aSThomas Huth                     goto illegal_insn;
3452fcf5ef2aSThomas Huth                 }
3453fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
3454fcf5ef2aSThomas Huth             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3455fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
3456fcf5ef2aSThomas Huth                 if (!supervisor(dc)) {
3457fcf5ef2aSThomas Huth                     goto priv_insn;
3458fcf5ef2aSThomas Huth                 }
3459fcf5ef2aSThomas Huth                 update_psr(dc);
3460fcf5ef2aSThomas Huth                 gen_helper_rdpsr(cpu_dst, cpu_env);
3461fcf5ef2aSThomas Huth #else
3462fcf5ef2aSThomas Huth                 CHECK_IU_FEATURE(dc, HYPV);
3463fcf5ef2aSThomas Huth                 if (!hypervisor(dc))
3464fcf5ef2aSThomas Huth                     goto priv_insn;
3465fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3466fcf5ef2aSThomas Huth                 switch (rs1) {
3467fcf5ef2aSThomas Huth                 case 0: // hpstate
3468f7f17ef7SArtyom Tarasenko                     tcg_gen_ld_i64(cpu_dst, cpu_env,
3469f7f17ef7SArtyom Tarasenko                                    offsetof(CPUSPARCState, hpstate));
3470fcf5ef2aSThomas Huth                     break;
3471fcf5ef2aSThomas Huth                 case 1: // htstate
3472fcf5ef2aSThomas Huth                     // gen_op_rdhtstate();
3473fcf5ef2aSThomas Huth                     break;
3474fcf5ef2aSThomas Huth                 case 3: // hintp
3475fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_dst, cpu_hintp);
3476fcf5ef2aSThomas Huth                     break;
3477fcf5ef2aSThomas Huth                 case 5: // htba
3478fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_dst, cpu_htba);
3479fcf5ef2aSThomas Huth                     break;
3480fcf5ef2aSThomas Huth                 case 6: // hver
3481fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_dst, cpu_hver);
3482fcf5ef2aSThomas Huth                     break;
3483fcf5ef2aSThomas Huth                 case 31: // hstick_cmpr
3484fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
3485fcf5ef2aSThomas Huth                     break;
3486fcf5ef2aSThomas Huth                 default:
3487fcf5ef2aSThomas Huth                     goto illegal_insn;
3488fcf5ef2aSThomas Huth                 }
3489fcf5ef2aSThomas Huth #endif
3490fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_dst);
3491fcf5ef2aSThomas Huth                 break;
3492fcf5ef2aSThomas Huth             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
3493fcf5ef2aSThomas Huth                 if (!supervisor(dc)) {
3494fcf5ef2aSThomas Huth                     goto priv_insn;
3495fcf5ef2aSThomas Huth                 }
349652123f14SRichard Henderson                 cpu_tmp0 = tcg_temp_new();
3497fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3498fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3499fcf5ef2aSThomas Huth                 switch (rs1) {
3500fcf5ef2aSThomas Huth                 case 0: // tpc
3501fcf5ef2aSThomas Huth                     {
3502fcf5ef2aSThomas Huth                         TCGv_ptr r_tsptr;
3503fcf5ef2aSThomas Huth 
3504fcf5ef2aSThomas Huth                         r_tsptr = tcg_temp_new_ptr();
3505fcf5ef2aSThomas Huth                         gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3506fcf5ef2aSThomas Huth                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
3507fcf5ef2aSThomas Huth                                       offsetof(trap_state, tpc));
3508fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tsptr);
3509fcf5ef2aSThomas Huth                     }
3510fcf5ef2aSThomas Huth                     break;
3511fcf5ef2aSThomas Huth                 case 1: // tnpc
3512fcf5ef2aSThomas Huth                     {
3513fcf5ef2aSThomas Huth                         TCGv_ptr r_tsptr;
3514fcf5ef2aSThomas Huth 
3515fcf5ef2aSThomas Huth                         r_tsptr = tcg_temp_new_ptr();
3516fcf5ef2aSThomas Huth                         gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3517fcf5ef2aSThomas Huth                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
3518fcf5ef2aSThomas Huth                                       offsetof(trap_state, tnpc));
3519fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tsptr);
3520fcf5ef2aSThomas Huth                     }
3521fcf5ef2aSThomas Huth                     break;
3522fcf5ef2aSThomas Huth                 case 2: // tstate
3523fcf5ef2aSThomas Huth                     {
3524fcf5ef2aSThomas Huth                         TCGv_ptr r_tsptr;
3525fcf5ef2aSThomas Huth 
3526fcf5ef2aSThomas Huth                         r_tsptr = tcg_temp_new_ptr();
3527fcf5ef2aSThomas Huth                         gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3528fcf5ef2aSThomas Huth                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
3529fcf5ef2aSThomas Huth                                       offsetof(trap_state, tstate));
3530fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tsptr);
3531fcf5ef2aSThomas Huth                     }
3532fcf5ef2aSThomas Huth                     break;
3533fcf5ef2aSThomas Huth                 case 3: // tt
3534fcf5ef2aSThomas Huth                     {
3535fcf5ef2aSThomas Huth                         TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3536fcf5ef2aSThomas Huth 
3537fcf5ef2aSThomas Huth                         gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3538fcf5ef2aSThomas Huth                         tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3539fcf5ef2aSThomas Huth                                          offsetof(trap_state, tt));
3540fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tsptr);
3541fcf5ef2aSThomas Huth                     }
3542fcf5ef2aSThomas Huth                     break;
3543fcf5ef2aSThomas Huth                 case 4: // tick
3544fcf5ef2aSThomas Huth                     {
3545fcf5ef2aSThomas Huth                         TCGv_ptr r_tickptr;
3546fcf5ef2aSThomas Huth                         TCGv_i32 r_const;
3547fcf5ef2aSThomas Huth 
3548fcf5ef2aSThomas Huth                         r_tickptr = tcg_temp_new_ptr();
3549fcf5ef2aSThomas Huth                         r_const = tcg_const_i32(dc->mem_idx);
3550fcf5ef2aSThomas Huth                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
3551fcf5ef2aSThomas Huth                                        offsetof(CPUSPARCState, tick));
355246bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
355346bb0137SMark Cave-Ayland                             gen_io_start();
355446bb0137SMark Cave-Ayland                         }
3555fcf5ef2aSThomas Huth                         gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3556fcf5ef2aSThomas Huth                                                   r_tickptr, r_const);
3557fcf5ef2aSThomas Huth                         tcg_temp_free_ptr(r_tickptr);
3558fcf5ef2aSThomas Huth                         tcg_temp_free_i32(r_const);
355946bb0137SMark Cave-Ayland                         if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3560b5328172SPeter Maydell                             /* I/O operations in icount mode must end the TB */
3561b5328172SPeter Maydell                             dc->base.is_jmp = DISAS_EXIT;
356246bb0137SMark Cave-Ayland                         }
3563fcf5ef2aSThomas Huth                     }
3564fcf5ef2aSThomas Huth                     break;
3565fcf5ef2aSThomas Huth                 case 5: // tba
3566fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
3567fcf5ef2aSThomas Huth                     break;
3568fcf5ef2aSThomas Huth                 case 6: // pstate
3569fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3570fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, pstate));
3571fcf5ef2aSThomas Huth                     break;
3572fcf5ef2aSThomas Huth                 case 7: // tl
3573fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3574fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, tl));
3575fcf5ef2aSThomas Huth                     break;
3576fcf5ef2aSThomas Huth                 case 8: // pil
3577fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3578fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, psrpil));
3579fcf5ef2aSThomas Huth                     break;
3580fcf5ef2aSThomas Huth                 case 9: // cwp
3581fcf5ef2aSThomas Huth                     gen_helper_rdcwp(cpu_tmp0, cpu_env);
3582fcf5ef2aSThomas Huth                     break;
3583fcf5ef2aSThomas Huth                 case 10: // cansave
3584fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3585fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, cansave));
3586fcf5ef2aSThomas Huth                     break;
3587fcf5ef2aSThomas Huth                 case 11: // canrestore
3588fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3589fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, canrestore));
3590fcf5ef2aSThomas Huth                     break;
3591fcf5ef2aSThomas Huth                 case 12: // cleanwin
3592fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3593fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, cleanwin));
3594fcf5ef2aSThomas Huth                     break;
3595fcf5ef2aSThomas Huth                 case 13: // otherwin
3596fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3597fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, otherwin));
3598fcf5ef2aSThomas Huth                     break;
3599fcf5ef2aSThomas Huth                 case 14: // wstate
3600fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3601fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, wstate));
3602fcf5ef2aSThomas Huth                     break;
3603fcf5ef2aSThomas Huth                 case 16: // UA2005 gl
3604fcf5ef2aSThomas Huth                     CHECK_IU_FEATURE(dc, GL);
3605fcf5ef2aSThomas Huth                     tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3606fcf5ef2aSThomas Huth                                      offsetof(CPUSPARCState, gl));
3607fcf5ef2aSThomas Huth                     break;
3608fcf5ef2aSThomas Huth                 case 26: // UA2005 strand status
3609fcf5ef2aSThomas Huth                     CHECK_IU_FEATURE(dc, HYPV);
3610fcf5ef2aSThomas Huth                     if (!hypervisor(dc))
3611fcf5ef2aSThomas Huth                         goto priv_insn;
3612fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
3613fcf5ef2aSThomas Huth                     break;
3614fcf5ef2aSThomas Huth                 case 31: // ver
3615fcf5ef2aSThomas Huth                     tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
3616fcf5ef2aSThomas Huth                     break;
3617fcf5ef2aSThomas Huth                 case 15: // fq
3618fcf5ef2aSThomas Huth                 default:
3619fcf5ef2aSThomas Huth                     goto illegal_insn;
3620fcf5ef2aSThomas Huth                 }
3621fcf5ef2aSThomas Huth #else
3622fcf5ef2aSThomas Huth                 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3623fcf5ef2aSThomas Huth #endif
3624fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_tmp0);
3625fcf5ef2aSThomas Huth                 break;
3626aa04c9d9SGiuseppe Musacchio #endif
3627aa04c9d9SGiuseppe Musacchio #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
3628fcf5ef2aSThomas Huth             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3629fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3630fcf5ef2aSThomas Huth                 gen_helper_flushw(cpu_env);
3631fcf5ef2aSThomas Huth #else
3632fcf5ef2aSThomas Huth                 if (!supervisor(dc))
3633fcf5ef2aSThomas Huth                     goto priv_insn;
3634fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_tbr);
3635fcf5ef2aSThomas Huth #endif
3636fcf5ef2aSThomas Huth                 break;
3637fcf5ef2aSThomas Huth #endif
3638fcf5ef2aSThomas Huth             } else if (xop == 0x34) {   /* FPU Operations */
3639fcf5ef2aSThomas Huth                 if (gen_trap_ifnofpu(dc)) {
3640fcf5ef2aSThomas Huth                     goto jmp_insn;
3641fcf5ef2aSThomas Huth                 }
3642fcf5ef2aSThomas Huth                 gen_op_clear_ieee_excp_and_FTT();
3643fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3644fcf5ef2aSThomas Huth                 rs2 = GET_FIELD(insn, 27, 31);
3645fcf5ef2aSThomas Huth                 xop = GET_FIELD(insn, 18, 26);
3646fcf5ef2aSThomas Huth 
3647fcf5ef2aSThomas Huth                 switch (xop) {
3648fcf5ef2aSThomas Huth                 case 0x1: /* fmovs */
3649fcf5ef2aSThomas Huth                     cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3650fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_src1_32);
3651fcf5ef2aSThomas Huth                     break;
3652fcf5ef2aSThomas Huth                 case 0x5: /* fnegs */
3653fcf5ef2aSThomas Huth                     gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
3654fcf5ef2aSThomas Huth                     break;
3655fcf5ef2aSThomas Huth                 case 0x9: /* fabss */
3656fcf5ef2aSThomas Huth                     gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
3657fcf5ef2aSThomas Huth                     break;
3658fcf5ef2aSThomas Huth                 case 0x29: /* fsqrts */
3659fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FSQRT);
3660fcf5ef2aSThomas Huth                     gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
3661fcf5ef2aSThomas Huth                     break;
3662fcf5ef2aSThomas Huth                 case 0x2a: /* fsqrtd */
3663fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FSQRT);
3664fcf5ef2aSThomas Huth                     gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
3665fcf5ef2aSThomas Huth                     break;
3666fcf5ef2aSThomas Huth                 case 0x2b: /* fsqrtq */
3667fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3668fcf5ef2aSThomas Huth                     gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
3669fcf5ef2aSThomas Huth                     break;
3670fcf5ef2aSThomas Huth                 case 0x41: /* fadds */
3671fcf5ef2aSThomas Huth                     gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
3672fcf5ef2aSThomas Huth                     break;
3673fcf5ef2aSThomas Huth                 case 0x42: /* faddd */
3674fcf5ef2aSThomas Huth                     gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
3675fcf5ef2aSThomas Huth                     break;
3676fcf5ef2aSThomas Huth                 case 0x43: /* faddq */
3677fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3678fcf5ef2aSThomas Huth                     gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
3679fcf5ef2aSThomas Huth                     break;
3680fcf5ef2aSThomas Huth                 case 0x45: /* fsubs */
3681fcf5ef2aSThomas Huth                     gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
3682fcf5ef2aSThomas Huth                     break;
3683fcf5ef2aSThomas Huth                 case 0x46: /* fsubd */
3684fcf5ef2aSThomas Huth                     gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
3685fcf5ef2aSThomas Huth                     break;
3686fcf5ef2aSThomas Huth                 case 0x47: /* fsubq */
3687fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3688fcf5ef2aSThomas Huth                     gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
3689fcf5ef2aSThomas Huth                     break;
3690fcf5ef2aSThomas Huth                 case 0x49: /* fmuls */
3691fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FMUL);
3692fcf5ef2aSThomas Huth                     gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
3693fcf5ef2aSThomas Huth                     break;
3694fcf5ef2aSThomas Huth                 case 0x4a: /* fmuld */
3695fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FMUL);
3696fcf5ef2aSThomas Huth                     gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
3697fcf5ef2aSThomas Huth                     break;
3698fcf5ef2aSThomas Huth                 case 0x4b: /* fmulq */
3699fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3700fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FMUL);
3701fcf5ef2aSThomas Huth                     gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
3702fcf5ef2aSThomas Huth                     break;
3703fcf5ef2aSThomas Huth                 case 0x4d: /* fdivs */
3704fcf5ef2aSThomas Huth                     gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
3705fcf5ef2aSThomas Huth                     break;
3706fcf5ef2aSThomas Huth                 case 0x4e: /* fdivd */
3707fcf5ef2aSThomas Huth                     gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
3708fcf5ef2aSThomas Huth                     break;
3709fcf5ef2aSThomas Huth                 case 0x4f: /* fdivq */
3710fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3711fcf5ef2aSThomas Huth                     gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
3712fcf5ef2aSThomas Huth                     break;
3713fcf5ef2aSThomas Huth                 case 0x69: /* fsmuld */
3714fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FSMULD);
3715fcf5ef2aSThomas Huth                     gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
3716fcf5ef2aSThomas Huth                     break;
3717fcf5ef2aSThomas Huth                 case 0x6e: /* fdmulq */
3718fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3719fcf5ef2aSThomas Huth                     gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
3720fcf5ef2aSThomas Huth                     break;
3721fcf5ef2aSThomas Huth                 case 0xc4: /* fitos */
3722fcf5ef2aSThomas Huth                     gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
3723fcf5ef2aSThomas Huth                     break;
3724fcf5ef2aSThomas Huth                 case 0xc6: /* fdtos */
3725fcf5ef2aSThomas Huth                     gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
3726fcf5ef2aSThomas Huth                     break;
3727fcf5ef2aSThomas Huth                 case 0xc7: /* fqtos */
3728fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3729fcf5ef2aSThomas Huth                     gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
3730fcf5ef2aSThomas Huth                     break;
3731fcf5ef2aSThomas Huth                 case 0xc8: /* fitod */
3732fcf5ef2aSThomas Huth                     gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
3733fcf5ef2aSThomas Huth                     break;
3734fcf5ef2aSThomas Huth                 case 0xc9: /* fstod */
3735fcf5ef2aSThomas Huth                     gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
3736fcf5ef2aSThomas Huth                     break;
3737fcf5ef2aSThomas Huth                 case 0xcb: /* fqtod */
3738fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3739fcf5ef2aSThomas Huth                     gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
3740fcf5ef2aSThomas Huth                     break;
3741fcf5ef2aSThomas Huth                 case 0xcc: /* fitoq */
3742fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3743fcf5ef2aSThomas Huth                     gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
3744fcf5ef2aSThomas Huth                     break;
3745fcf5ef2aSThomas Huth                 case 0xcd: /* fstoq */
3746fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3747fcf5ef2aSThomas Huth                     gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
3748fcf5ef2aSThomas Huth                     break;
3749fcf5ef2aSThomas Huth                 case 0xce: /* fdtoq */
3750fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3751fcf5ef2aSThomas Huth                     gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
3752fcf5ef2aSThomas Huth                     break;
3753fcf5ef2aSThomas Huth                 case 0xd1: /* fstoi */
3754fcf5ef2aSThomas Huth                     gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
3755fcf5ef2aSThomas Huth                     break;
3756fcf5ef2aSThomas Huth                 case 0xd2: /* fdtoi */
3757fcf5ef2aSThomas Huth                     gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
3758fcf5ef2aSThomas Huth                     break;
3759fcf5ef2aSThomas Huth                 case 0xd3: /* fqtoi */
3760fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3761fcf5ef2aSThomas Huth                     gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
3762fcf5ef2aSThomas Huth                     break;
3763fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3764fcf5ef2aSThomas Huth                 case 0x2: /* V9 fmovd */
3765fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3766fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_src1_64);
3767fcf5ef2aSThomas Huth                     break;
3768fcf5ef2aSThomas Huth                 case 0x3: /* V9 fmovq */
3769fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3770fcf5ef2aSThomas Huth                     gen_move_Q(dc, rd, rs2);
3771fcf5ef2aSThomas Huth                     break;
3772fcf5ef2aSThomas Huth                 case 0x6: /* V9 fnegd */
3773fcf5ef2aSThomas Huth                     gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
3774fcf5ef2aSThomas Huth                     break;
3775fcf5ef2aSThomas Huth                 case 0x7: /* V9 fnegq */
3776fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3777fcf5ef2aSThomas Huth                     gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
3778fcf5ef2aSThomas Huth                     break;
3779fcf5ef2aSThomas Huth                 case 0xa: /* V9 fabsd */
3780fcf5ef2aSThomas Huth                     gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
3781fcf5ef2aSThomas Huth                     break;
3782fcf5ef2aSThomas Huth                 case 0xb: /* V9 fabsq */
3783fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3784fcf5ef2aSThomas Huth                     gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
3785fcf5ef2aSThomas Huth                     break;
3786fcf5ef2aSThomas Huth                 case 0x81: /* V9 fstox */
3787fcf5ef2aSThomas Huth                     gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
3788fcf5ef2aSThomas Huth                     break;
3789fcf5ef2aSThomas Huth                 case 0x82: /* V9 fdtox */
3790fcf5ef2aSThomas Huth                     gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
3791fcf5ef2aSThomas Huth                     break;
3792fcf5ef2aSThomas Huth                 case 0x83: /* V9 fqtox */
3793fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3794fcf5ef2aSThomas Huth                     gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
3795fcf5ef2aSThomas Huth                     break;
3796fcf5ef2aSThomas Huth                 case 0x84: /* V9 fxtos */
3797fcf5ef2aSThomas Huth                     gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
3798fcf5ef2aSThomas Huth                     break;
3799fcf5ef2aSThomas Huth                 case 0x88: /* V9 fxtod */
3800fcf5ef2aSThomas Huth                     gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
3801fcf5ef2aSThomas Huth                     break;
3802fcf5ef2aSThomas Huth                 case 0x8c: /* V9 fxtoq */
3803fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3804fcf5ef2aSThomas Huth                     gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
3805fcf5ef2aSThomas Huth                     break;
3806fcf5ef2aSThomas Huth #endif
3807fcf5ef2aSThomas Huth                 default:
3808fcf5ef2aSThomas Huth                     goto illegal_insn;
3809fcf5ef2aSThomas Huth                 }
3810fcf5ef2aSThomas Huth             } else if (xop == 0x35) {   /* FPU Operations */
3811fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3812fcf5ef2aSThomas Huth                 int cond;
3813fcf5ef2aSThomas Huth #endif
3814fcf5ef2aSThomas Huth                 if (gen_trap_ifnofpu(dc)) {
3815fcf5ef2aSThomas Huth                     goto jmp_insn;
3816fcf5ef2aSThomas Huth                 }
3817fcf5ef2aSThomas Huth                 gen_op_clear_ieee_excp_and_FTT();
3818fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3819fcf5ef2aSThomas Huth                 rs2 = GET_FIELD(insn, 27, 31);
3820fcf5ef2aSThomas Huth                 xop = GET_FIELD(insn, 18, 26);
3821fcf5ef2aSThomas Huth 
3822fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3823fcf5ef2aSThomas Huth #define FMOVR(sz)                                                  \
3824fcf5ef2aSThomas Huth                 do {                                               \
3825fcf5ef2aSThomas Huth                     DisasCompare cmp;                              \
3826fcf5ef2aSThomas Huth                     cond = GET_FIELD_SP(insn, 10, 12);             \
3827fcf5ef2aSThomas Huth                     cpu_src1 = get_src1(dc, insn);                 \
3828fcf5ef2aSThomas Huth                     gen_compare_reg(&cmp, cond, cpu_src1);         \
3829fcf5ef2aSThomas Huth                     gen_fmov##sz(dc, &cmp, rd, rs2);               \
3830fcf5ef2aSThomas Huth                     free_compare(&cmp);                            \
3831fcf5ef2aSThomas Huth                 } while (0)
3832fcf5ef2aSThomas Huth 
3833fcf5ef2aSThomas Huth                 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3834fcf5ef2aSThomas Huth                     FMOVR(s);
3835fcf5ef2aSThomas Huth                     break;
3836fcf5ef2aSThomas Huth                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
3837fcf5ef2aSThomas Huth                     FMOVR(d);
3838fcf5ef2aSThomas Huth                     break;
3839fcf5ef2aSThomas Huth                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
3840fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
3841fcf5ef2aSThomas Huth                     FMOVR(q);
3842fcf5ef2aSThomas Huth                     break;
3843fcf5ef2aSThomas Huth                 }
3844fcf5ef2aSThomas Huth #undef FMOVR
3845fcf5ef2aSThomas Huth #endif
3846fcf5ef2aSThomas Huth                 switch (xop) {
3847fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
3848fcf5ef2aSThomas Huth #define FMOVCC(fcc, sz)                                                 \
3849fcf5ef2aSThomas Huth                     do {                                                \
3850fcf5ef2aSThomas Huth                         DisasCompare cmp;                               \
3851fcf5ef2aSThomas Huth                         cond = GET_FIELD_SP(insn, 14, 17);              \
3852fcf5ef2aSThomas Huth                         gen_fcompare(&cmp, fcc, cond);                  \
3853fcf5ef2aSThomas Huth                         gen_fmov##sz(dc, &cmp, rd, rs2);                \
3854fcf5ef2aSThomas Huth                         free_compare(&cmp);                             \
3855fcf5ef2aSThomas Huth                     } while (0)
3856fcf5ef2aSThomas Huth 
3857fcf5ef2aSThomas Huth                     case 0x001: /* V9 fmovscc %fcc0 */
3858fcf5ef2aSThomas Huth                         FMOVCC(0, s);
3859fcf5ef2aSThomas Huth                         break;
3860fcf5ef2aSThomas Huth                     case 0x002: /* V9 fmovdcc %fcc0 */
3861fcf5ef2aSThomas Huth                         FMOVCC(0, d);
3862fcf5ef2aSThomas Huth                         break;
3863fcf5ef2aSThomas Huth                     case 0x003: /* V9 fmovqcc %fcc0 */
3864fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3865fcf5ef2aSThomas Huth                         FMOVCC(0, q);
3866fcf5ef2aSThomas Huth                         break;
3867fcf5ef2aSThomas Huth                     case 0x041: /* V9 fmovscc %fcc1 */
3868fcf5ef2aSThomas Huth                         FMOVCC(1, s);
3869fcf5ef2aSThomas Huth                         break;
3870fcf5ef2aSThomas Huth                     case 0x042: /* V9 fmovdcc %fcc1 */
3871fcf5ef2aSThomas Huth                         FMOVCC(1, d);
3872fcf5ef2aSThomas Huth                         break;
3873fcf5ef2aSThomas Huth                     case 0x043: /* V9 fmovqcc %fcc1 */
3874fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3875fcf5ef2aSThomas Huth                         FMOVCC(1, q);
3876fcf5ef2aSThomas Huth                         break;
3877fcf5ef2aSThomas Huth                     case 0x081: /* V9 fmovscc %fcc2 */
3878fcf5ef2aSThomas Huth                         FMOVCC(2, s);
3879fcf5ef2aSThomas Huth                         break;
3880fcf5ef2aSThomas Huth                     case 0x082: /* V9 fmovdcc %fcc2 */
3881fcf5ef2aSThomas Huth                         FMOVCC(2, d);
3882fcf5ef2aSThomas Huth                         break;
3883fcf5ef2aSThomas Huth                     case 0x083: /* V9 fmovqcc %fcc2 */
3884fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3885fcf5ef2aSThomas Huth                         FMOVCC(2, q);
3886fcf5ef2aSThomas Huth                         break;
3887fcf5ef2aSThomas Huth                     case 0x0c1: /* V9 fmovscc %fcc3 */
3888fcf5ef2aSThomas Huth                         FMOVCC(3, s);
3889fcf5ef2aSThomas Huth                         break;
3890fcf5ef2aSThomas Huth                     case 0x0c2: /* V9 fmovdcc %fcc3 */
3891fcf5ef2aSThomas Huth                         FMOVCC(3, d);
3892fcf5ef2aSThomas Huth                         break;
3893fcf5ef2aSThomas Huth                     case 0x0c3: /* V9 fmovqcc %fcc3 */
3894fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3895fcf5ef2aSThomas Huth                         FMOVCC(3, q);
3896fcf5ef2aSThomas Huth                         break;
3897fcf5ef2aSThomas Huth #undef FMOVCC
3898fcf5ef2aSThomas Huth #define FMOVCC(xcc, sz)                                                 \
3899fcf5ef2aSThomas Huth                     do {                                                \
3900fcf5ef2aSThomas Huth                         DisasCompare cmp;                               \
3901fcf5ef2aSThomas Huth                         cond = GET_FIELD_SP(insn, 14, 17);              \
3902fcf5ef2aSThomas Huth                         gen_compare(&cmp, xcc, cond, dc);               \
3903fcf5ef2aSThomas Huth                         gen_fmov##sz(dc, &cmp, rd, rs2);                \
3904fcf5ef2aSThomas Huth                         free_compare(&cmp);                             \
3905fcf5ef2aSThomas Huth                     } while (0)
3906fcf5ef2aSThomas Huth 
3907fcf5ef2aSThomas Huth                     case 0x101: /* V9 fmovscc %icc */
3908fcf5ef2aSThomas Huth                         FMOVCC(0, s);
3909fcf5ef2aSThomas Huth                         break;
3910fcf5ef2aSThomas Huth                     case 0x102: /* V9 fmovdcc %icc */
3911fcf5ef2aSThomas Huth                         FMOVCC(0, d);
3912fcf5ef2aSThomas Huth                         break;
3913fcf5ef2aSThomas Huth                     case 0x103: /* V9 fmovqcc %icc */
3914fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3915fcf5ef2aSThomas Huth                         FMOVCC(0, q);
3916fcf5ef2aSThomas Huth                         break;
3917fcf5ef2aSThomas Huth                     case 0x181: /* V9 fmovscc %xcc */
3918fcf5ef2aSThomas Huth                         FMOVCC(1, s);
3919fcf5ef2aSThomas Huth                         break;
3920fcf5ef2aSThomas Huth                     case 0x182: /* V9 fmovdcc %xcc */
3921fcf5ef2aSThomas Huth                         FMOVCC(1, d);
3922fcf5ef2aSThomas Huth                         break;
3923fcf5ef2aSThomas Huth                     case 0x183: /* V9 fmovqcc %xcc */
3924fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3925fcf5ef2aSThomas Huth                         FMOVCC(1, q);
3926fcf5ef2aSThomas Huth                         break;
3927fcf5ef2aSThomas Huth #undef FMOVCC
3928fcf5ef2aSThomas Huth #endif
3929fcf5ef2aSThomas Huth                     case 0x51: /* fcmps, V9 %fcc */
3930fcf5ef2aSThomas Huth                         cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3931fcf5ef2aSThomas Huth                         cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3932fcf5ef2aSThomas Huth                         gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
3933fcf5ef2aSThomas Huth                         break;
3934fcf5ef2aSThomas Huth                     case 0x52: /* fcmpd, V9 %fcc */
3935fcf5ef2aSThomas Huth                         cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3936fcf5ef2aSThomas Huth                         cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3937fcf5ef2aSThomas Huth                         gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
3938fcf5ef2aSThomas Huth                         break;
3939fcf5ef2aSThomas Huth                     case 0x53: /* fcmpq, V9 %fcc */
3940fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3941fcf5ef2aSThomas Huth                         gen_op_load_fpr_QT0(QFPREG(rs1));
3942fcf5ef2aSThomas Huth                         gen_op_load_fpr_QT1(QFPREG(rs2));
3943fcf5ef2aSThomas Huth                         gen_op_fcmpq(rd & 3);
3944fcf5ef2aSThomas Huth                         break;
3945fcf5ef2aSThomas Huth                     case 0x55: /* fcmpes, V9 %fcc */
3946fcf5ef2aSThomas Huth                         cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3947fcf5ef2aSThomas Huth                         cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3948fcf5ef2aSThomas Huth                         gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
3949fcf5ef2aSThomas Huth                         break;
3950fcf5ef2aSThomas Huth                     case 0x56: /* fcmped, V9 %fcc */
3951fcf5ef2aSThomas Huth                         cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3952fcf5ef2aSThomas Huth                         cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3953fcf5ef2aSThomas Huth                         gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
3954fcf5ef2aSThomas Huth                         break;
3955fcf5ef2aSThomas Huth                     case 0x57: /* fcmpeq, V9 %fcc */
3956fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
3957fcf5ef2aSThomas Huth                         gen_op_load_fpr_QT0(QFPREG(rs1));
3958fcf5ef2aSThomas Huth                         gen_op_load_fpr_QT1(QFPREG(rs2));
3959fcf5ef2aSThomas Huth                         gen_op_fcmpeq(rd & 3);
3960fcf5ef2aSThomas Huth                         break;
3961fcf5ef2aSThomas Huth                     default:
3962fcf5ef2aSThomas Huth                         goto illegal_insn;
3963fcf5ef2aSThomas Huth                 }
3964fcf5ef2aSThomas Huth             } else if (xop == 0x2) {
3965fcf5ef2aSThomas Huth                 TCGv dst = gen_dest_gpr(dc, rd);
3966fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
3967fcf5ef2aSThomas Huth                 if (rs1 == 0) {
3968fcf5ef2aSThomas Huth                     /* clr/mov shortcut : or %g0, x, y -> mov x, y */
3969fcf5ef2aSThomas Huth                     if (IS_IMM) {       /* immediate */
3970fcf5ef2aSThomas Huth                         simm = GET_FIELDs(insn, 19, 31);
3971fcf5ef2aSThomas Huth                         tcg_gen_movi_tl(dst, simm);
3972fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, dst);
3973fcf5ef2aSThomas Huth                     } else {            /* register */
3974fcf5ef2aSThomas Huth                         rs2 = GET_FIELD(insn, 27, 31);
3975fcf5ef2aSThomas Huth                         if (rs2 == 0) {
3976fcf5ef2aSThomas Huth                             tcg_gen_movi_tl(dst, 0);
3977fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, dst);
3978fcf5ef2aSThomas Huth                         } else {
3979fcf5ef2aSThomas Huth                             cpu_src2 = gen_load_gpr(dc, rs2);
3980fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, cpu_src2);
3981fcf5ef2aSThomas Huth                         }
3982fcf5ef2aSThomas Huth                     }
3983fcf5ef2aSThomas Huth                 } else {
3984fcf5ef2aSThomas Huth                     cpu_src1 = get_src1(dc, insn);
3985fcf5ef2aSThomas Huth                     if (IS_IMM) {       /* immediate */
3986fcf5ef2aSThomas Huth                         simm = GET_FIELDs(insn, 19, 31);
3987fcf5ef2aSThomas Huth                         tcg_gen_ori_tl(dst, cpu_src1, simm);
3988fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, dst);
3989fcf5ef2aSThomas Huth                     } else {            /* register */
3990fcf5ef2aSThomas Huth                         rs2 = GET_FIELD(insn, 27, 31);
3991fcf5ef2aSThomas Huth                         if (rs2 == 0) {
3992fcf5ef2aSThomas Huth                             /* mov shortcut:  or x, %g0, y -> mov x, y */
3993fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, cpu_src1);
3994fcf5ef2aSThomas Huth                         } else {
3995fcf5ef2aSThomas Huth                             cpu_src2 = gen_load_gpr(dc, rs2);
3996fcf5ef2aSThomas Huth                             tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3997fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, dst);
3998fcf5ef2aSThomas Huth                         }
3999fcf5ef2aSThomas Huth                     }
4000fcf5ef2aSThomas Huth                 }
4001fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4002fcf5ef2aSThomas Huth             } else if (xop == 0x25) { /* sll, V9 sllx */
4003fcf5ef2aSThomas Huth                 cpu_src1 = get_src1(dc, insn);
4004fcf5ef2aSThomas Huth                 if (IS_IMM) {   /* immediate */
4005fcf5ef2aSThomas Huth                     simm = GET_FIELDs(insn, 20, 31);
4006fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4007fcf5ef2aSThomas Huth                         tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
4008fcf5ef2aSThomas Huth                     } else {
4009fcf5ef2aSThomas Huth                         tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
4010fcf5ef2aSThomas Huth                     }
4011fcf5ef2aSThomas Huth                 } else {                /* register */
4012fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
4013fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
401452123f14SRichard Henderson                     cpu_tmp0 = tcg_temp_new();
4015fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4016fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4017fcf5ef2aSThomas Huth                     } else {
4018fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4019fcf5ef2aSThomas Huth                     }
4020fcf5ef2aSThomas Huth                     tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
4021fcf5ef2aSThomas Huth                 }
4022fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_dst);
4023fcf5ef2aSThomas Huth             } else if (xop == 0x26) { /* srl, V9 srlx */
4024fcf5ef2aSThomas Huth                 cpu_src1 = get_src1(dc, insn);
4025fcf5ef2aSThomas Huth                 if (IS_IMM) {   /* immediate */
4026fcf5ef2aSThomas Huth                     simm = GET_FIELDs(insn, 20, 31);
4027fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4028fcf5ef2aSThomas Huth                         tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
4029fcf5ef2aSThomas Huth                     } else {
4030fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4031fcf5ef2aSThomas Huth                         tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
4032fcf5ef2aSThomas Huth                     }
4033fcf5ef2aSThomas Huth                 } else {                /* register */
4034fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
4035fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
403652123f14SRichard Henderson                     cpu_tmp0 = tcg_temp_new();
4037fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4038fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4039fcf5ef2aSThomas Huth                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
4040fcf5ef2aSThomas Huth                     } else {
4041fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4042fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4043fcf5ef2aSThomas Huth                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
4044fcf5ef2aSThomas Huth                     }
4045fcf5ef2aSThomas Huth                 }
4046fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_dst);
4047fcf5ef2aSThomas Huth             } else if (xop == 0x27) { /* sra, V9 srax */
4048fcf5ef2aSThomas Huth                 cpu_src1 = get_src1(dc, insn);
4049fcf5ef2aSThomas Huth                 if (IS_IMM) {   /* immediate */
4050fcf5ef2aSThomas Huth                     simm = GET_FIELDs(insn, 20, 31);
4051fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4052fcf5ef2aSThomas Huth                         tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
4053fcf5ef2aSThomas Huth                     } else {
4054fcf5ef2aSThomas Huth                         tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
4055fcf5ef2aSThomas Huth                         tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
4056fcf5ef2aSThomas Huth                     }
4057fcf5ef2aSThomas Huth                 } else {                /* register */
4058fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
4059fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
406052123f14SRichard Henderson                     cpu_tmp0 = tcg_temp_new();
4061fcf5ef2aSThomas Huth                     if (insn & (1 << 12)) {
4062fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4063fcf5ef2aSThomas Huth                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
4064fcf5ef2aSThomas Huth                     } else {
4065fcf5ef2aSThomas Huth                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4066fcf5ef2aSThomas Huth                         tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
4067fcf5ef2aSThomas Huth                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
4068fcf5ef2aSThomas Huth                     }
4069fcf5ef2aSThomas Huth                 }
4070fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_dst);
4071fcf5ef2aSThomas Huth #endif
4072fcf5ef2aSThomas Huth             } else if (xop < 0x36) {
4073fcf5ef2aSThomas Huth                 if (xop < 0x20) {
4074fcf5ef2aSThomas Huth                     cpu_src1 = get_src1(dc, insn);
4075fcf5ef2aSThomas Huth                     cpu_src2 = get_src2(dc, insn);
4076fcf5ef2aSThomas Huth                     switch (xop & ~0x10) {
4077fcf5ef2aSThomas Huth                     case 0x0: /* add */
4078fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4079fcf5ef2aSThomas Huth                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4080fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4081fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_ADD;
4082fcf5ef2aSThomas Huth                         } else {
4083fcf5ef2aSThomas Huth                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4084fcf5ef2aSThomas Huth                         }
4085fcf5ef2aSThomas Huth                         break;
4086fcf5ef2aSThomas Huth                     case 0x1: /* and */
4087fcf5ef2aSThomas Huth                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
4088fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4089fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4090fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4091fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4092fcf5ef2aSThomas Huth                         }
4093fcf5ef2aSThomas Huth                         break;
4094fcf5ef2aSThomas Huth                     case 0x2: /* or */
4095fcf5ef2aSThomas Huth                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
4096fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4097fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4098fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4099fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4100fcf5ef2aSThomas Huth                         }
4101fcf5ef2aSThomas Huth                         break;
4102fcf5ef2aSThomas Huth                     case 0x3: /* xor */
4103fcf5ef2aSThomas Huth                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
4104fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4105fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4106fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4107fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4108fcf5ef2aSThomas Huth                         }
4109fcf5ef2aSThomas Huth                         break;
4110fcf5ef2aSThomas Huth                     case 0x4: /* sub */
4111fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4112fcf5ef2aSThomas Huth                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4113fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4114fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_SUB;
4115fcf5ef2aSThomas Huth                         } else {
4116fcf5ef2aSThomas Huth                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
4117fcf5ef2aSThomas Huth                         }
4118fcf5ef2aSThomas Huth                         break;
4119fcf5ef2aSThomas Huth                     case 0x5: /* andn */
4120fcf5ef2aSThomas Huth                         tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
4121fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4122fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4123fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4124fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4125fcf5ef2aSThomas Huth                         }
4126fcf5ef2aSThomas Huth                         break;
4127fcf5ef2aSThomas Huth                     case 0x6: /* orn */
4128fcf5ef2aSThomas Huth                         tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
4129fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4130fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4131fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4132fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4133fcf5ef2aSThomas Huth                         }
4134fcf5ef2aSThomas Huth                         break;
4135fcf5ef2aSThomas Huth                     case 0x7: /* xorn */
4136fcf5ef2aSThomas Huth                         tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
4137fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4138fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4139fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4140fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4141fcf5ef2aSThomas Huth                         }
4142fcf5ef2aSThomas Huth                         break;
4143fcf5ef2aSThomas Huth                     case 0x8: /* addx, V9 addc */
4144fcf5ef2aSThomas Huth                         gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4145fcf5ef2aSThomas Huth                                         (xop & 0x10));
4146fcf5ef2aSThomas Huth                         break;
4147fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4148fcf5ef2aSThomas Huth                     case 0x9: /* V9 mulx */
4149fcf5ef2aSThomas Huth                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
4150fcf5ef2aSThomas Huth                         break;
4151fcf5ef2aSThomas Huth #endif
4152fcf5ef2aSThomas Huth                     case 0xa: /* umul */
4153fcf5ef2aSThomas Huth                         CHECK_IU_FEATURE(dc, MUL);
4154fcf5ef2aSThomas Huth                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
4155fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4156fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4157fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4158fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4159fcf5ef2aSThomas Huth                         }
4160fcf5ef2aSThomas Huth                         break;
4161fcf5ef2aSThomas Huth                     case 0xb: /* smul */
4162fcf5ef2aSThomas Huth                         CHECK_IU_FEATURE(dc, MUL);
4163fcf5ef2aSThomas Huth                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
4164fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4165fcf5ef2aSThomas Huth                             tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4166fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4167fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_LOGIC;
4168fcf5ef2aSThomas Huth                         }
4169fcf5ef2aSThomas Huth                         break;
4170fcf5ef2aSThomas Huth                     case 0xc: /* subx, V9 subc */
4171fcf5ef2aSThomas Huth                         gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4172fcf5ef2aSThomas Huth                                         (xop & 0x10));
4173fcf5ef2aSThomas Huth                         break;
4174fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4175fcf5ef2aSThomas Huth                     case 0xd: /* V9 udivx */
4176fcf5ef2aSThomas Huth                         gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
4177fcf5ef2aSThomas Huth                         break;
4178fcf5ef2aSThomas Huth #endif
4179fcf5ef2aSThomas Huth                     case 0xe: /* udiv */
4180fcf5ef2aSThomas Huth                         CHECK_IU_FEATURE(dc, DIV);
4181fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4182fcf5ef2aSThomas Huth                             gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4183fcf5ef2aSThomas Huth                                                cpu_src2);
4184fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_DIV;
4185fcf5ef2aSThomas Huth                         } else {
4186fcf5ef2aSThomas Huth                             gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4187fcf5ef2aSThomas Huth                                             cpu_src2);
4188fcf5ef2aSThomas Huth                         }
4189fcf5ef2aSThomas Huth                         break;
4190fcf5ef2aSThomas Huth                     case 0xf: /* sdiv */
4191fcf5ef2aSThomas Huth                         CHECK_IU_FEATURE(dc, DIV);
4192fcf5ef2aSThomas Huth                         if (xop & 0x10) {
4193fcf5ef2aSThomas Huth                             gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4194fcf5ef2aSThomas Huth                                                cpu_src2);
4195fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_DIV;
4196fcf5ef2aSThomas Huth                         } else {
4197fcf5ef2aSThomas Huth                             gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4198fcf5ef2aSThomas Huth                                             cpu_src2);
4199fcf5ef2aSThomas Huth                         }
4200fcf5ef2aSThomas Huth                         break;
4201fcf5ef2aSThomas Huth                     default:
4202fcf5ef2aSThomas Huth                         goto illegal_insn;
4203fcf5ef2aSThomas Huth                     }
4204fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4205fcf5ef2aSThomas Huth                 } else {
4206fcf5ef2aSThomas Huth                     cpu_src1 = get_src1(dc, insn);
4207fcf5ef2aSThomas Huth                     cpu_src2 = get_src2(dc, insn);
4208fcf5ef2aSThomas Huth                     switch (xop) {
4209fcf5ef2aSThomas Huth                     case 0x20: /* taddcc */
4210fcf5ef2aSThomas Huth                         gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4211fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4212fcf5ef2aSThomas Huth                         tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4213fcf5ef2aSThomas Huth                         dc->cc_op = CC_OP_TADD;
4214fcf5ef2aSThomas Huth                         break;
4215fcf5ef2aSThomas Huth                     case 0x21: /* tsubcc */
4216fcf5ef2aSThomas Huth                         gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4217fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4218fcf5ef2aSThomas Huth                         tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4219fcf5ef2aSThomas Huth                         dc->cc_op = CC_OP_TSUB;
4220fcf5ef2aSThomas Huth                         break;
4221fcf5ef2aSThomas Huth                     case 0x22: /* taddcctv */
4222fcf5ef2aSThomas Huth                         gen_helper_taddcctv(cpu_dst, cpu_env,
4223fcf5ef2aSThomas Huth                                             cpu_src1, cpu_src2);
4224fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4225fcf5ef2aSThomas Huth                         dc->cc_op = CC_OP_TADDTV;
4226fcf5ef2aSThomas Huth                         break;
4227fcf5ef2aSThomas Huth                     case 0x23: /* tsubcctv */
4228fcf5ef2aSThomas Huth                         gen_helper_tsubcctv(cpu_dst, cpu_env,
4229fcf5ef2aSThomas Huth                                             cpu_src1, cpu_src2);
4230fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4231fcf5ef2aSThomas Huth                         dc->cc_op = CC_OP_TSUBTV;
4232fcf5ef2aSThomas Huth                         break;
4233fcf5ef2aSThomas Huth                     case 0x24: /* mulscc */
4234fcf5ef2aSThomas Huth                         update_psr(dc);
4235fcf5ef2aSThomas Huth                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
4236fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4237fcf5ef2aSThomas Huth                         tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4238fcf5ef2aSThomas Huth                         dc->cc_op = CC_OP_ADD;
4239fcf5ef2aSThomas Huth                         break;
4240fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
4241fcf5ef2aSThomas Huth                     case 0x25:  /* sll */
4242fcf5ef2aSThomas Huth                         if (IS_IMM) { /* immediate */
4243fcf5ef2aSThomas Huth                             simm = GET_FIELDs(insn, 20, 31);
4244fcf5ef2aSThomas Huth                             tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
4245fcf5ef2aSThomas Huth                         } else { /* register */
424652123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4247fcf5ef2aSThomas Huth                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4248fcf5ef2aSThomas Huth                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4249fcf5ef2aSThomas Huth                         }
4250fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4251fcf5ef2aSThomas Huth                         break;
4252fcf5ef2aSThomas Huth                     case 0x26:  /* srl */
4253fcf5ef2aSThomas Huth                         if (IS_IMM) { /* immediate */
4254fcf5ef2aSThomas Huth                             simm = GET_FIELDs(insn, 20, 31);
4255fcf5ef2aSThomas Huth                             tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
4256fcf5ef2aSThomas Huth                         } else { /* register */
425752123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4258fcf5ef2aSThomas Huth                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4259fcf5ef2aSThomas Huth                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4260fcf5ef2aSThomas Huth                         }
4261fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4262fcf5ef2aSThomas Huth                         break;
4263fcf5ef2aSThomas Huth                     case 0x27:  /* sra */
4264fcf5ef2aSThomas Huth                         if (IS_IMM) { /* immediate */
4265fcf5ef2aSThomas Huth                             simm = GET_FIELDs(insn, 20, 31);
4266fcf5ef2aSThomas Huth                             tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
4267fcf5ef2aSThomas Huth                         } else { /* register */
426852123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4269fcf5ef2aSThomas Huth                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4270fcf5ef2aSThomas Huth                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4271fcf5ef2aSThomas Huth                         }
4272fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4273fcf5ef2aSThomas Huth                         break;
4274fcf5ef2aSThomas Huth #endif
4275fcf5ef2aSThomas Huth                     case 0x30:
4276fcf5ef2aSThomas Huth                         {
427752123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4278fcf5ef2aSThomas Huth                             switch(rd) {
4279fcf5ef2aSThomas Huth                             case 0: /* wry */
4280fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4281fcf5ef2aSThomas Huth                                 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
4282fcf5ef2aSThomas Huth                                 break;
4283fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
4284fcf5ef2aSThomas Huth                             case 0x01 ... 0x0f: /* undefined in the
4285fcf5ef2aSThomas Huth                                                    SPARCv8 manual, nop
4286fcf5ef2aSThomas Huth                                                    on the microSPARC
4287fcf5ef2aSThomas Huth                                                    II */
4288fcf5ef2aSThomas Huth                             case 0x10 ... 0x1f: /* implementation-dependent
4289fcf5ef2aSThomas Huth                                                    in the SPARCv8
4290fcf5ef2aSThomas Huth                                                    manual, nop on the
4291fcf5ef2aSThomas Huth                                                    microSPARC II */
4292fcf5ef2aSThomas Huth                                 if ((rd == 0x13) && (dc->def->features &
4293fcf5ef2aSThomas Huth                                                      CPU_FEATURE_POWERDOWN)) {
4294fcf5ef2aSThomas Huth                                     /* LEON3 power-down */
4295fcf5ef2aSThomas Huth                                     save_state(dc);
4296fcf5ef2aSThomas Huth                                     gen_helper_power_down(cpu_env);
4297fcf5ef2aSThomas Huth                                 }
4298fcf5ef2aSThomas Huth                                 break;
4299fcf5ef2aSThomas Huth #else
4300fcf5ef2aSThomas Huth                             case 0x2: /* V9 wrccr */
4301fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4302fcf5ef2aSThomas Huth                                 gen_helper_wrccr(cpu_env, cpu_tmp0);
4303fcf5ef2aSThomas Huth                                 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4304fcf5ef2aSThomas Huth                                 dc->cc_op = CC_OP_FLAGS;
4305fcf5ef2aSThomas Huth                                 break;
4306fcf5ef2aSThomas Huth                             case 0x3: /* V9 wrasi */
4307fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4308fcf5ef2aSThomas Huth                                 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
4309fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4310fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState, asi));
4311fcf5ef2aSThomas Huth                                 /* End TB to notice changed ASI.  */
4312fcf5ef2aSThomas Huth                                 save_state(dc);
4313fcf5ef2aSThomas Huth                                 gen_op_next_insn();
431407ea28b4SRichard Henderson                                 tcg_gen_exit_tb(NULL, 0);
4315af00be49SEmilio G. Cota                                 dc->base.is_jmp = DISAS_NORETURN;
4316fcf5ef2aSThomas Huth                                 break;
4317fcf5ef2aSThomas Huth                             case 0x6: /* V9 wrfprs */
4318fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4319fcf5ef2aSThomas Huth                                 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
4320fcf5ef2aSThomas Huth                                 dc->fprs_dirty = 0;
4321fcf5ef2aSThomas Huth                                 save_state(dc);
4322fcf5ef2aSThomas Huth                                 gen_op_next_insn();
432307ea28b4SRichard Henderson                                 tcg_gen_exit_tb(NULL, 0);
4324af00be49SEmilio G. Cota                                 dc->base.is_jmp = DISAS_NORETURN;
4325fcf5ef2aSThomas Huth                                 break;
4326fcf5ef2aSThomas Huth                             case 0xf: /* V9 sir, nop if user */
4327fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
4328fcf5ef2aSThomas Huth                                 if (supervisor(dc)) {
4329fcf5ef2aSThomas Huth                                     ; // XXX
4330fcf5ef2aSThomas Huth                                 }
4331fcf5ef2aSThomas Huth #endif
4332fcf5ef2aSThomas Huth                                 break;
4333fcf5ef2aSThomas Huth                             case 0x13: /* Graphics Status */
4334fcf5ef2aSThomas Huth                                 if (gen_trap_ifnofpu(dc)) {
4335fcf5ef2aSThomas Huth                                     goto jmp_insn;
4336fcf5ef2aSThomas Huth                                 }
4337fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
4338fcf5ef2aSThomas Huth                                 break;
4339fcf5ef2aSThomas Huth                             case 0x14: /* Softint set */
4340fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4341fcf5ef2aSThomas Huth                                     goto illegal_insn;
4342fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4343fcf5ef2aSThomas Huth                                 gen_helper_set_softint(cpu_env, cpu_tmp0);
4344fcf5ef2aSThomas Huth                                 break;
4345fcf5ef2aSThomas Huth                             case 0x15: /* Softint clear */
4346fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4347fcf5ef2aSThomas Huth                                     goto illegal_insn;
4348fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4349fcf5ef2aSThomas Huth                                 gen_helper_clear_softint(cpu_env, cpu_tmp0);
4350fcf5ef2aSThomas Huth                                 break;
4351fcf5ef2aSThomas Huth                             case 0x16: /* Softint write */
4352fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4353fcf5ef2aSThomas Huth                                     goto illegal_insn;
4354fcf5ef2aSThomas Huth                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4355fcf5ef2aSThomas Huth                                 gen_helper_write_softint(cpu_env, cpu_tmp0);
4356fcf5ef2aSThomas Huth                                 break;
4357fcf5ef2aSThomas Huth                             case 0x17: /* Tick compare */
4358fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
4359fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4360fcf5ef2aSThomas Huth                                     goto illegal_insn;
4361fcf5ef2aSThomas Huth #endif
4362fcf5ef2aSThomas Huth                                 {
4363fcf5ef2aSThomas Huth                                     TCGv_ptr r_tickptr;
4364fcf5ef2aSThomas Huth 
4365fcf5ef2aSThomas Huth                                     tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
4366fcf5ef2aSThomas Huth                                                    cpu_src2);
4367fcf5ef2aSThomas Huth                                     r_tickptr = tcg_temp_new_ptr();
4368fcf5ef2aSThomas Huth                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
4369fcf5ef2aSThomas Huth                                                    offsetof(CPUSPARCState, tick));
437046bb0137SMark Cave-Ayland                                     if (tb_cflags(dc->base.tb) &
437146bb0137SMark Cave-Ayland                                            CF_USE_ICOUNT) {
437246bb0137SMark Cave-Ayland                                         gen_io_start();
437346bb0137SMark Cave-Ayland                                     }
4374fcf5ef2aSThomas Huth                                     gen_helper_tick_set_limit(r_tickptr,
4375fcf5ef2aSThomas Huth                                                               cpu_tick_cmpr);
4376fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tickptr);
437746bb0137SMark Cave-Ayland                                     /* End TB to handle timer interrupt */
437846bb0137SMark Cave-Ayland                                     dc->base.is_jmp = DISAS_EXIT;
4379fcf5ef2aSThomas Huth                                 }
4380fcf5ef2aSThomas Huth                                 break;
4381fcf5ef2aSThomas Huth                             case 0x18: /* System tick */
4382fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
4383fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4384fcf5ef2aSThomas Huth                                     goto illegal_insn;
4385fcf5ef2aSThomas Huth #endif
4386fcf5ef2aSThomas Huth                                 {
4387fcf5ef2aSThomas Huth                                     TCGv_ptr r_tickptr;
4388fcf5ef2aSThomas Huth 
4389fcf5ef2aSThomas Huth                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
4390fcf5ef2aSThomas Huth                                                    cpu_src2);
4391fcf5ef2aSThomas Huth                                     r_tickptr = tcg_temp_new_ptr();
4392fcf5ef2aSThomas Huth                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
4393fcf5ef2aSThomas Huth                                                    offsetof(CPUSPARCState, stick));
439446bb0137SMark Cave-Ayland                                     if (tb_cflags(dc->base.tb) &
439546bb0137SMark Cave-Ayland                                            CF_USE_ICOUNT) {
439646bb0137SMark Cave-Ayland                                         gen_io_start();
439746bb0137SMark Cave-Ayland                                     }
4398fcf5ef2aSThomas Huth                                     gen_helper_tick_set_count(r_tickptr,
4399fcf5ef2aSThomas Huth                                                               cpu_tmp0);
4400fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tickptr);
440146bb0137SMark Cave-Ayland                                     /* End TB to handle timer interrupt */
440246bb0137SMark Cave-Ayland                                     dc->base.is_jmp = DISAS_EXIT;
4403fcf5ef2aSThomas Huth                                 }
4404fcf5ef2aSThomas Huth                                 break;
4405fcf5ef2aSThomas Huth                             case 0x19: /* System tick compare */
4406fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
4407fcf5ef2aSThomas Huth                                 if (!supervisor(dc))
4408fcf5ef2aSThomas Huth                                     goto illegal_insn;
4409fcf5ef2aSThomas Huth #endif
4410fcf5ef2aSThomas Huth                                 {
4411fcf5ef2aSThomas Huth                                     TCGv_ptr r_tickptr;
4412fcf5ef2aSThomas Huth 
4413fcf5ef2aSThomas Huth                                     tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
4414fcf5ef2aSThomas Huth                                                    cpu_src2);
4415fcf5ef2aSThomas Huth                                     r_tickptr = tcg_temp_new_ptr();
4416fcf5ef2aSThomas Huth                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
4417fcf5ef2aSThomas Huth                                                    offsetof(CPUSPARCState, stick));
441846bb0137SMark Cave-Ayland                                     if (tb_cflags(dc->base.tb) &
441946bb0137SMark Cave-Ayland                                            CF_USE_ICOUNT) {
442046bb0137SMark Cave-Ayland                                         gen_io_start();
442146bb0137SMark Cave-Ayland                                     }
4422fcf5ef2aSThomas Huth                                     gen_helper_tick_set_limit(r_tickptr,
4423fcf5ef2aSThomas Huth                                                               cpu_stick_cmpr);
4424fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tickptr);
442546bb0137SMark Cave-Ayland                                     /* End TB to handle timer interrupt */
442646bb0137SMark Cave-Ayland                                     dc->base.is_jmp = DISAS_EXIT;
4427fcf5ef2aSThomas Huth                                 }
4428fcf5ef2aSThomas Huth                                 break;
4429fcf5ef2aSThomas Huth 
4430fcf5ef2aSThomas Huth                             case 0x10: /* Performance Control */
4431fcf5ef2aSThomas Huth                             case 0x11: /* Performance Instrumentation
4432fcf5ef2aSThomas Huth                                           Counter */
4433fcf5ef2aSThomas Huth                             case 0x12: /* Dispatch Control */
4434fcf5ef2aSThomas Huth #endif
4435fcf5ef2aSThomas Huth                             default:
4436fcf5ef2aSThomas Huth                                 goto illegal_insn;
4437fcf5ef2aSThomas Huth                             }
4438fcf5ef2aSThomas Huth                         }
4439fcf5ef2aSThomas Huth                         break;
4440fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
4441fcf5ef2aSThomas Huth                     case 0x31: /* wrpsr, V9 saved, restored */
4442fcf5ef2aSThomas Huth                         {
4443fcf5ef2aSThomas Huth                             if (!supervisor(dc))
4444fcf5ef2aSThomas Huth                                 goto priv_insn;
4445fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4446fcf5ef2aSThomas Huth                             switch (rd) {
4447fcf5ef2aSThomas Huth                             case 0:
4448fcf5ef2aSThomas Huth                                 gen_helper_saved(cpu_env);
4449fcf5ef2aSThomas Huth                                 break;
4450fcf5ef2aSThomas Huth                             case 1:
4451fcf5ef2aSThomas Huth                                 gen_helper_restored(cpu_env);
4452fcf5ef2aSThomas Huth                                 break;
4453fcf5ef2aSThomas Huth                             case 2: /* UA2005 allclean */
4454fcf5ef2aSThomas Huth                             case 3: /* UA2005 otherw */
4455fcf5ef2aSThomas Huth                             case 4: /* UA2005 normalw */
4456fcf5ef2aSThomas Huth                             case 5: /* UA2005 invalw */
4457fcf5ef2aSThomas Huth                                 // XXX
4458fcf5ef2aSThomas Huth                             default:
4459fcf5ef2aSThomas Huth                                 goto illegal_insn;
4460fcf5ef2aSThomas Huth                             }
4461fcf5ef2aSThomas Huth #else
446252123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4463fcf5ef2aSThomas Huth                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4464fcf5ef2aSThomas Huth                             gen_helper_wrpsr(cpu_env, cpu_tmp0);
4465fcf5ef2aSThomas Huth                             tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4466fcf5ef2aSThomas Huth                             dc->cc_op = CC_OP_FLAGS;
4467fcf5ef2aSThomas Huth                             save_state(dc);
4468fcf5ef2aSThomas Huth                             gen_op_next_insn();
446907ea28b4SRichard Henderson                             tcg_gen_exit_tb(NULL, 0);
4470af00be49SEmilio G. Cota                             dc->base.is_jmp = DISAS_NORETURN;
4471fcf5ef2aSThomas Huth #endif
4472fcf5ef2aSThomas Huth                         }
4473fcf5ef2aSThomas Huth                         break;
4474fcf5ef2aSThomas Huth                     case 0x32: /* wrwim, V9 wrpr */
4475fcf5ef2aSThomas Huth                         {
4476fcf5ef2aSThomas Huth                             if (!supervisor(dc))
4477fcf5ef2aSThomas Huth                                 goto priv_insn;
447852123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4479fcf5ef2aSThomas Huth                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4480fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4481fcf5ef2aSThomas Huth                             switch (rd) {
4482fcf5ef2aSThomas Huth                             case 0: // tpc
4483fcf5ef2aSThomas Huth                                 {
4484fcf5ef2aSThomas Huth                                     TCGv_ptr r_tsptr;
4485fcf5ef2aSThomas Huth 
4486fcf5ef2aSThomas Huth                                     r_tsptr = tcg_temp_new_ptr();
4487fcf5ef2aSThomas Huth                                     gen_load_trap_state_at_tl(r_tsptr, cpu_env);
4488fcf5ef2aSThomas Huth                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
4489fcf5ef2aSThomas Huth                                                   offsetof(trap_state, tpc));
4490fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tsptr);
4491fcf5ef2aSThomas Huth                                 }
4492fcf5ef2aSThomas Huth                                 break;
4493fcf5ef2aSThomas Huth                             case 1: // tnpc
4494fcf5ef2aSThomas Huth                                 {
4495fcf5ef2aSThomas Huth                                     TCGv_ptr r_tsptr;
4496fcf5ef2aSThomas Huth 
4497fcf5ef2aSThomas Huth                                     r_tsptr = tcg_temp_new_ptr();
4498fcf5ef2aSThomas Huth                                     gen_load_trap_state_at_tl(r_tsptr, cpu_env);
4499fcf5ef2aSThomas Huth                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
4500fcf5ef2aSThomas Huth                                                   offsetof(trap_state, tnpc));
4501fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tsptr);
4502fcf5ef2aSThomas Huth                                 }
4503fcf5ef2aSThomas Huth                                 break;
4504fcf5ef2aSThomas Huth                             case 2: // tstate
4505fcf5ef2aSThomas Huth                                 {
4506fcf5ef2aSThomas Huth                                     TCGv_ptr r_tsptr;
4507fcf5ef2aSThomas Huth 
4508fcf5ef2aSThomas Huth                                     r_tsptr = tcg_temp_new_ptr();
4509fcf5ef2aSThomas Huth                                     gen_load_trap_state_at_tl(r_tsptr, cpu_env);
4510fcf5ef2aSThomas Huth                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
4511fcf5ef2aSThomas Huth                                                   offsetof(trap_state,
4512fcf5ef2aSThomas Huth                                                            tstate));
4513fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tsptr);
4514fcf5ef2aSThomas Huth                                 }
4515fcf5ef2aSThomas Huth                                 break;
4516fcf5ef2aSThomas Huth                             case 3: // tt
4517fcf5ef2aSThomas Huth                                 {
4518fcf5ef2aSThomas Huth                                     TCGv_ptr r_tsptr;
4519fcf5ef2aSThomas Huth 
4520fcf5ef2aSThomas Huth                                     r_tsptr = tcg_temp_new_ptr();
4521fcf5ef2aSThomas Huth                                     gen_load_trap_state_at_tl(r_tsptr, cpu_env);
4522fcf5ef2aSThomas Huth                                     tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4523fcf5ef2aSThomas Huth                                                     offsetof(trap_state, tt));
4524fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tsptr);
4525fcf5ef2aSThomas Huth                                 }
4526fcf5ef2aSThomas Huth                                 break;
4527fcf5ef2aSThomas Huth                             case 4: // tick
4528fcf5ef2aSThomas Huth                                 {
4529fcf5ef2aSThomas Huth                                     TCGv_ptr r_tickptr;
4530fcf5ef2aSThomas Huth 
4531fcf5ef2aSThomas Huth                                     r_tickptr = tcg_temp_new_ptr();
4532fcf5ef2aSThomas Huth                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
4533fcf5ef2aSThomas Huth                                                    offsetof(CPUSPARCState, tick));
453446bb0137SMark Cave-Ayland                                     if (tb_cflags(dc->base.tb) &
453546bb0137SMark Cave-Ayland                                            CF_USE_ICOUNT) {
453646bb0137SMark Cave-Ayland                                         gen_io_start();
453746bb0137SMark Cave-Ayland                                     }
4538fcf5ef2aSThomas Huth                                     gen_helper_tick_set_count(r_tickptr,
4539fcf5ef2aSThomas Huth                                                               cpu_tmp0);
4540fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tickptr);
454146bb0137SMark Cave-Ayland                                     /* End TB to handle timer interrupt */
454246bb0137SMark Cave-Ayland                                     dc->base.is_jmp = DISAS_EXIT;
4543fcf5ef2aSThomas Huth                                 }
4544fcf5ef2aSThomas Huth                                 break;
4545fcf5ef2aSThomas Huth                             case 5: // tba
4546fcf5ef2aSThomas Huth                                 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
4547fcf5ef2aSThomas Huth                                 break;
4548fcf5ef2aSThomas Huth                             case 6: // pstate
4549fcf5ef2aSThomas Huth                                 save_state(dc);
455046bb0137SMark Cave-Ayland                                 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
455146bb0137SMark Cave-Ayland                                     gen_io_start();
455246bb0137SMark Cave-Ayland                                 }
4553fcf5ef2aSThomas Huth                                 gen_helper_wrpstate(cpu_env, cpu_tmp0);
455446bb0137SMark Cave-Ayland                                 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4555b5328172SPeter Maydell                                     /* I/O ops in icount mode must end the TB */
4556b5328172SPeter Maydell                                     dc->base.is_jmp = DISAS_EXIT;
455746bb0137SMark Cave-Ayland                                 }
4558fcf5ef2aSThomas Huth                                 dc->npc = DYNAMIC_PC;
4559fcf5ef2aSThomas Huth                                 break;
4560fcf5ef2aSThomas Huth                             case 7: // tl
4561fcf5ef2aSThomas Huth                                 save_state(dc);
4562fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4563fcf5ef2aSThomas Huth                                                offsetof(CPUSPARCState, tl));
4564fcf5ef2aSThomas Huth                                 dc->npc = DYNAMIC_PC;
4565fcf5ef2aSThomas Huth                                 break;
4566fcf5ef2aSThomas Huth                             case 8: // pil
456746bb0137SMark Cave-Ayland                                 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
456846bb0137SMark Cave-Ayland                                     gen_io_start();
456946bb0137SMark Cave-Ayland                                 }
4570fcf5ef2aSThomas Huth                                 gen_helper_wrpil(cpu_env, cpu_tmp0);
457146bb0137SMark Cave-Ayland                                 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4572b5328172SPeter Maydell                                     /* I/O ops in icount mode must end the TB */
4573b5328172SPeter Maydell                                     dc->base.is_jmp = DISAS_EXIT;
457446bb0137SMark Cave-Ayland                                 }
4575fcf5ef2aSThomas Huth                                 break;
4576fcf5ef2aSThomas Huth                             case 9: // cwp
4577fcf5ef2aSThomas Huth                                 gen_helper_wrcwp(cpu_env, cpu_tmp0);
4578fcf5ef2aSThomas Huth                                 break;
4579fcf5ef2aSThomas Huth                             case 10: // cansave
4580fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4581fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState,
4582fcf5ef2aSThomas Huth                                                          cansave));
4583fcf5ef2aSThomas Huth                                 break;
4584fcf5ef2aSThomas Huth                             case 11: // canrestore
4585fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4586fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState,
4587fcf5ef2aSThomas Huth                                                          canrestore));
4588fcf5ef2aSThomas Huth                                 break;
4589fcf5ef2aSThomas Huth                             case 12: // cleanwin
4590fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4591fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState,
4592fcf5ef2aSThomas Huth                                                          cleanwin));
4593fcf5ef2aSThomas Huth                                 break;
4594fcf5ef2aSThomas Huth                             case 13: // otherwin
4595fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4596fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState,
4597fcf5ef2aSThomas Huth                                                          otherwin));
4598fcf5ef2aSThomas Huth                                 break;
4599fcf5ef2aSThomas Huth                             case 14: // wstate
4600fcf5ef2aSThomas Huth                                 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4601fcf5ef2aSThomas Huth                                                 offsetof(CPUSPARCState,
4602fcf5ef2aSThomas Huth                                                          wstate));
4603fcf5ef2aSThomas Huth                                 break;
4604fcf5ef2aSThomas Huth                             case 16: // UA2005 gl
4605fcf5ef2aSThomas Huth                                 CHECK_IU_FEATURE(dc, GL);
4606cbc3a6a4SArtyom Tarasenko                                 gen_helper_wrgl(cpu_env, cpu_tmp0);
4607fcf5ef2aSThomas Huth                                 break;
4608fcf5ef2aSThomas Huth                             case 26: // UA2005 strand status
4609fcf5ef2aSThomas Huth                                 CHECK_IU_FEATURE(dc, HYPV);
4610fcf5ef2aSThomas Huth                                 if (!hypervisor(dc))
4611fcf5ef2aSThomas Huth                                     goto priv_insn;
4612fcf5ef2aSThomas Huth                                 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
4613fcf5ef2aSThomas Huth                                 break;
4614fcf5ef2aSThomas Huth                             default:
4615fcf5ef2aSThomas Huth                                 goto illegal_insn;
4616fcf5ef2aSThomas Huth                             }
4617fcf5ef2aSThomas Huth #else
4618fcf5ef2aSThomas Huth                             tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4619fcf5ef2aSThomas Huth                             if (dc->def->nwindows != 32) {
4620fcf5ef2aSThomas Huth                                 tcg_gen_andi_tl(cpu_wim, cpu_wim,
4621fcf5ef2aSThomas Huth                                                 (1 << dc->def->nwindows) - 1);
4622fcf5ef2aSThomas Huth                             }
4623fcf5ef2aSThomas Huth #endif
4624fcf5ef2aSThomas Huth                         }
4625fcf5ef2aSThomas Huth                         break;
4626fcf5ef2aSThomas Huth                     case 0x33: /* wrtbr, UA2005 wrhpr */
4627fcf5ef2aSThomas Huth                         {
4628fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
4629fcf5ef2aSThomas Huth                             if (!supervisor(dc))
4630fcf5ef2aSThomas Huth                                 goto priv_insn;
4631fcf5ef2aSThomas Huth                             tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
4632fcf5ef2aSThomas Huth #else
4633fcf5ef2aSThomas Huth                             CHECK_IU_FEATURE(dc, HYPV);
4634fcf5ef2aSThomas Huth                             if (!hypervisor(dc))
4635fcf5ef2aSThomas Huth                                 goto priv_insn;
463652123f14SRichard Henderson                             cpu_tmp0 = tcg_temp_new();
4637fcf5ef2aSThomas Huth                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4638fcf5ef2aSThomas Huth                             switch (rd) {
4639fcf5ef2aSThomas Huth                             case 0: // hpstate
4640f7f17ef7SArtyom Tarasenko                                 tcg_gen_st_i64(cpu_tmp0, cpu_env,
4641f7f17ef7SArtyom Tarasenko                                                offsetof(CPUSPARCState,
4642f7f17ef7SArtyom Tarasenko                                                         hpstate));
4643fcf5ef2aSThomas Huth                                 save_state(dc);
4644fcf5ef2aSThomas Huth                                 gen_op_next_insn();
464507ea28b4SRichard Henderson                                 tcg_gen_exit_tb(NULL, 0);
4646af00be49SEmilio G. Cota                                 dc->base.is_jmp = DISAS_NORETURN;
4647fcf5ef2aSThomas Huth                                 break;
4648fcf5ef2aSThomas Huth                             case 1: // htstate
4649fcf5ef2aSThomas Huth                                 // XXX gen_op_wrhtstate();
4650fcf5ef2aSThomas Huth                                 break;
4651fcf5ef2aSThomas Huth                             case 3: // hintp
4652fcf5ef2aSThomas Huth                                 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
4653fcf5ef2aSThomas Huth                                 break;
4654fcf5ef2aSThomas Huth                             case 5: // htba
4655fcf5ef2aSThomas Huth                                 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
4656fcf5ef2aSThomas Huth                                 break;
4657fcf5ef2aSThomas Huth                             case 31: // hstick_cmpr
4658fcf5ef2aSThomas Huth                                 {
4659fcf5ef2aSThomas Huth                                     TCGv_ptr r_tickptr;
4660fcf5ef2aSThomas Huth 
4661fcf5ef2aSThomas Huth                                     tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
4662fcf5ef2aSThomas Huth                                     r_tickptr = tcg_temp_new_ptr();
4663fcf5ef2aSThomas Huth                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
4664fcf5ef2aSThomas Huth                                                    offsetof(CPUSPARCState, hstick));
466546bb0137SMark Cave-Ayland                                     if (tb_cflags(dc->base.tb) &
466646bb0137SMark Cave-Ayland                                            CF_USE_ICOUNT) {
466746bb0137SMark Cave-Ayland                                         gen_io_start();
466846bb0137SMark Cave-Ayland                                     }
4669fcf5ef2aSThomas Huth                                     gen_helper_tick_set_limit(r_tickptr,
4670fcf5ef2aSThomas Huth                                                               cpu_hstick_cmpr);
4671fcf5ef2aSThomas Huth                                     tcg_temp_free_ptr(r_tickptr);
467246bb0137SMark Cave-Ayland                                     /* End TB to handle timer interrupt */
467346bb0137SMark Cave-Ayland                                     dc->base.is_jmp = DISAS_EXIT;
4674fcf5ef2aSThomas Huth                                 }
4675fcf5ef2aSThomas Huth                                 break;
4676fcf5ef2aSThomas Huth                             case 6: // hver readonly
4677fcf5ef2aSThomas Huth                             default:
4678fcf5ef2aSThomas Huth                                 goto illegal_insn;
4679fcf5ef2aSThomas Huth                             }
4680fcf5ef2aSThomas Huth #endif
4681fcf5ef2aSThomas Huth                         }
4682fcf5ef2aSThomas Huth                         break;
4683fcf5ef2aSThomas Huth #endif
4684fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4685fcf5ef2aSThomas Huth                     case 0x2c: /* V9 movcc */
4686fcf5ef2aSThomas Huth                         {
4687fcf5ef2aSThomas Huth                             int cc = GET_FIELD_SP(insn, 11, 12);
4688fcf5ef2aSThomas Huth                             int cond = GET_FIELD_SP(insn, 14, 17);
4689fcf5ef2aSThomas Huth                             DisasCompare cmp;
4690fcf5ef2aSThomas Huth                             TCGv dst;
4691fcf5ef2aSThomas Huth 
4692fcf5ef2aSThomas Huth                             if (insn & (1 << 18)) {
4693fcf5ef2aSThomas Huth                                 if (cc == 0) {
4694fcf5ef2aSThomas Huth                                     gen_compare(&cmp, 0, cond, dc);
4695fcf5ef2aSThomas Huth                                 } else if (cc == 2) {
4696fcf5ef2aSThomas Huth                                     gen_compare(&cmp, 1, cond, dc);
4697fcf5ef2aSThomas Huth                                 } else {
4698fcf5ef2aSThomas Huth                                     goto illegal_insn;
4699fcf5ef2aSThomas Huth                                 }
4700fcf5ef2aSThomas Huth                             } else {
4701fcf5ef2aSThomas Huth                                 gen_fcompare(&cmp, cc, cond);
4702fcf5ef2aSThomas Huth                             }
4703fcf5ef2aSThomas Huth 
4704fcf5ef2aSThomas Huth                             /* The get_src2 above loaded the normal 13-bit
4705fcf5ef2aSThomas Huth                                immediate field, not the 11-bit field we have
4706fcf5ef2aSThomas Huth                                in movcc.  But it did handle the reg case.  */
4707fcf5ef2aSThomas Huth                             if (IS_IMM) {
4708fcf5ef2aSThomas Huth                                 simm = GET_FIELD_SPs(insn, 0, 10);
4709fcf5ef2aSThomas Huth                                 tcg_gen_movi_tl(cpu_src2, simm);
4710fcf5ef2aSThomas Huth                             }
4711fcf5ef2aSThomas Huth 
4712fcf5ef2aSThomas Huth                             dst = gen_load_gpr(dc, rd);
4713fcf5ef2aSThomas Huth                             tcg_gen_movcond_tl(cmp.cond, dst,
4714fcf5ef2aSThomas Huth                                                cmp.c1, cmp.c2,
4715fcf5ef2aSThomas Huth                                                cpu_src2, dst);
4716fcf5ef2aSThomas Huth                             free_compare(&cmp);
4717fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, dst);
4718fcf5ef2aSThomas Huth                             break;
4719fcf5ef2aSThomas Huth                         }
4720fcf5ef2aSThomas Huth                     case 0x2d: /* V9 sdivx */
4721fcf5ef2aSThomas Huth                         gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
4722fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4723fcf5ef2aSThomas Huth                         break;
4724fcf5ef2aSThomas Huth                     case 0x2e: /* V9 popc */
472508da3180SRichard Henderson                         tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
4726fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, cpu_dst);
4727fcf5ef2aSThomas Huth                         break;
4728fcf5ef2aSThomas Huth                     case 0x2f: /* V9 movr */
4729fcf5ef2aSThomas Huth                         {
4730fcf5ef2aSThomas Huth                             int cond = GET_FIELD_SP(insn, 10, 12);
4731fcf5ef2aSThomas Huth                             DisasCompare cmp;
4732fcf5ef2aSThomas Huth                             TCGv dst;
4733fcf5ef2aSThomas Huth 
4734fcf5ef2aSThomas Huth                             gen_compare_reg(&cmp, cond, cpu_src1);
4735fcf5ef2aSThomas Huth 
4736fcf5ef2aSThomas Huth                             /* The get_src2 above loaded the normal 13-bit
4737fcf5ef2aSThomas Huth                                immediate field, not the 10-bit field we have
4738fcf5ef2aSThomas Huth                                in movr.  But it did handle the reg case.  */
4739fcf5ef2aSThomas Huth                             if (IS_IMM) {
4740fcf5ef2aSThomas Huth                                 simm = GET_FIELD_SPs(insn, 0, 9);
4741fcf5ef2aSThomas Huth                                 tcg_gen_movi_tl(cpu_src2, simm);
4742fcf5ef2aSThomas Huth                             }
4743fcf5ef2aSThomas Huth 
4744fcf5ef2aSThomas Huth                             dst = gen_load_gpr(dc, rd);
4745fcf5ef2aSThomas Huth                             tcg_gen_movcond_tl(cmp.cond, dst,
4746fcf5ef2aSThomas Huth                                                cmp.c1, cmp.c2,
4747fcf5ef2aSThomas Huth                                                cpu_src2, dst);
4748fcf5ef2aSThomas Huth                             free_compare(&cmp);
4749fcf5ef2aSThomas Huth                             gen_store_gpr(dc, rd, dst);
4750fcf5ef2aSThomas Huth                             break;
4751fcf5ef2aSThomas Huth                         }
4752fcf5ef2aSThomas Huth #endif
4753fcf5ef2aSThomas Huth                     default:
4754fcf5ef2aSThomas Huth                         goto illegal_insn;
4755fcf5ef2aSThomas Huth                     }
4756fcf5ef2aSThomas Huth                 }
4757fcf5ef2aSThomas Huth             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4758fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
4759fcf5ef2aSThomas Huth                 int opf = GET_FIELD_SP(insn, 5, 13);
4760fcf5ef2aSThomas Huth                 rs1 = GET_FIELD(insn, 13, 17);
4761fcf5ef2aSThomas Huth                 rs2 = GET_FIELD(insn, 27, 31);
4762fcf5ef2aSThomas Huth                 if (gen_trap_ifnofpu(dc)) {
4763fcf5ef2aSThomas Huth                     goto jmp_insn;
4764fcf5ef2aSThomas Huth                 }
4765fcf5ef2aSThomas Huth 
4766fcf5ef2aSThomas Huth                 switch (opf) {
4767fcf5ef2aSThomas Huth                 case 0x000: /* VIS I edge8cc */
4768fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4769fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4770fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4771fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
4772fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4773fcf5ef2aSThomas Huth                     break;
4774fcf5ef2aSThomas Huth                 case 0x001: /* VIS II edge8n */
4775fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4776fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4777fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4778fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
4779fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4780fcf5ef2aSThomas Huth                     break;
4781fcf5ef2aSThomas Huth                 case 0x002: /* VIS I edge8lcc */
4782fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4783fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4784fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4785fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
4786fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4787fcf5ef2aSThomas Huth                     break;
4788fcf5ef2aSThomas Huth                 case 0x003: /* VIS II edge8ln */
4789fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4790fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4791fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4792fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
4793fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4794fcf5ef2aSThomas Huth                     break;
4795fcf5ef2aSThomas Huth                 case 0x004: /* VIS I edge16cc */
4796fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4797fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4798fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4799fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
4800fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4801fcf5ef2aSThomas Huth                     break;
4802fcf5ef2aSThomas Huth                 case 0x005: /* VIS II edge16n */
4803fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4804fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4805fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4806fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
4807fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4808fcf5ef2aSThomas Huth                     break;
4809fcf5ef2aSThomas Huth                 case 0x006: /* VIS I edge16lcc */
4810fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4811fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4812fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4813fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
4814fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4815fcf5ef2aSThomas Huth                     break;
4816fcf5ef2aSThomas Huth                 case 0x007: /* VIS II edge16ln */
4817fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4818fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4819fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4820fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
4821fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4822fcf5ef2aSThomas Huth                     break;
4823fcf5ef2aSThomas Huth                 case 0x008: /* VIS I edge32cc */
4824fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4825fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4826fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4827fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
4828fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4829fcf5ef2aSThomas Huth                     break;
4830fcf5ef2aSThomas Huth                 case 0x009: /* VIS II edge32n */
4831fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4832fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4833fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4834fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
4835fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4836fcf5ef2aSThomas Huth                     break;
4837fcf5ef2aSThomas Huth                 case 0x00a: /* VIS I edge32lcc */
4838fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4839fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4840fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4841fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
4842fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4843fcf5ef2aSThomas Huth                     break;
4844fcf5ef2aSThomas Huth                 case 0x00b: /* VIS II edge32ln */
4845fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4846fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4847fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4848fcf5ef2aSThomas Huth                     gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
4849fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4850fcf5ef2aSThomas Huth                     break;
4851fcf5ef2aSThomas Huth                 case 0x010: /* VIS I array8 */
4852fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4853fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4854fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4855fcf5ef2aSThomas Huth                     gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4856fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4857fcf5ef2aSThomas Huth                     break;
4858fcf5ef2aSThomas Huth                 case 0x012: /* VIS I array16 */
4859fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4860fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4861fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4862fcf5ef2aSThomas Huth                     gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4863fcf5ef2aSThomas Huth                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
4864fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4865fcf5ef2aSThomas Huth                     break;
4866fcf5ef2aSThomas Huth                 case 0x014: /* VIS I array32 */
4867fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4868fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4869fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4870fcf5ef2aSThomas Huth                     gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4871fcf5ef2aSThomas Huth                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
4872fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4873fcf5ef2aSThomas Huth                     break;
4874fcf5ef2aSThomas Huth                 case 0x018: /* VIS I alignaddr */
4875fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4876fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4877fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4878fcf5ef2aSThomas Huth                     gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
4879fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4880fcf5ef2aSThomas Huth                     break;
4881fcf5ef2aSThomas Huth                 case 0x01a: /* VIS I alignaddrl */
4882fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4883fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4884fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4885fcf5ef2aSThomas Huth                     gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
4886fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4887fcf5ef2aSThomas Huth                     break;
4888fcf5ef2aSThomas Huth                 case 0x019: /* VIS II bmask */
4889fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
4890fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rs1);
4891fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
4892fcf5ef2aSThomas Huth                     tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4893fcf5ef2aSThomas Huth                     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
4894fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4895fcf5ef2aSThomas Huth                     break;
4896fcf5ef2aSThomas Huth                 case 0x020: /* VIS I fcmple16 */
4897fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4898fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4899fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4900fcf5ef2aSThomas Huth                     gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
4901fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4902fcf5ef2aSThomas Huth                     break;
4903fcf5ef2aSThomas Huth                 case 0x022: /* VIS I fcmpne16 */
4904fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4905fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4906fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4907fcf5ef2aSThomas Huth                     gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
4908fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4909fcf5ef2aSThomas Huth                     break;
4910fcf5ef2aSThomas Huth                 case 0x024: /* VIS I fcmple32 */
4911fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4912fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4913fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4914fcf5ef2aSThomas Huth                     gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
4915fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4916fcf5ef2aSThomas Huth                     break;
4917fcf5ef2aSThomas Huth                 case 0x026: /* VIS I fcmpne32 */
4918fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4919fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4920fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4921fcf5ef2aSThomas Huth                     gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
4922fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4923fcf5ef2aSThomas Huth                     break;
4924fcf5ef2aSThomas Huth                 case 0x028: /* VIS I fcmpgt16 */
4925fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4926fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4927fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4928fcf5ef2aSThomas Huth                     gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
4929fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4930fcf5ef2aSThomas Huth                     break;
4931fcf5ef2aSThomas Huth                 case 0x02a: /* VIS I fcmpeq16 */
4932fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4933fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4934fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4935fcf5ef2aSThomas Huth                     gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
4936fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4937fcf5ef2aSThomas Huth                     break;
4938fcf5ef2aSThomas Huth                 case 0x02c: /* VIS I fcmpgt32 */
4939fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4940fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4941fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4942fcf5ef2aSThomas Huth                     gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
4943fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4944fcf5ef2aSThomas Huth                     break;
4945fcf5ef2aSThomas Huth                 case 0x02e: /* VIS I fcmpeq32 */
4946fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4947fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4948fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4949fcf5ef2aSThomas Huth                     gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
4950fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_dst);
4951fcf5ef2aSThomas Huth                     break;
4952fcf5ef2aSThomas Huth                 case 0x031: /* VIS I fmul8x16 */
4953fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4954fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
4955fcf5ef2aSThomas Huth                     break;
4956fcf5ef2aSThomas Huth                 case 0x033: /* VIS I fmul8x16au */
4957fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4958fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
4959fcf5ef2aSThomas Huth                     break;
4960fcf5ef2aSThomas Huth                 case 0x035: /* VIS I fmul8x16al */
4961fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4962fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
4963fcf5ef2aSThomas Huth                     break;
4964fcf5ef2aSThomas Huth                 case 0x036: /* VIS I fmul8sux16 */
4965fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4966fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
4967fcf5ef2aSThomas Huth                     break;
4968fcf5ef2aSThomas Huth                 case 0x037: /* VIS I fmul8ulx16 */
4969fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4970fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
4971fcf5ef2aSThomas Huth                     break;
4972fcf5ef2aSThomas Huth                 case 0x038: /* VIS I fmuld8sux16 */
4973fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4974fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
4975fcf5ef2aSThomas Huth                     break;
4976fcf5ef2aSThomas Huth                 case 0x039: /* VIS I fmuld8ulx16 */
4977fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4978fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
4979fcf5ef2aSThomas Huth                     break;
4980fcf5ef2aSThomas Huth                 case 0x03a: /* VIS I fpack32 */
4981fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4982fcf5ef2aSThomas Huth                     gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4983fcf5ef2aSThomas Huth                     break;
4984fcf5ef2aSThomas Huth                 case 0x03b: /* VIS I fpack16 */
4985fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4986fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4987fcf5ef2aSThomas Huth                     cpu_dst_32 = gen_dest_fpr_F(dc);
4988fcf5ef2aSThomas Huth                     gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4989fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_dst_32);
4990fcf5ef2aSThomas Huth                     break;
4991fcf5ef2aSThomas Huth                 case 0x03d: /* VIS I fpackfix */
4992fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
4993fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4994fcf5ef2aSThomas Huth                     cpu_dst_32 = gen_dest_fpr_F(dc);
4995fcf5ef2aSThomas Huth                     gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4996fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_dst_32);
4997fcf5ef2aSThomas Huth                     break;
4998fcf5ef2aSThomas Huth                 case 0x03e: /* VIS I pdist */
4999fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5000fcf5ef2aSThomas Huth                     gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
5001fcf5ef2aSThomas Huth                     break;
5002fcf5ef2aSThomas Huth                 case 0x048: /* VIS I faligndata */
5003fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5004fcf5ef2aSThomas Huth                     gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
5005fcf5ef2aSThomas Huth                     break;
5006fcf5ef2aSThomas Huth                 case 0x04b: /* VIS I fpmerge */
5007fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5008fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
5009fcf5ef2aSThomas Huth                     break;
5010fcf5ef2aSThomas Huth                 case 0x04c: /* VIS II bshuffle */
5011fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS2);
5012fcf5ef2aSThomas Huth                     gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
5013fcf5ef2aSThomas Huth                     break;
5014fcf5ef2aSThomas Huth                 case 0x04d: /* VIS I fexpand */
5015fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5016fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
5017fcf5ef2aSThomas Huth                     break;
5018fcf5ef2aSThomas Huth                 case 0x050: /* VIS I fpadd16 */
5019fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5020fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
5021fcf5ef2aSThomas Huth                     break;
5022fcf5ef2aSThomas Huth                 case 0x051: /* VIS I fpadd16s */
5023fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5024fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
5025fcf5ef2aSThomas Huth                     break;
5026fcf5ef2aSThomas Huth                 case 0x052: /* VIS I fpadd32 */
5027fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5028fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
5029fcf5ef2aSThomas Huth                     break;
5030fcf5ef2aSThomas Huth                 case 0x053: /* VIS I fpadd32s */
5031fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5032fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
5033fcf5ef2aSThomas Huth                     break;
5034fcf5ef2aSThomas Huth                 case 0x054: /* VIS I fpsub16 */
5035fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5036fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
5037fcf5ef2aSThomas Huth                     break;
5038fcf5ef2aSThomas Huth                 case 0x055: /* VIS I fpsub16s */
5039fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5040fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
5041fcf5ef2aSThomas Huth                     break;
5042fcf5ef2aSThomas Huth                 case 0x056: /* VIS I fpsub32 */
5043fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5044fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
5045fcf5ef2aSThomas Huth                     break;
5046fcf5ef2aSThomas Huth                 case 0x057: /* VIS I fpsub32s */
5047fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5048fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
5049fcf5ef2aSThomas Huth                     break;
5050fcf5ef2aSThomas Huth                 case 0x060: /* VIS I fzero */
5051fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5052fcf5ef2aSThomas Huth                     cpu_dst_64 = gen_dest_fpr_D(dc, rd);
5053fcf5ef2aSThomas Huth                     tcg_gen_movi_i64(cpu_dst_64, 0);
5054fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_dst_64);
5055fcf5ef2aSThomas Huth                     break;
5056fcf5ef2aSThomas Huth                 case 0x061: /* VIS I fzeros */
5057fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5058fcf5ef2aSThomas Huth                     cpu_dst_32 = gen_dest_fpr_F(dc);
5059fcf5ef2aSThomas Huth                     tcg_gen_movi_i32(cpu_dst_32, 0);
5060fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_dst_32);
5061fcf5ef2aSThomas Huth                     break;
5062fcf5ef2aSThomas Huth                 case 0x062: /* VIS I fnor */
5063fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5064fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
5065fcf5ef2aSThomas Huth                     break;
5066fcf5ef2aSThomas Huth                 case 0x063: /* VIS I fnors */
5067fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5068fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
5069fcf5ef2aSThomas Huth                     break;
5070fcf5ef2aSThomas Huth                 case 0x064: /* VIS I fandnot2 */
5071fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5072fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
5073fcf5ef2aSThomas Huth                     break;
5074fcf5ef2aSThomas Huth                 case 0x065: /* VIS I fandnot2s */
5075fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5076fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
5077fcf5ef2aSThomas Huth                     break;
5078fcf5ef2aSThomas Huth                 case 0x066: /* VIS I fnot2 */
5079fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5080fcf5ef2aSThomas Huth                     gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
5081fcf5ef2aSThomas Huth                     break;
5082fcf5ef2aSThomas Huth                 case 0x067: /* VIS I fnot2s */
5083fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5084fcf5ef2aSThomas Huth                     gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
5085fcf5ef2aSThomas Huth                     break;
5086fcf5ef2aSThomas Huth                 case 0x068: /* VIS I fandnot1 */
5087fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5088fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
5089fcf5ef2aSThomas Huth                     break;
5090fcf5ef2aSThomas Huth                 case 0x069: /* VIS I fandnot1s */
5091fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5092fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
5093fcf5ef2aSThomas Huth                     break;
5094fcf5ef2aSThomas Huth                 case 0x06a: /* VIS I fnot1 */
5095fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5096fcf5ef2aSThomas Huth                     gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
5097fcf5ef2aSThomas Huth                     break;
5098fcf5ef2aSThomas Huth                 case 0x06b: /* VIS I fnot1s */
5099fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5100fcf5ef2aSThomas Huth                     gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
5101fcf5ef2aSThomas Huth                     break;
5102fcf5ef2aSThomas Huth                 case 0x06c: /* VIS I fxor */
5103fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5104fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
5105fcf5ef2aSThomas Huth                     break;
5106fcf5ef2aSThomas Huth                 case 0x06d: /* VIS I fxors */
5107fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5108fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
5109fcf5ef2aSThomas Huth                     break;
5110fcf5ef2aSThomas Huth                 case 0x06e: /* VIS I fnand */
5111fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5112fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
5113fcf5ef2aSThomas Huth                     break;
5114fcf5ef2aSThomas Huth                 case 0x06f: /* VIS I fnands */
5115fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5116fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
5117fcf5ef2aSThomas Huth                     break;
5118fcf5ef2aSThomas Huth                 case 0x070: /* VIS I fand */
5119fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5120fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
5121fcf5ef2aSThomas Huth                     break;
5122fcf5ef2aSThomas Huth                 case 0x071: /* VIS I fands */
5123fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5124fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
5125fcf5ef2aSThomas Huth                     break;
5126fcf5ef2aSThomas Huth                 case 0x072: /* VIS I fxnor */
5127fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5128fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
5129fcf5ef2aSThomas Huth                     break;
5130fcf5ef2aSThomas Huth                 case 0x073: /* VIS I fxnors */
5131fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5132fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
5133fcf5ef2aSThomas Huth                     break;
5134fcf5ef2aSThomas Huth                 case 0x074: /* VIS I fsrc1 */
5135fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5136fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5137fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_src1_64);
5138fcf5ef2aSThomas Huth                     break;
5139fcf5ef2aSThomas Huth                 case 0x075: /* VIS I fsrc1s */
5140fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5141fcf5ef2aSThomas Huth                     cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5142fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_src1_32);
5143fcf5ef2aSThomas Huth                     break;
5144fcf5ef2aSThomas Huth                 case 0x076: /* VIS I fornot2 */
5145fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5146fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
5147fcf5ef2aSThomas Huth                     break;
5148fcf5ef2aSThomas Huth                 case 0x077: /* VIS I fornot2s */
5149fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5150fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
5151fcf5ef2aSThomas Huth                     break;
5152fcf5ef2aSThomas Huth                 case 0x078: /* VIS I fsrc2 */
5153fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5154fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5155fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_src1_64);
5156fcf5ef2aSThomas Huth                     break;
5157fcf5ef2aSThomas Huth                 case 0x079: /* VIS I fsrc2s */
5158fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5159fcf5ef2aSThomas Huth                     cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5160fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_src1_32);
5161fcf5ef2aSThomas Huth                     break;
5162fcf5ef2aSThomas Huth                 case 0x07a: /* VIS I fornot1 */
5163fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5164fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
5165fcf5ef2aSThomas Huth                     break;
5166fcf5ef2aSThomas Huth                 case 0x07b: /* VIS I fornot1s */
5167fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5168fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
5169fcf5ef2aSThomas Huth                     break;
5170fcf5ef2aSThomas Huth                 case 0x07c: /* VIS I for */
5171fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5172fcf5ef2aSThomas Huth                     gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
5173fcf5ef2aSThomas Huth                     break;
5174fcf5ef2aSThomas Huth                 case 0x07d: /* VIS I fors */
5175fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5176fcf5ef2aSThomas Huth                     gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
5177fcf5ef2aSThomas Huth                     break;
5178fcf5ef2aSThomas Huth                 case 0x07e: /* VIS I fone */
5179fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5180fcf5ef2aSThomas Huth                     cpu_dst_64 = gen_dest_fpr_D(dc, rd);
5181fcf5ef2aSThomas Huth                     tcg_gen_movi_i64(cpu_dst_64, -1);
5182fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_dst_64);
5183fcf5ef2aSThomas Huth                     break;
5184fcf5ef2aSThomas Huth                 case 0x07f: /* VIS I fones */
5185fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, VIS1);
5186fcf5ef2aSThomas Huth                     cpu_dst_32 = gen_dest_fpr_F(dc);
5187fcf5ef2aSThomas Huth                     tcg_gen_movi_i32(cpu_dst_32, -1);
5188fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_dst_32);
5189fcf5ef2aSThomas Huth                     break;
5190fcf5ef2aSThomas Huth                 case 0x080: /* VIS I shutdown */
5191fcf5ef2aSThomas Huth                 case 0x081: /* VIS II siam */
5192fcf5ef2aSThomas Huth                     // XXX
5193fcf5ef2aSThomas Huth                     goto illegal_insn;
5194fcf5ef2aSThomas Huth                 default:
5195fcf5ef2aSThomas Huth                     goto illegal_insn;
5196fcf5ef2aSThomas Huth                 }
5197fcf5ef2aSThomas Huth #else
5198fcf5ef2aSThomas Huth                 goto ncp_insn;
5199fcf5ef2aSThomas Huth #endif
5200fcf5ef2aSThomas Huth             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
5201fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5202fcf5ef2aSThomas Huth                 goto illegal_insn;
5203fcf5ef2aSThomas Huth #else
5204fcf5ef2aSThomas Huth                 goto ncp_insn;
5205fcf5ef2aSThomas Huth #endif
5206fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5207fcf5ef2aSThomas Huth             } else if (xop == 0x39) { /* V9 return */
5208fcf5ef2aSThomas Huth                 save_state(dc);
5209fcf5ef2aSThomas Huth                 cpu_src1 = get_src1(dc, insn);
521052123f14SRichard Henderson                 cpu_tmp0 = tcg_temp_new();
5211fcf5ef2aSThomas Huth                 if (IS_IMM) {   /* immediate */
5212fcf5ef2aSThomas Huth                     simm = GET_FIELDs(insn, 19, 31);
5213fcf5ef2aSThomas Huth                     tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
5214fcf5ef2aSThomas Huth                 } else {                /* register */
5215fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
5216fcf5ef2aSThomas Huth                     if (rs2) {
5217fcf5ef2aSThomas Huth                         cpu_src2 = gen_load_gpr(dc, rs2);
5218fcf5ef2aSThomas Huth                         tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
5219fcf5ef2aSThomas Huth                     } else {
5220fcf5ef2aSThomas Huth                         tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
5221fcf5ef2aSThomas Huth                     }
5222fcf5ef2aSThomas Huth                 }
5223fcf5ef2aSThomas Huth                 gen_helper_restore(cpu_env);
5224fcf5ef2aSThomas Huth                 gen_mov_pc_npc(dc);
5225fcf5ef2aSThomas Huth                 gen_check_align(cpu_tmp0, 3);
5226fcf5ef2aSThomas Huth                 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
5227fcf5ef2aSThomas Huth                 dc->npc = DYNAMIC_PC;
5228fcf5ef2aSThomas Huth                 goto jmp_insn;
5229fcf5ef2aSThomas Huth #endif
5230fcf5ef2aSThomas Huth             } else {
5231fcf5ef2aSThomas Huth                 cpu_src1 = get_src1(dc, insn);
523252123f14SRichard Henderson                 cpu_tmp0 = tcg_temp_new();
5233fcf5ef2aSThomas Huth                 if (IS_IMM) {   /* immediate */
5234fcf5ef2aSThomas Huth                     simm = GET_FIELDs(insn, 19, 31);
5235fcf5ef2aSThomas Huth                     tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
5236fcf5ef2aSThomas Huth                 } else {                /* register */
5237fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
5238fcf5ef2aSThomas Huth                     if (rs2) {
5239fcf5ef2aSThomas Huth                         cpu_src2 = gen_load_gpr(dc, rs2);
5240fcf5ef2aSThomas Huth                         tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
5241fcf5ef2aSThomas Huth                     } else {
5242fcf5ef2aSThomas Huth                         tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
5243fcf5ef2aSThomas Huth                     }
5244fcf5ef2aSThomas Huth                 }
5245fcf5ef2aSThomas Huth                 switch (xop) {
5246fcf5ef2aSThomas Huth                 case 0x38:      /* jmpl */
5247fcf5ef2aSThomas Huth                     {
5248fcf5ef2aSThomas Huth                         TCGv t = gen_dest_gpr(dc, rd);
5249fcf5ef2aSThomas Huth                         tcg_gen_movi_tl(t, dc->pc);
5250fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd, t);
5251fcf5ef2aSThomas Huth 
5252fcf5ef2aSThomas Huth                         gen_mov_pc_npc(dc);
5253fcf5ef2aSThomas Huth                         gen_check_align(cpu_tmp0, 3);
5254fcf5ef2aSThomas Huth                         gen_address_mask(dc, cpu_tmp0);
5255fcf5ef2aSThomas Huth                         tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
5256fcf5ef2aSThomas Huth                         dc->npc = DYNAMIC_PC;
5257fcf5ef2aSThomas Huth                     }
5258fcf5ef2aSThomas Huth                     goto jmp_insn;
5259fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5260fcf5ef2aSThomas Huth                 case 0x39:      /* rett, V9 return */
5261fcf5ef2aSThomas Huth                     {
5262fcf5ef2aSThomas Huth                         if (!supervisor(dc))
5263fcf5ef2aSThomas Huth                             goto priv_insn;
5264fcf5ef2aSThomas Huth                         gen_mov_pc_npc(dc);
5265fcf5ef2aSThomas Huth                         gen_check_align(cpu_tmp0, 3);
5266fcf5ef2aSThomas Huth                         tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
5267fcf5ef2aSThomas Huth                         dc->npc = DYNAMIC_PC;
5268fcf5ef2aSThomas Huth                         gen_helper_rett(cpu_env);
5269fcf5ef2aSThomas Huth                     }
5270fcf5ef2aSThomas Huth                     goto jmp_insn;
5271fcf5ef2aSThomas Huth #endif
5272fcf5ef2aSThomas Huth                 case 0x3b: /* flush */
5273fcf5ef2aSThomas Huth                     if (!((dc)->def->features & CPU_FEATURE_FLUSH))
5274fcf5ef2aSThomas Huth                         goto unimp_flush;
5275fcf5ef2aSThomas Huth                     /* nop */
5276fcf5ef2aSThomas Huth                     break;
5277fcf5ef2aSThomas Huth                 case 0x3c:      /* save */
5278fcf5ef2aSThomas Huth                     gen_helper_save(cpu_env);
5279fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_tmp0);
5280fcf5ef2aSThomas Huth                     break;
5281fcf5ef2aSThomas Huth                 case 0x3d:      /* restore */
5282fcf5ef2aSThomas Huth                     gen_helper_restore(cpu_env);
5283fcf5ef2aSThomas Huth                     gen_store_gpr(dc, rd, cpu_tmp0);
5284fcf5ef2aSThomas Huth                     break;
5285fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
5286fcf5ef2aSThomas Huth                 case 0x3e:      /* V9 done/retry */
5287fcf5ef2aSThomas Huth                     {
5288fcf5ef2aSThomas Huth                         switch (rd) {
5289fcf5ef2aSThomas Huth                         case 0:
5290fcf5ef2aSThomas Huth                             if (!supervisor(dc))
5291fcf5ef2aSThomas Huth                                 goto priv_insn;
5292fcf5ef2aSThomas Huth                             dc->npc = DYNAMIC_PC;
5293fcf5ef2aSThomas Huth                             dc->pc = DYNAMIC_PC;
529446bb0137SMark Cave-Ayland                             if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
529546bb0137SMark Cave-Ayland                                 gen_io_start();
529646bb0137SMark Cave-Ayland                             }
5297fcf5ef2aSThomas Huth                             gen_helper_done(cpu_env);
5298fcf5ef2aSThomas Huth                             goto jmp_insn;
5299fcf5ef2aSThomas Huth                         case 1:
5300fcf5ef2aSThomas Huth                             if (!supervisor(dc))
5301fcf5ef2aSThomas Huth                                 goto priv_insn;
5302fcf5ef2aSThomas Huth                             dc->npc = DYNAMIC_PC;
5303fcf5ef2aSThomas Huth                             dc->pc = DYNAMIC_PC;
530446bb0137SMark Cave-Ayland                             if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
530546bb0137SMark Cave-Ayland                                 gen_io_start();
530646bb0137SMark Cave-Ayland                             }
5307fcf5ef2aSThomas Huth                             gen_helper_retry(cpu_env);
5308fcf5ef2aSThomas Huth                             goto jmp_insn;
5309fcf5ef2aSThomas Huth                         default:
5310fcf5ef2aSThomas Huth                             goto illegal_insn;
5311fcf5ef2aSThomas Huth                         }
5312fcf5ef2aSThomas Huth                     }
5313fcf5ef2aSThomas Huth                     break;
5314fcf5ef2aSThomas Huth #endif
5315fcf5ef2aSThomas Huth                 default:
5316fcf5ef2aSThomas Huth                     goto illegal_insn;
5317fcf5ef2aSThomas Huth                 }
5318fcf5ef2aSThomas Huth             }
5319fcf5ef2aSThomas Huth             break;
5320fcf5ef2aSThomas Huth         }
5321fcf5ef2aSThomas Huth         break;
5322fcf5ef2aSThomas Huth     case 3:                     /* load/store instructions */
5323fcf5ef2aSThomas Huth         {
5324fcf5ef2aSThomas Huth             unsigned int xop = GET_FIELD(insn, 7, 12);
5325fcf5ef2aSThomas Huth             /* ??? gen_address_mask prevents us from using a source
5326fcf5ef2aSThomas Huth                register directly.  Always generate a temporary.  */
532752123f14SRichard Henderson             TCGv cpu_addr = tcg_temp_new();
5328fcf5ef2aSThomas Huth 
5329fcf5ef2aSThomas Huth             tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5330fcf5ef2aSThomas Huth             if (xop == 0x3c || xop == 0x3e) {
5331fcf5ef2aSThomas Huth                 /* V9 casa/casxa : no offset */
5332fcf5ef2aSThomas Huth             } else if (IS_IMM) {     /* immediate */
5333fcf5ef2aSThomas Huth                 simm = GET_FIELDs(insn, 19, 31);
5334fcf5ef2aSThomas Huth                 if (simm != 0) {
5335fcf5ef2aSThomas Huth                     tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5336fcf5ef2aSThomas Huth                 }
5337fcf5ef2aSThomas Huth             } else {            /* register */
5338fcf5ef2aSThomas Huth                 rs2 = GET_FIELD(insn, 27, 31);
5339fcf5ef2aSThomas Huth                 if (rs2 != 0) {
5340fcf5ef2aSThomas Huth                     tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
5341fcf5ef2aSThomas Huth                 }
5342fcf5ef2aSThomas Huth             }
5343fcf5ef2aSThomas Huth             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5344fcf5ef2aSThomas Huth                 (xop > 0x17 && xop <= 0x1d ) ||
5345fcf5ef2aSThomas Huth                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
5346fcf5ef2aSThomas Huth                 TCGv cpu_val = gen_dest_gpr(dc, rd);
5347fcf5ef2aSThomas Huth 
5348fcf5ef2aSThomas Huth                 switch (xop) {
5349fcf5ef2aSThomas Huth                 case 0x0:       /* ld, V9 lduw, load unsigned word */
5350fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5351fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
5352fcf5ef2aSThomas Huth                     break;
5353fcf5ef2aSThomas Huth                 case 0x1:       /* ldub, load unsigned byte */
5354fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5355fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
5356fcf5ef2aSThomas Huth                     break;
5357fcf5ef2aSThomas Huth                 case 0x2:       /* lduh, load unsigned halfword */
5358fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5359fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
5360fcf5ef2aSThomas Huth                     break;
5361fcf5ef2aSThomas Huth                 case 0x3:       /* ldd, load double word */
5362fcf5ef2aSThomas Huth                     if (rd & 1)
5363fcf5ef2aSThomas Huth                         goto illegal_insn;
5364fcf5ef2aSThomas Huth                     else {
5365fcf5ef2aSThomas Huth                         TCGv_i64 t64;
5366fcf5ef2aSThomas Huth 
5367fcf5ef2aSThomas Huth                         gen_address_mask(dc, cpu_addr);
5368fcf5ef2aSThomas Huth                         t64 = tcg_temp_new_i64();
5369fcf5ef2aSThomas Huth                         tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
5370fcf5ef2aSThomas Huth                         tcg_gen_trunc_i64_tl(cpu_val, t64);
5371fcf5ef2aSThomas Huth                         tcg_gen_ext32u_tl(cpu_val, cpu_val);
5372fcf5ef2aSThomas Huth                         gen_store_gpr(dc, rd + 1, cpu_val);
5373fcf5ef2aSThomas Huth                         tcg_gen_shri_i64(t64, t64, 32);
5374fcf5ef2aSThomas Huth                         tcg_gen_trunc_i64_tl(cpu_val, t64);
5375fcf5ef2aSThomas Huth                         tcg_temp_free_i64(t64);
5376fcf5ef2aSThomas Huth                         tcg_gen_ext32u_tl(cpu_val, cpu_val);
5377fcf5ef2aSThomas Huth                     }
5378fcf5ef2aSThomas Huth                     break;
5379fcf5ef2aSThomas Huth                 case 0x9:       /* ldsb, load signed byte */
5380fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5381fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
5382fcf5ef2aSThomas Huth                     break;
5383fcf5ef2aSThomas Huth                 case 0xa:       /* ldsh, load signed halfword */
5384fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5385fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
5386fcf5ef2aSThomas Huth                     break;
5387fcf5ef2aSThomas Huth                 case 0xd:       /* ldstub */
5388fcf5ef2aSThomas Huth                     gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
5389fcf5ef2aSThomas Huth                     break;
5390fcf5ef2aSThomas Huth                 case 0x0f:
5391fcf5ef2aSThomas Huth                     /* swap, swap register with memory. Also atomically */
5392fcf5ef2aSThomas Huth                     CHECK_IU_FEATURE(dc, SWAP);
5393fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rd);
5394fcf5ef2aSThomas Huth                     gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5395fcf5ef2aSThomas Huth                              dc->mem_idx, MO_TEUL);
5396fcf5ef2aSThomas Huth                     break;
5397fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5398fcf5ef2aSThomas Huth                 case 0x10:      /* lda, V9 lduwa, load word alternate */
5399fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
5400fcf5ef2aSThomas Huth                     break;
5401fcf5ef2aSThomas Huth                 case 0x11:      /* lduba, load unsigned byte alternate */
5402fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
5403fcf5ef2aSThomas Huth                     break;
5404fcf5ef2aSThomas Huth                 case 0x12:      /* lduha, load unsigned halfword alternate */
5405fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
5406fcf5ef2aSThomas Huth                     break;
5407fcf5ef2aSThomas Huth                 case 0x13:      /* ldda, load double word alternate */
5408fcf5ef2aSThomas Huth                     if (rd & 1) {
5409fcf5ef2aSThomas Huth                         goto illegal_insn;
5410fcf5ef2aSThomas Huth                     }
5411fcf5ef2aSThomas Huth                     gen_ldda_asi(dc, cpu_addr, insn, rd);
5412fcf5ef2aSThomas Huth                     goto skip_move;
5413fcf5ef2aSThomas Huth                 case 0x19:      /* ldsba, load signed byte alternate */
5414fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
5415fcf5ef2aSThomas Huth                     break;
5416fcf5ef2aSThomas Huth                 case 0x1a:      /* ldsha, load signed halfword alternate */
5417fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
5418fcf5ef2aSThomas Huth                     break;
5419fcf5ef2aSThomas Huth                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
5420fcf5ef2aSThomas Huth                     gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
5421fcf5ef2aSThomas Huth                     break;
5422fcf5ef2aSThomas Huth                 case 0x1f:      /* swapa, swap reg with alt. memory. Also
5423fcf5ef2aSThomas Huth                                    atomically */
5424fcf5ef2aSThomas Huth                     CHECK_IU_FEATURE(dc, SWAP);
5425fcf5ef2aSThomas Huth                     cpu_src1 = gen_load_gpr(dc, rd);
5426fcf5ef2aSThomas Huth                     gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
5427fcf5ef2aSThomas Huth                     break;
5428fcf5ef2aSThomas Huth 
5429fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
5430fcf5ef2aSThomas Huth                 case 0x30: /* ldc */
5431fcf5ef2aSThomas Huth                 case 0x31: /* ldcsr */
5432fcf5ef2aSThomas Huth                 case 0x33: /* lddc */
5433fcf5ef2aSThomas Huth                     goto ncp_insn;
5434fcf5ef2aSThomas Huth #endif
5435fcf5ef2aSThomas Huth #endif
5436fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5437fcf5ef2aSThomas Huth                 case 0x08: /* V9 ldsw */
5438fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5439fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
5440fcf5ef2aSThomas Huth                     break;
5441fcf5ef2aSThomas Huth                 case 0x0b: /* V9 ldx */
5442fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5443fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
5444fcf5ef2aSThomas Huth                     break;
5445fcf5ef2aSThomas Huth                 case 0x18: /* V9 ldswa */
5446fcf5ef2aSThomas Huth                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
5447fcf5ef2aSThomas Huth                     break;
5448fcf5ef2aSThomas Huth                 case 0x1b: /* V9 ldxa */
5449fc313c64SFrédéric Pétrot                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
5450fcf5ef2aSThomas Huth                     break;
5451fcf5ef2aSThomas Huth                 case 0x2d: /* V9 prefetch, no effect */
5452fcf5ef2aSThomas Huth                     goto skip_move;
5453fcf5ef2aSThomas Huth                 case 0x30: /* V9 ldfa */
5454fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5455fcf5ef2aSThomas Huth                         goto jmp_insn;
5456fcf5ef2aSThomas Huth                     }
5457fcf5ef2aSThomas Huth                     gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
5458fcf5ef2aSThomas Huth                     gen_update_fprs_dirty(dc, rd);
5459fcf5ef2aSThomas Huth                     goto skip_move;
5460fcf5ef2aSThomas Huth                 case 0x33: /* V9 lddfa */
5461fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5462fcf5ef2aSThomas Huth                         goto jmp_insn;
5463fcf5ef2aSThomas Huth                     }
5464fcf5ef2aSThomas Huth                     gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
5465fcf5ef2aSThomas Huth                     gen_update_fprs_dirty(dc, DFPREG(rd));
5466fcf5ef2aSThomas Huth                     goto skip_move;
5467fcf5ef2aSThomas Huth                 case 0x3d: /* V9 prefetcha, no effect */
5468fcf5ef2aSThomas Huth                     goto skip_move;
5469fcf5ef2aSThomas Huth                 case 0x32: /* V9 ldqfa */
5470fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
5471fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5472fcf5ef2aSThomas Huth                         goto jmp_insn;
5473fcf5ef2aSThomas Huth                     }
5474fcf5ef2aSThomas Huth                     gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
5475fcf5ef2aSThomas Huth                     gen_update_fprs_dirty(dc, QFPREG(rd));
5476fcf5ef2aSThomas Huth                     goto skip_move;
5477fcf5ef2aSThomas Huth #endif
5478fcf5ef2aSThomas Huth                 default:
5479fcf5ef2aSThomas Huth                     goto illegal_insn;
5480fcf5ef2aSThomas Huth                 }
5481fcf5ef2aSThomas Huth                 gen_store_gpr(dc, rd, cpu_val);
5482fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5483fcf5ef2aSThomas Huth             skip_move: ;
5484fcf5ef2aSThomas Huth #endif
5485fcf5ef2aSThomas Huth             } else if (xop >= 0x20 && xop < 0x24) {
5486fcf5ef2aSThomas Huth                 if (gen_trap_ifnofpu(dc)) {
5487fcf5ef2aSThomas Huth                     goto jmp_insn;
5488fcf5ef2aSThomas Huth                 }
5489fcf5ef2aSThomas Huth                 switch (xop) {
5490fcf5ef2aSThomas Huth                 case 0x20:      /* ldf, load fpreg */
5491fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5492fcf5ef2aSThomas Huth                     cpu_dst_32 = gen_dest_fpr_F(dc);
5493fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5494fcf5ef2aSThomas Huth                                         dc->mem_idx, MO_TEUL);
5495fcf5ef2aSThomas Huth                     gen_store_fpr_F(dc, rd, cpu_dst_32);
5496fcf5ef2aSThomas Huth                     break;
5497fcf5ef2aSThomas Huth                 case 0x21:      /* ldfsr, V9 ldxfsr */
5498fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5499fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5500fcf5ef2aSThomas Huth                     if (rd == 1) {
5501fcf5ef2aSThomas Huth                         TCGv_i64 t64 = tcg_temp_new_i64();
5502fcf5ef2aSThomas Huth                         tcg_gen_qemu_ld_i64(t64, cpu_addr,
5503fc313c64SFrédéric Pétrot                                             dc->mem_idx, MO_TEUQ);
5504fcf5ef2aSThomas Huth                         gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
5505fcf5ef2aSThomas Huth                         tcg_temp_free_i64(t64);
5506fcf5ef2aSThomas Huth                         break;
5507fcf5ef2aSThomas Huth                     }
5508fcf5ef2aSThomas Huth #endif
5509*36ab4623SRichard Henderson                     cpu_dst_32 = tcg_temp_new_i32();
5510fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5511fcf5ef2aSThomas Huth                                         dc->mem_idx, MO_TEUL);
5512fcf5ef2aSThomas Huth                     gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
5513fcf5ef2aSThomas Huth                     break;
5514fcf5ef2aSThomas Huth                 case 0x22:      /* ldqf, load quad fpreg */
5515fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
5516fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5517fcf5ef2aSThomas Huth                     cpu_src1_64 = tcg_temp_new_i64();
5518fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5519fc313c64SFrédéric Pétrot                                         MO_TEUQ | MO_ALIGN_4);
5520fcf5ef2aSThomas Huth                     tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5521fcf5ef2aSThomas Huth                     cpu_src2_64 = tcg_temp_new_i64();
5522fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5523fc313c64SFrédéric Pétrot                                         MO_TEUQ | MO_ALIGN_4);
5524fcf5ef2aSThomas Huth                     gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5525fcf5ef2aSThomas Huth                     tcg_temp_free_i64(cpu_src1_64);
5526fcf5ef2aSThomas Huth                     tcg_temp_free_i64(cpu_src2_64);
5527fcf5ef2aSThomas Huth                     break;
5528fcf5ef2aSThomas Huth                 case 0x23:      /* lddf, load double fpreg */
5529fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5530fcf5ef2aSThomas Huth                     cpu_dst_64 = gen_dest_fpr_D(dc, rd);
5531fcf5ef2aSThomas Huth                     tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5532fc313c64SFrédéric Pétrot                                         MO_TEUQ | MO_ALIGN_4);
5533fcf5ef2aSThomas Huth                     gen_store_fpr_D(dc, rd, cpu_dst_64);
5534fcf5ef2aSThomas Huth                     break;
5535fcf5ef2aSThomas Huth                 default:
5536fcf5ef2aSThomas Huth                     goto illegal_insn;
5537fcf5ef2aSThomas Huth                 }
5538fcf5ef2aSThomas Huth             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
5539fcf5ef2aSThomas Huth                        xop == 0xe || xop == 0x1e) {
5540fcf5ef2aSThomas Huth                 TCGv cpu_val = gen_load_gpr(dc, rd);
5541fcf5ef2aSThomas Huth 
5542fcf5ef2aSThomas Huth                 switch (xop) {
5543fcf5ef2aSThomas Huth                 case 0x4: /* st, store word */
5544fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5545fcf5ef2aSThomas Huth                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
5546fcf5ef2aSThomas Huth                     break;
5547fcf5ef2aSThomas Huth                 case 0x5: /* stb, store byte */
5548fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5549fcf5ef2aSThomas Huth                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
5550fcf5ef2aSThomas Huth                     break;
5551fcf5ef2aSThomas Huth                 case 0x6: /* sth, store halfword */
5552fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5553fcf5ef2aSThomas Huth                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
5554fcf5ef2aSThomas Huth                     break;
5555fcf5ef2aSThomas Huth                 case 0x7: /* std, store double word */
5556fcf5ef2aSThomas Huth                     if (rd & 1)
5557fcf5ef2aSThomas Huth                         goto illegal_insn;
5558fcf5ef2aSThomas Huth                     else {
5559fcf5ef2aSThomas Huth                         TCGv_i64 t64;
5560fcf5ef2aSThomas Huth                         TCGv lo;
5561fcf5ef2aSThomas Huth 
5562fcf5ef2aSThomas Huth                         gen_address_mask(dc, cpu_addr);
5563fcf5ef2aSThomas Huth                         lo = gen_load_gpr(dc, rd + 1);
5564fcf5ef2aSThomas Huth                         t64 = tcg_temp_new_i64();
5565fcf5ef2aSThomas Huth                         tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5566fcf5ef2aSThomas Huth                         tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5567fcf5ef2aSThomas Huth                         tcg_temp_free_i64(t64);
5568fcf5ef2aSThomas Huth                     }
5569fcf5ef2aSThomas Huth                     break;
5570fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5571fcf5ef2aSThomas Huth                 case 0x14: /* sta, V9 stwa, store word alternate */
5572fcf5ef2aSThomas Huth                     gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
5573fcf5ef2aSThomas Huth                     break;
5574fcf5ef2aSThomas Huth                 case 0x15: /* stba, store byte alternate */
5575fcf5ef2aSThomas Huth                     gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
5576fcf5ef2aSThomas Huth                     break;
5577fcf5ef2aSThomas Huth                 case 0x16: /* stha, store halfword alternate */
5578fcf5ef2aSThomas Huth                     gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
5579fcf5ef2aSThomas Huth                     break;
5580fcf5ef2aSThomas Huth                 case 0x17: /* stda, store double word alternate */
5581fcf5ef2aSThomas Huth                     if (rd & 1) {
5582fcf5ef2aSThomas Huth                         goto illegal_insn;
5583fcf5ef2aSThomas Huth                     }
5584fcf5ef2aSThomas Huth                     gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
5585fcf5ef2aSThomas Huth                     break;
5586fcf5ef2aSThomas Huth #endif
5587fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5588fcf5ef2aSThomas Huth                 case 0x0e: /* V9 stx */
5589fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5590fcf5ef2aSThomas Huth                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
5591fcf5ef2aSThomas Huth                     break;
5592fcf5ef2aSThomas Huth                 case 0x1e: /* V9 stxa */
5593fc313c64SFrédéric Pétrot                     gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
5594fcf5ef2aSThomas Huth                     break;
5595fcf5ef2aSThomas Huth #endif
5596fcf5ef2aSThomas Huth                 default:
5597fcf5ef2aSThomas Huth                     goto illegal_insn;
5598fcf5ef2aSThomas Huth                 }
5599fcf5ef2aSThomas Huth             } else if (xop > 0x23 && xop < 0x28) {
5600fcf5ef2aSThomas Huth                 if (gen_trap_ifnofpu(dc)) {
5601fcf5ef2aSThomas Huth                     goto jmp_insn;
5602fcf5ef2aSThomas Huth                 }
5603fcf5ef2aSThomas Huth                 switch (xop) {
5604fcf5ef2aSThomas Huth                 case 0x24: /* stf, store fpreg */
5605fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5606fcf5ef2aSThomas Huth                     cpu_src1_32 = gen_load_fpr_F(dc, rd);
5607fcf5ef2aSThomas Huth                     tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5608fcf5ef2aSThomas Huth                                         dc->mem_idx, MO_TEUL);
5609fcf5ef2aSThomas Huth                     break;
5610fcf5ef2aSThomas Huth                 case 0x25: /* stfsr, V9 stxfsr */
5611fcf5ef2aSThomas Huth                     {
5612fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5613fcf5ef2aSThomas Huth                         gen_address_mask(dc, cpu_addr);
5614fcf5ef2aSThomas Huth                         if (rd == 1) {
5615fcf5ef2aSThomas Huth                             tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
5616fcf5ef2aSThomas Huth                             break;
5617fcf5ef2aSThomas Huth                         }
5618fcf5ef2aSThomas Huth #endif
5619fcf5ef2aSThomas Huth                         tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
5620fcf5ef2aSThomas Huth                     }
5621fcf5ef2aSThomas Huth                     break;
5622fcf5ef2aSThomas Huth                 case 0x26:
5623fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5624fcf5ef2aSThomas Huth                     /* V9 stqf, store quad fpreg */
5625fcf5ef2aSThomas Huth                     CHECK_FPU_FEATURE(dc, FLOAT128);
5626fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5627fcf5ef2aSThomas Huth                     /* ??? While stqf only requires 4-byte alignment, it is
5628fcf5ef2aSThomas Huth                        legal for the cpu to signal the unaligned exception.
5629fcf5ef2aSThomas Huth                        The OS trap handler is then required to fix it up.
5630fcf5ef2aSThomas Huth                        For qemu, this avoids having to probe the second page
5631fcf5ef2aSThomas Huth                        before performing the first write.  */
5632fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5633fcf5ef2aSThomas Huth                     tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5634fc313c64SFrédéric Pétrot                                         dc->mem_idx, MO_TEUQ | MO_ALIGN_16);
5635fcf5ef2aSThomas Huth                     tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5636fcf5ef2aSThomas Huth                     cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5637fcf5ef2aSThomas Huth                     tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5638fc313c64SFrédéric Pétrot                                         dc->mem_idx, MO_TEUQ);
5639fcf5ef2aSThomas Huth                     break;
5640fcf5ef2aSThomas Huth #else /* !TARGET_SPARC64 */
5641fcf5ef2aSThomas Huth                     /* stdfq, store floating point queue */
5642fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY)
5643fcf5ef2aSThomas Huth                     goto illegal_insn;
5644fcf5ef2aSThomas Huth #else
5645fcf5ef2aSThomas Huth                     if (!supervisor(dc))
5646fcf5ef2aSThomas Huth                         goto priv_insn;
5647fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5648fcf5ef2aSThomas Huth                         goto jmp_insn;
5649fcf5ef2aSThomas Huth                     }
5650fcf5ef2aSThomas Huth                     goto nfq_insn;
5651fcf5ef2aSThomas Huth #endif
5652fcf5ef2aSThomas Huth #endif
5653fcf5ef2aSThomas Huth                 case 0x27: /* stdf, store double fpreg */
5654fcf5ef2aSThomas Huth                     gen_address_mask(dc, cpu_addr);
5655fcf5ef2aSThomas Huth                     cpu_src1_64 = gen_load_fpr_D(dc, rd);
5656fcf5ef2aSThomas Huth                     tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5657fc313c64SFrédéric Pétrot                                         MO_TEUQ | MO_ALIGN_4);
5658fcf5ef2aSThomas Huth                     break;
5659fcf5ef2aSThomas Huth                 default:
5660fcf5ef2aSThomas Huth                     goto illegal_insn;
5661fcf5ef2aSThomas Huth                 }
5662fcf5ef2aSThomas Huth             } else if (xop > 0x33 && xop < 0x3f) {
5663fcf5ef2aSThomas Huth                 switch (xop) {
5664fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5665fcf5ef2aSThomas Huth                 case 0x34: /* V9 stfa */
5666fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5667fcf5ef2aSThomas Huth                         goto jmp_insn;
5668fcf5ef2aSThomas Huth                     }
5669fcf5ef2aSThomas Huth                     gen_stf_asi(dc, cpu_addr, insn, 4, rd);
5670fcf5ef2aSThomas Huth                     break;
5671fcf5ef2aSThomas Huth                 case 0x36: /* V9 stqfa */
5672fcf5ef2aSThomas Huth                     {
5673fcf5ef2aSThomas Huth                         CHECK_FPU_FEATURE(dc, FLOAT128);
5674fcf5ef2aSThomas Huth                         if (gen_trap_ifnofpu(dc)) {
5675fcf5ef2aSThomas Huth                             goto jmp_insn;
5676fcf5ef2aSThomas Huth                         }
5677fcf5ef2aSThomas Huth                         gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
5678fcf5ef2aSThomas Huth                     }
5679fcf5ef2aSThomas Huth                     break;
5680fcf5ef2aSThomas Huth                 case 0x37: /* V9 stdfa */
5681fcf5ef2aSThomas Huth                     if (gen_trap_ifnofpu(dc)) {
5682fcf5ef2aSThomas Huth                         goto jmp_insn;
5683fcf5ef2aSThomas Huth                     }
5684fcf5ef2aSThomas Huth                     gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
5685fcf5ef2aSThomas Huth                     break;
5686fcf5ef2aSThomas Huth                 case 0x3e: /* V9 casxa */
5687fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
5688fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
5689fcf5ef2aSThomas Huth                     gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
5690fcf5ef2aSThomas Huth                     break;
5691fcf5ef2aSThomas Huth #else
5692fcf5ef2aSThomas Huth                 case 0x34: /* stc */
5693fcf5ef2aSThomas Huth                 case 0x35: /* stcsr */
5694fcf5ef2aSThomas Huth                 case 0x36: /* stdcq */
5695fcf5ef2aSThomas Huth                 case 0x37: /* stdc */
5696fcf5ef2aSThomas Huth                     goto ncp_insn;
5697fcf5ef2aSThomas Huth #endif
5698fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5699fcf5ef2aSThomas Huth                 case 0x3c: /* V9 or LEON3 casa */
5700fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
5701fcf5ef2aSThomas Huth                     CHECK_IU_FEATURE(dc, CASA);
5702fcf5ef2aSThomas Huth #endif
5703fcf5ef2aSThomas Huth                     rs2 = GET_FIELD(insn, 27, 31);
5704fcf5ef2aSThomas Huth                     cpu_src2 = gen_load_gpr(dc, rs2);
5705fcf5ef2aSThomas Huth                     gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5706fcf5ef2aSThomas Huth                     break;
5707fcf5ef2aSThomas Huth #endif
5708fcf5ef2aSThomas Huth                 default:
5709fcf5ef2aSThomas Huth                     goto illegal_insn;
5710fcf5ef2aSThomas Huth                 }
5711fcf5ef2aSThomas Huth             } else {
5712fcf5ef2aSThomas Huth                 goto illegal_insn;
5713fcf5ef2aSThomas Huth             }
5714fcf5ef2aSThomas Huth         }
5715fcf5ef2aSThomas Huth         break;
5716fcf5ef2aSThomas Huth     }
5717fcf5ef2aSThomas Huth     /* default case for non jump instructions */
5718fcf5ef2aSThomas Huth     if (dc->npc == DYNAMIC_PC) {
5719fcf5ef2aSThomas Huth         dc->pc = DYNAMIC_PC;
5720fcf5ef2aSThomas Huth         gen_op_next_insn();
5721fcf5ef2aSThomas Huth     } else if (dc->npc == JUMP_PC) {
5722fcf5ef2aSThomas Huth         /* we can do a static jump */
5723fcf5ef2aSThomas Huth         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
5724af00be49SEmilio G. Cota         dc->base.is_jmp = DISAS_NORETURN;
5725fcf5ef2aSThomas Huth     } else {
5726fcf5ef2aSThomas Huth         dc->pc = dc->npc;
5727fcf5ef2aSThomas Huth         dc->npc = dc->npc + 4;
5728fcf5ef2aSThomas Huth     }
5729fcf5ef2aSThomas Huth  jmp_insn:
5730fcf5ef2aSThomas Huth     goto egress;
5731fcf5ef2aSThomas Huth  illegal_insn:
5732fcf5ef2aSThomas Huth     gen_exception(dc, TT_ILL_INSN);
5733fcf5ef2aSThomas Huth     goto egress;
5734fcf5ef2aSThomas Huth  unimp_flush:
5735fcf5ef2aSThomas Huth     gen_exception(dc, TT_UNIMP_FLUSH);
5736fcf5ef2aSThomas Huth     goto egress;
5737fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
5738fcf5ef2aSThomas Huth  priv_insn:
5739fcf5ef2aSThomas Huth     gen_exception(dc, TT_PRIV_INSN);
5740fcf5ef2aSThomas Huth     goto egress;
5741fcf5ef2aSThomas Huth #endif
5742fcf5ef2aSThomas Huth  nfpu_insn:
5743fcf5ef2aSThomas Huth     gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
5744fcf5ef2aSThomas Huth     goto egress;
5745fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5746fcf5ef2aSThomas Huth  nfq_insn:
5747fcf5ef2aSThomas Huth     gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
5748fcf5ef2aSThomas Huth     goto egress;
5749fcf5ef2aSThomas Huth #endif
5750fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
5751fcf5ef2aSThomas Huth  ncp_insn:
5752fcf5ef2aSThomas Huth     gen_exception(dc, TT_NCP_INSN);
5753fcf5ef2aSThomas Huth     goto egress;
5754fcf5ef2aSThomas Huth #endif
5755fcf5ef2aSThomas Huth  egress:
5756fcf5ef2aSThomas Huth }
5757fcf5ef2aSThomas Huth 
57586e61bc94SEmilio G. Cota static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5759fcf5ef2aSThomas Huth {
57606e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
57619c489ea6SLluís Vilanova     CPUSPARCState *env = cs->env_ptr;
57626e61bc94SEmilio G. Cota     int bound;
5763af00be49SEmilio G. Cota 
5764af00be49SEmilio G. Cota     dc->pc = dc->base.pc_first;
57656e61bc94SEmilio G. Cota     dc->npc = (target_ulong)dc->base.tb->cs_base;
5766fcf5ef2aSThomas Huth     dc->cc_op = CC_OP_DYNAMIC;
57676e61bc94SEmilio G. Cota     dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
5768576e1c4cSIgor Mammedov     dc->def = &env->def;
57696e61bc94SEmilio G. Cota     dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
57706e61bc94SEmilio G. Cota     dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
5771c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
57726e61bc94SEmilio G. Cota     dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
5773c9b459aaSArtyom Tarasenko #endif
5774fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5775fcf5ef2aSThomas Huth     dc->fprs_dirty = 0;
57766e61bc94SEmilio G. Cota     dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
5777c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
57786e61bc94SEmilio G. Cota     dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
5779c9b459aaSArtyom Tarasenko #endif
5780fcf5ef2aSThomas Huth #endif
57816e61bc94SEmilio G. Cota     /*
57826e61bc94SEmilio G. Cota      * if we reach a page boundary, we stop generation so that the
57836e61bc94SEmilio G. Cota      * PC of a TT_TFAULT exception is always in the right page
57846e61bc94SEmilio G. Cota      */
57856e61bc94SEmilio G. Cota     bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
57866e61bc94SEmilio G. Cota     dc->base.max_insns = MIN(dc->base.max_insns, bound);
5787af00be49SEmilio G. Cota }
5788fcf5ef2aSThomas Huth 
57896e61bc94SEmilio G. Cota static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
57906e61bc94SEmilio G. Cota {
57916e61bc94SEmilio G. Cota }
57926e61bc94SEmilio G. Cota 
57936e61bc94SEmilio G. Cota static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
57946e61bc94SEmilio G. Cota {
57956e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
57966e61bc94SEmilio G. Cota 
5797fcf5ef2aSThomas Huth     if (dc->npc & JUMP_PC) {
5798fcf5ef2aSThomas Huth         assert(dc->jump_pc[1] == dc->pc + 4);
5799fcf5ef2aSThomas Huth         tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5800fcf5ef2aSThomas Huth     } else {
5801fcf5ef2aSThomas Huth         tcg_gen_insn_start(dc->pc, dc->npc);
5802fcf5ef2aSThomas Huth     }
58036e61bc94SEmilio G. Cota }
5804fcf5ef2aSThomas Huth 
58056e61bc94SEmilio G. Cota static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
58066e61bc94SEmilio G. Cota {
58076e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
58086e61bc94SEmilio G. Cota     CPUSPARCState *env = cs->env_ptr;
58096e61bc94SEmilio G. Cota     unsigned int insn;
5810fcf5ef2aSThomas Huth 
58114e116893SIlya Leoshkevich     insn = translator_ldl(env, &dc->base, dc->pc);
5812af00be49SEmilio G. Cota     dc->base.pc_next += 4;
5813fcf5ef2aSThomas Huth     disas_sparc_insn(dc, insn);
5814fcf5ef2aSThomas Huth 
5815af00be49SEmilio G. Cota     if (dc->base.is_jmp == DISAS_NORETURN) {
58166e61bc94SEmilio G. Cota         return;
5817c5e6ccdfSEmilio G. Cota     }
5818af00be49SEmilio G. Cota     if (dc->pc != dc->base.pc_next) {
58196e61bc94SEmilio G. Cota         dc->base.is_jmp = DISAS_TOO_MANY;
5820af00be49SEmilio G. Cota     }
58216e61bc94SEmilio G. Cota }
5822fcf5ef2aSThomas Huth 
58236e61bc94SEmilio G. Cota static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
58246e61bc94SEmilio G. Cota {
58256e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
58266e61bc94SEmilio G. Cota 
582746bb0137SMark Cave-Ayland     switch (dc->base.is_jmp) {
582846bb0137SMark Cave-Ayland     case DISAS_NEXT:
582946bb0137SMark Cave-Ayland     case DISAS_TOO_MANY:
5830fcf5ef2aSThomas Huth         if (dc->pc != DYNAMIC_PC &&
5831fcf5ef2aSThomas Huth             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5832fcf5ef2aSThomas Huth             /* static PC and NPC: we can use direct chaining */
5833fcf5ef2aSThomas Huth             gen_goto_tb(dc, 0, dc->pc, dc->npc);
5834fcf5ef2aSThomas Huth         } else {
5835fcf5ef2aSThomas Huth             if (dc->pc != DYNAMIC_PC) {
5836fcf5ef2aSThomas Huth                 tcg_gen_movi_tl(cpu_pc, dc->pc);
5837fcf5ef2aSThomas Huth             }
5838fcf5ef2aSThomas Huth             save_npc(dc);
583907ea28b4SRichard Henderson             tcg_gen_exit_tb(NULL, 0);
5840fcf5ef2aSThomas Huth         }
584146bb0137SMark Cave-Ayland         break;
584246bb0137SMark Cave-Ayland 
584346bb0137SMark Cave-Ayland     case DISAS_NORETURN:
584446bb0137SMark Cave-Ayland        break;
584546bb0137SMark Cave-Ayland 
584646bb0137SMark Cave-Ayland     case DISAS_EXIT:
584746bb0137SMark Cave-Ayland         /* Exit TB */
584846bb0137SMark Cave-Ayland         save_state(dc);
584946bb0137SMark Cave-Ayland         tcg_gen_exit_tb(NULL, 0);
585046bb0137SMark Cave-Ayland         break;
585146bb0137SMark Cave-Ayland 
585246bb0137SMark Cave-Ayland     default:
585346bb0137SMark Cave-Ayland         g_assert_not_reached();
5854fcf5ef2aSThomas Huth     }
5855fcf5ef2aSThomas Huth }
58566e61bc94SEmilio G. Cota 
58578eb806a7SRichard Henderson static void sparc_tr_disas_log(const DisasContextBase *dcbase,
58588eb806a7SRichard Henderson                                CPUState *cpu, FILE *logfile)
58596e61bc94SEmilio G. Cota {
58608eb806a7SRichard Henderson     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
58618eb806a7SRichard Henderson     target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
58626e61bc94SEmilio G. Cota }
58636e61bc94SEmilio G. Cota 
58646e61bc94SEmilio G. Cota static const TranslatorOps sparc_tr_ops = {
58656e61bc94SEmilio G. Cota     .init_disas_context = sparc_tr_init_disas_context,
58666e61bc94SEmilio G. Cota     .tb_start           = sparc_tr_tb_start,
58676e61bc94SEmilio G. Cota     .insn_start         = sparc_tr_insn_start,
58686e61bc94SEmilio G. Cota     .translate_insn     = sparc_tr_translate_insn,
58696e61bc94SEmilio G. Cota     .tb_stop            = sparc_tr_tb_stop,
58706e61bc94SEmilio G. Cota     .disas_log          = sparc_tr_disas_log,
58716e61bc94SEmilio G. Cota };
58726e61bc94SEmilio G. Cota 
5873597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
5874306c8721SRichard Henderson                            target_ulong pc, void *host_pc)
58756e61bc94SEmilio G. Cota {
58766e61bc94SEmilio G. Cota     DisasContext dc = {};
58776e61bc94SEmilio G. Cota 
5878306c8721SRichard Henderson     translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
5879fcf5ef2aSThomas Huth }
5880fcf5ef2aSThomas Huth 
588155c3ceefSRichard Henderson void sparc_tcg_init(void)
5882fcf5ef2aSThomas Huth {
5883fcf5ef2aSThomas Huth     static const char gregnames[32][4] = {
5884fcf5ef2aSThomas Huth         "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
5885fcf5ef2aSThomas Huth         "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5886fcf5ef2aSThomas Huth         "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5887fcf5ef2aSThomas Huth         "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
5888fcf5ef2aSThomas Huth     };
5889fcf5ef2aSThomas Huth     static const char fregnames[32][4] = {
5890fcf5ef2aSThomas Huth         "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5891fcf5ef2aSThomas Huth         "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5892fcf5ef2aSThomas Huth         "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5893fcf5ef2aSThomas Huth         "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5894fcf5ef2aSThomas Huth     };
5895fcf5ef2aSThomas Huth 
5896fcf5ef2aSThomas Huth     static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
5897fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5898fcf5ef2aSThomas Huth         { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
5899fcf5ef2aSThomas Huth         { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
5900fcf5ef2aSThomas Huth #else
5901fcf5ef2aSThomas Huth         { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5902fcf5ef2aSThomas Huth #endif
5903fcf5ef2aSThomas Huth         { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5904fcf5ef2aSThomas Huth         { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5905fcf5ef2aSThomas Huth     };
5906fcf5ef2aSThomas Huth 
5907fcf5ef2aSThomas Huth     static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5908fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5909fcf5ef2aSThomas Huth         { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5910fcf5ef2aSThomas Huth         { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5911fcf5ef2aSThomas Huth         { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5912fcf5ef2aSThomas Huth         { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5913fcf5ef2aSThomas Huth           "hstick_cmpr" },
5914fcf5ef2aSThomas Huth         { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5915fcf5ef2aSThomas Huth         { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5916fcf5ef2aSThomas Huth         { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5917fcf5ef2aSThomas Huth         { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5918fcf5ef2aSThomas Huth         { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
5919fcf5ef2aSThomas Huth #endif
5920fcf5ef2aSThomas Huth         { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5921fcf5ef2aSThomas Huth         { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5922fcf5ef2aSThomas Huth         { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5923fcf5ef2aSThomas Huth         { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5924fcf5ef2aSThomas Huth         { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5925fcf5ef2aSThomas Huth         { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5926fcf5ef2aSThomas Huth         { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5927fcf5ef2aSThomas Huth         { &cpu_y, offsetof(CPUSPARCState, y), "y" },
5928fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY
5929fcf5ef2aSThomas Huth         { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
5930fcf5ef2aSThomas Huth #endif
5931fcf5ef2aSThomas Huth     };
5932fcf5ef2aSThomas Huth 
5933fcf5ef2aSThomas Huth     unsigned int i;
5934fcf5ef2aSThomas Huth 
5935fcf5ef2aSThomas Huth     cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5936fcf5ef2aSThomas Huth                                          offsetof(CPUSPARCState, regwptr),
5937fcf5ef2aSThomas Huth                                          "regwptr");
5938fcf5ef2aSThomas Huth 
5939fcf5ef2aSThomas Huth     for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5940fcf5ef2aSThomas Huth         *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5941fcf5ef2aSThomas Huth     }
5942fcf5ef2aSThomas Huth 
5943fcf5ef2aSThomas Huth     for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5944fcf5ef2aSThomas Huth         *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5945fcf5ef2aSThomas Huth     }
5946fcf5ef2aSThomas Huth 
5947f764718dSRichard Henderson     cpu_regs[0] = NULL;
5948fcf5ef2aSThomas Huth     for (i = 1; i < 8; ++i) {
5949fcf5ef2aSThomas Huth         cpu_regs[i] = tcg_global_mem_new(cpu_env,
5950fcf5ef2aSThomas Huth                                          offsetof(CPUSPARCState, gregs[i]),
5951fcf5ef2aSThomas Huth                                          gregnames[i]);
5952fcf5ef2aSThomas Huth     }
5953fcf5ef2aSThomas Huth 
5954fcf5ef2aSThomas Huth     for (i = 8; i < 32; ++i) {
5955fcf5ef2aSThomas Huth         cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5956fcf5ef2aSThomas Huth                                          (i - 8) * sizeof(target_ulong),
5957fcf5ef2aSThomas Huth                                          gregnames[i]);
5958fcf5ef2aSThomas Huth     }
5959fcf5ef2aSThomas Huth 
5960fcf5ef2aSThomas Huth     for (i = 0; i < TARGET_DPREGS; i++) {
5961fcf5ef2aSThomas Huth         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5962fcf5ef2aSThomas Huth                                             offsetof(CPUSPARCState, fpr[i]),
5963fcf5ef2aSThomas Huth                                             fregnames[i]);
5964fcf5ef2aSThomas Huth     }
5965fcf5ef2aSThomas Huth }
5966fcf5ef2aSThomas Huth 
5967f36aaa53SRichard Henderson void sparc_restore_state_to_opc(CPUState *cs,
5968f36aaa53SRichard Henderson                                 const TranslationBlock *tb,
5969f36aaa53SRichard Henderson                                 const uint64_t *data)
5970fcf5ef2aSThomas Huth {
5971f36aaa53SRichard Henderson     SPARCCPU *cpu = SPARC_CPU(cs);
5972f36aaa53SRichard Henderson     CPUSPARCState *env = &cpu->env;
5973fcf5ef2aSThomas Huth     target_ulong pc = data[0];
5974fcf5ef2aSThomas Huth     target_ulong npc = data[1];
5975fcf5ef2aSThomas Huth 
5976fcf5ef2aSThomas Huth     env->pc = pc;
5977fcf5ef2aSThomas Huth     if (npc == DYNAMIC_PC) {
5978fcf5ef2aSThomas Huth         /* dynamic NPC: already stored */
5979fcf5ef2aSThomas Huth     } else if (npc & JUMP_PC) {
5980fcf5ef2aSThomas Huth         /* jump PC: use 'cond' and the jump targets of the translation */
5981fcf5ef2aSThomas Huth         if (env->cond) {
5982fcf5ef2aSThomas Huth             env->npc = npc & ~3;
5983fcf5ef2aSThomas Huth         } else {
5984fcf5ef2aSThomas Huth             env->npc = pc + 4;
5985fcf5ef2aSThomas Huth         }
5986fcf5ef2aSThomas Huth     } else {
5987fcf5ef2aSThomas Huth         env->npc = npc;
5988fcf5ef2aSThomas Huth     }
5989fcf5ef2aSThomas Huth }
5990