xref: /openbmc/qemu/target/sparc/translate.c (revision 0b2a61cc26caa8e3ba6425f7c4159aa75fe520b9)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth    SPARC translation
3fcf5ef2aSThomas Huth 
4fcf5ef2aSThomas Huth    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5fcf5ef2aSThomas Huth    Copyright (C) 2003-2005 Fabrice Bellard
6fcf5ef2aSThomas Huth 
7fcf5ef2aSThomas Huth    This library is free software; you can redistribute it and/or
8fcf5ef2aSThomas Huth    modify it under the terms of the GNU Lesser General Public
9fcf5ef2aSThomas Huth    License as published by the Free Software Foundation; either
105650b549SChetan Pant    version 2.1 of the License, or (at your option) any later version.
11fcf5ef2aSThomas Huth 
12fcf5ef2aSThomas Huth    This library is distributed in the hope that it will be useful,
13fcf5ef2aSThomas Huth    but WITHOUT ANY WARRANTY; without even the implied warranty of
14fcf5ef2aSThomas Huth    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15fcf5ef2aSThomas Huth    Lesser General Public License for more details.
16fcf5ef2aSThomas Huth 
17fcf5ef2aSThomas Huth    You should have received a copy of the GNU Lesser General Public
18fcf5ef2aSThomas Huth    License along with this library; if not, see <http://www.gnu.org/licenses/>.
19fcf5ef2aSThomas Huth  */
20fcf5ef2aSThomas Huth 
21fcf5ef2aSThomas Huth #include "qemu/osdep.h"
22fcf5ef2aSThomas Huth 
23fcf5ef2aSThomas Huth #include "cpu.h"
24fcf5ef2aSThomas Huth #include "disas/disas.h"
25fcf5ef2aSThomas Huth #include "exec/helper-proto.h"
26fcf5ef2aSThomas Huth #include "exec/exec-all.h"
27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h"
28fafba1bbSRichard Henderson #include "tcg/tcg-op-gvec.h"
29fcf5ef2aSThomas Huth #include "exec/helper-gen.h"
30c5e6ccdfSEmilio G. Cota #include "exec/translator.h"
31fcf5ef2aSThomas Huth #include "exec/log.h"
32fcf5ef2aSThomas Huth #include "asi.h"
33fcf5ef2aSThomas Huth 
34d53106c9SRichard Henderson #define HELPER_H "helper.h"
35d53106c9SRichard Henderson #include "exec/helper-info.c.inc"
36d53106c9SRichard Henderson #undef  HELPER_H
37fcf5ef2aSThomas Huth 
38668bb9b7SRichard Henderson #ifdef TARGET_SPARC64
39668bb9b7SRichard Henderson # define gen_helper_rdpsr(D, E)                 qemu_build_not_reached()
4086b82fe0SRichard Henderson # define gen_helper_rett(E)                     qemu_build_not_reached()
410faef01bSRichard Henderson # define gen_helper_power_down(E)               qemu_build_not_reached()
4225524734SRichard Henderson # define gen_helper_wrpsr(E, S)                 qemu_build_not_reached()
43668bb9b7SRichard Henderson #else
440faef01bSRichard Henderson # define gen_helper_clear_softint(E, S)         qemu_build_not_reached()
458f75b8a4SRichard Henderson # define gen_helper_done(E)                     qemu_build_not_reached()
46e8325dc0SRichard Henderson # define gen_helper_flushw(E)                   qemu_build_not_reached()
47af25071cSRichard Henderson # define gen_helper_rdccr(D, E)                 qemu_build_not_reached()
485d617bfbSRichard Henderson # define gen_helper_rdcwp(D, E)                 qemu_build_not_reached()
4925524734SRichard Henderson # define gen_helper_restored(E)                 qemu_build_not_reached()
508f75b8a4SRichard Henderson # define gen_helper_retry(E)                    qemu_build_not_reached()
5125524734SRichard Henderson # define gen_helper_saved(E)                    qemu_build_not_reached()
520faef01bSRichard Henderson # define gen_helper_set_softint(E, S)           qemu_build_not_reached()
53af25071cSRichard Henderson # define gen_helper_tick_get_count(D, E, T, C)  qemu_build_not_reached()
549422278eSRichard Henderson # define gen_helper_tick_set_count(P, S)        qemu_build_not_reached()
55bb97f2f5SRichard Henderson # define gen_helper_tick_set_limit(P, S)        qemu_build_not_reached()
560faef01bSRichard Henderson # define gen_helper_wrccr(E, S)                 qemu_build_not_reached()
579422278eSRichard Henderson # define gen_helper_wrcwp(E, S)                 qemu_build_not_reached()
589422278eSRichard Henderson # define gen_helper_wrgl(E, S)                  qemu_build_not_reached()
590faef01bSRichard Henderson # define gen_helper_write_softint(E, S)         qemu_build_not_reached()
609422278eSRichard Henderson # define gen_helper_wrpil(E, S)                 qemu_build_not_reached()
619422278eSRichard Henderson # define gen_helper_wrpstate(E, S)              qemu_build_not_reached()
62e2fa6bd1SRichard Henderson # define gen_helper_fcmpeq16             ({ qemu_build_not_reached(); NULL; })
63e2fa6bd1SRichard Henderson # define gen_helper_fcmpeq32             ({ qemu_build_not_reached(); NULL; })
64e2fa6bd1SRichard Henderson # define gen_helper_fcmpgt16             ({ qemu_build_not_reached(); NULL; })
65e2fa6bd1SRichard Henderson # define gen_helper_fcmpgt32             ({ qemu_build_not_reached(); NULL; })
66e2fa6bd1SRichard Henderson # define gen_helper_fcmple16             ({ qemu_build_not_reached(); NULL; })
67e2fa6bd1SRichard Henderson # define gen_helper_fcmple32             ({ qemu_build_not_reached(); NULL; })
68e2fa6bd1SRichard Henderson # define gen_helper_fcmpne16             ({ qemu_build_not_reached(); NULL; })
69e2fa6bd1SRichard Henderson # define gen_helper_fcmpne32             ({ qemu_build_not_reached(); NULL; })
708aa418b3SRichard Henderson # define gen_helper_fdtox                ({ qemu_build_not_reached(); NULL; })
71e06c9f83SRichard Henderson # define gen_helper_fexpand              ({ qemu_build_not_reached(); NULL; })
72e06c9f83SRichard Henderson # define gen_helper_fmul8sux16           ({ qemu_build_not_reached(); NULL; })
73e06c9f83SRichard Henderson # define gen_helper_fmul8ulx16           ({ qemu_build_not_reached(); NULL; })
74e06c9f83SRichard Henderson # define gen_helper_fmul8x16al           ({ qemu_build_not_reached(); NULL; })
75e06c9f83SRichard Henderson # define gen_helper_fmul8x16au           ({ qemu_build_not_reached(); NULL; })
76e06c9f83SRichard Henderson # define gen_helper_fmul8x16             ({ qemu_build_not_reached(); NULL; })
77e06c9f83SRichard Henderson # define gen_helper_fmuld8sux16          ({ qemu_build_not_reached(); NULL; })
78e06c9f83SRichard Henderson # define gen_helper_fmuld8ulx16          ({ qemu_build_not_reached(); NULL; })
79e06c9f83SRichard Henderson # define gen_helper_fpmerge              ({ qemu_build_not_reached(); NULL; })
801617586fSRichard Henderson # define gen_helper_fqtox                ({ qemu_build_not_reached(); NULL; })
81199d43efSRichard Henderson # define gen_helper_fstox                ({ qemu_build_not_reached(); NULL; })
828aa418b3SRichard Henderson # define gen_helper_fxtod                ({ qemu_build_not_reached(); NULL; })
837b8e3e1aSRichard Henderson # define gen_helper_fxtoq                ({ qemu_build_not_reached(); NULL; })
84f4e18df5SRichard Henderson # define gen_helper_fxtos                ({ qemu_build_not_reached(); NULL; })
85afb04344SRichard Henderson # define gen_helper_pdist                ({ qemu_build_not_reached(); NULL; })
86da681406SRichard Henderson # define FSR_LDXFSR_MASK                        0
87da681406SRichard Henderson # define FSR_LDXFSR_OLDMASK                     0
88668bb9b7SRichard Henderson # define MAXTL_MASK                             0
89af25071cSRichard Henderson #endif
90af25071cSRichard Henderson 
91633c4283SRichard Henderson /* Dynamic PC, must exit to main loop. */
92633c4283SRichard Henderson #define DYNAMIC_PC         1
93633c4283SRichard Henderson /* Dynamic PC, one of two values according to jump_pc[T2]. */
94633c4283SRichard Henderson #define JUMP_PC            2
95633c4283SRichard Henderson /* Dynamic PC, may lookup next TB. */
96633c4283SRichard Henderson #define DYNAMIC_PC_LOOKUP  3
97fcf5ef2aSThomas Huth 
9846bb0137SMark Cave-Ayland #define DISAS_EXIT  DISAS_TARGET_0
9946bb0137SMark Cave-Ayland 
100fcf5ef2aSThomas Huth /* global register indexes */
101fcf5ef2aSThomas Huth static TCGv_ptr cpu_regwptr;
102fcf5ef2aSThomas Huth static TCGv cpu_fsr, cpu_pc, cpu_npc;
103fcf5ef2aSThomas Huth static TCGv cpu_regs[32];
104fcf5ef2aSThomas Huth static TCGv cpu_y;
105fcf5ef2aSThomas Huth static TCGv cpu_tbr;
106fcf5ef2aSThomas Huth static TCGv cpu_cond;
1072a1905c7SRichard Henderson static TCGv cpu_cc_N;
1082a1905c7SRichard Henderson static TCGv cpu_cc_V;
1092a1905c7SRichard Henderson static TCGv cpu_icc_Z;
1102a1905c7SRichard Henderson static TCGv cpu_icc_C;
111fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1122a1905c7SRichard Henderson static TCGv cpu_xcc_Z;
1132a1905c7SRichard Henderson static TCGv cpu_xcc_C;
1142a1905c7SRichard Henderson static TCGv_i32 cpu_fprs;
115fcf5ef2aSThomas Huth static TCGv cpu_gsr;
116fcf5ef2aSThomas Huth #else
117af25071cSRichard Henderson # define cpu_fprs               ({ qemu_build_not_reached(); (TCGv)NULL; })
118af25071cSRichard Henderson # define cpu_gsr                ({ qemu_build_not_reached(); (TCGv)NULL; })
119fcf5ef2aSThomas Huth #endif
1202a1905c7SRichard Henderson 
1212a1905c7SRichard Henderson #ifdef TARGET_SPARC64
1222a1905c7SRichard Henderson #define cpu_cc_Z  cpu_xcc_Z
1232a1905c7SRichard Henderson #define cpu_cc_C  cpu_xcc_C
1242a1905c7SRichard Henderson #else
1252a1905c7SRichard Henderson #define cpu_cc_Z  cpu_icc_Z
1262a1905c7SRichard Henderson #define cpu_cc_C  cpu_icc_C
1272a1905c7SRichard Henderson #define cpu_xcc_Z ({ qemu_build_not_reached(); NULL; })
1282a1905c7SRichard Henderson #define cpu_xcc_C ({ qemu_build_not_reached(); NULL; })
1292a1905c7SRichard Henderson #endif
1302a1905c7SRichard Henderson 
131fcf5ef2aSThomas Huth /* Floating point registers */
132fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[TARGET_DPREGS];
133fcf5ef2aSThomas Huth 
134af25071cSRichard Henderson #define env_field_offsetof(X)     offsetof(CPUSPARCState, X)
135af25071cSRichard Henderson #ifdef TARGET_SPARC64
136cd6269f7SRichard Henderson # define env32_field_offsetof(X)  ({ qemu_build_not_reached(); 0; })
137af25071cSRichard Henderson # define env64_field_offsetof(X)  env_field_offsetof(X)
138af25071cSRichard Henderson #else
139cd6269f7SRichard Henderson # define env32_field_offsetof(X)  env_field_offsetof(X)
140af25071cSRichard Henderson # define env64_field_offsetof(X)  ({ qemu_build_not_reached(); 0; })
141af25071cSRichard Henderson #endif
142af25071cSRichard Henderson 
143533f042fSRichard Henderson typedef struct DisasCompare {
144533f042fSRichard Henderson     TCGCond cond;
145533f042fSRichard Henderson     TCGv c1;
146533f042fSRichard Henderson     int c2;
147533f042fSRichard Henderson } DisasCompare;
148533f042fSRichard Henderson 
149186e7890SRichard Henderson typedef struct DisasDelayException {
150186e7890SRichard Henderson     struct DisasDelayException *next;
151186e7890SRichard Henderson     TCGLabel *lab;
152186e7890SRichard Henderson     TCGv_i32 excp;
153186e7890SRichard Henderson     /* Saved state at parent insn. */
154186e7890SRichard Henderson     target_ulong pc;
155186e7890SRichard Henderson     target_ulong npc;
156186e7890SRichard Henderson } DisasDelayException;
157186e7890SRichard Henderson 
158fcf5ef2aSThomas Huth typedef struct DisasContext {
159af00be49SEmilio G. Cota     DisasContextBase base;
160fcf5ef2aSThomas Huth     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
161fcf5ef2aSThomas Huth     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
162533f042fSRichard Henderson 
163533f042fSRichard Henderson     /* Used when JUMP_PC value is used. */
164533f042fSRichard Henderson     DisasCompare jump;
165533f042fSRichard Henderson     target_ulong jump_pc[2];
166533f042fSRichard Henderson 
167fcf5ef2aSThomas Huth     int mem_idx;
16889527e3aSRichard Henderson     bool cpu_cond_live;
169c9b459aaSArtyom Tarasenko     bool fpu_enabled;
170c9b459aaSArtyom Tarasenko     bool address_mask_32bit;
171c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
172c9b459aaSArtyom Tarasenko     bool supervisor;
173c9b459aaSArtyom Tarasenko #ifdef TARGET_SPARC64
174c9b459aaSArtyom Tarasenko     bool hypervisor;
175c9b459aaSArtyom Tarasenko #endif
176c9b459aaSArtyom Tarasenko #endif
177c9b459aaSArtyom Tarasenko 
178fcf5ef2aSThomas Huth     sparc_def_t *def;
179fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
180fcf5ef2aSThomas Huth     int fprs_dirty;
181fcf5ef2aSThomas Huth     int asi;
182fcf5ef2aSThomas Huth #endif
183186e7890SRichard Henderson     DisasDelayException *delay_excp_list;
184fcf5ef2aSThomas Huth } DisasContext;
185fcf5ef2aSThomas Huth 
186fcf5ef2aSThomas Huth // This function uses non-native bit order
187fcf5ef2aSThomas Huth #define GET_FIELD(X, FROM, TO)                                  \
188fcf5ef2aSThomas Huth     ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
189fcf5ef2aSThomas Huth 
190fcf5ef2aSThomas Huth // This function uses the order in the manuals, i.e. bit 0 is 2^0
191fcf5ef2aSThomas Huth #define GET_FIELD_SP(X, FROM, TO)               \
192fcf5ef2aSThomas Huth     GET_FIELD(X, 31 - (TO), 31 - (FROM))
193fcf5ef2aSThomas Huth 
194fcf5ef2aSThomas Huth #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
195fcf5ef2aSThomas Huth #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
196fcf5ef2aSThomas Huth 
197fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
198fcf5ef2aSThomas Huth #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
199fcf5ef2aSThomas Huth #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
200fcf5ef2aSThomas Huth #else
201fcf5ef2aSThomas Huth #define DFPREG(r) (r & 0x1e)
202fcf5ef2aSThomas Huth #define QFPREG(r) (r & 0x1c)
203fcf5ef2aSThomas Huth #endif
204fcf5ef2aSThomas Huth 
205fcf5ef2aSThomas Huth #define UA2005_HTRAP_MASK 0xff
206fcf5ef2aSThomas Huth #define V8_TRAP_MASK 0x7f
207fcf5ef2aSThomas Huth 
208fcf5ef2aSThomas Huth #define IS_IMM (insn & (1<<13))
209fcf5ef2aSThomas Huth 
2100c2e96c1SRichard Henderson static void gen_update_fprs_dirty(DisasContext *dc, int rd)
211fcf5ef2aSThomas Huth {
212fcf5ef2aSThomas Huth #if defined(TARGET_SPARC64)
213fcf5ef2aSThomas Huth     int bit = (rd < 32) ? 1 : 2;
214fcf5ef2aSThomas Huth     /* If we know we've already set this bit within the TB,
215fcf5ef2aSThomas Huth        we can avoid setting it again.  */
216fcf5ef2aSThomas Huth     if (!(dc->fprs_dirty & bit)) {
217fcf5ef2aSThomas Huth         dc->fprs_dirty |= bit;
218fcf5ef2aSThomas Huth         tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
219fcf5ef2aSThomas Huth     }
220fcf5ef2aSThomas Huth #endif
221fcf5ef2aSThomas Huth }
222fcf5ef2aSThomas Huth 
223fcf5ef2aSThomas Huth /* floating point registers moves */
224fcf5ef2aSThomas Huth static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
225fcf5ef2aSThomas Huth {
22636ab4623SRichard Henderson     TCGv_i32 ret = tcg_temp_new_i32();
227dc41aa7dSRichard Henderson     if (src & 1) {
228dc41aa7dSRichard Henderson         tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
229dc41aa7dSRichard Henderson     } else {
230dc41aa7dSRichard Henderson         tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
231fcf5ef2aSThomas Huth     }
232dc41aa7dSRichard Henderson     return ret;
233fcf5ef2aSThomas Huth }
234fcf5ef2aSThomas Huth 
235fcf5ef2aSThomas Huth static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
236fcf5ef2aSThomas Huth {
2378e7bbc75SRichard Henderson     TCGv_i64 t = tcg_temp_new_i64();
2388e7bbc75SRichard Henderson 
2398e7bbc75SRichard Henderson     tcg_gen_extu_i32_i64(t, v);
240fcf5ef2aSThomas Huth     tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
241fcf5ef2aSThomas Huth                         (dst & 1 ? 0 : 32), 32);
242fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, dst);
243fcf5ef2aSThomas Huth }
244fcf5ef2aSThomas Huth 
245fcf5ef2aSThomas Huth static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
246fcf5ef2aSThomas Huth {
247fcf5ef2aSThomas Huth     src = DFPREG(src);
248fcf5ef2aSThomas Huth     return cpu_fpr[src / 2];
249fcf5ef2aSThomas Huth }
250fcf5ef2aSThomas Huth 
251fcf5ef2aSThomas Huth static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
252fcf5ef2aSThomas Huth {
253fcf5ef2aSThomas Huth     dst = DFPREG(dst);
254fcf5ef2aSThomas Huth     tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
255fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, dst);
256fcf5ef2aSThomas Huth }
257fcf5ef2aSThomas Huth 
258fcf5ef2aSThomas Huth static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
259fcf5ef2aSThomas Huth {
260fcf5ef2aSThomas Huth     return cpu_fpr[DFPREG(dst) / 2];
261fcf5ef2aSThomas Huth }
262fcf5ef2aSThomas Huth 
26333ec4245SRichard Henderson static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src)
26433ec4245SRichard Henderson {
26533ec4245SRichard Henderson     TCGv_i128 ret = tcg_temp_new_i128();
26633ec4245SRichard Henderson 
26733ec4245SRichard Henderson     src = QFPREG(src);
26833ec4245SRichard Henderson     tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]);
26933ec4245SRichard Henderson     return ret;
27033ec4245SRichard Henderson }
27133ec4245SRichard Henderson 
27233ec4245SRichard Henderson static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 v)
27333ec4245SRichard Henderson {
27433ec4245SRichard Henderson     dst = DFPREG(dst);
27533ec4245SRichard Henderson     tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v);
27633ec4245SRichard Henderson     gen_update_fprs_dirty(dc, dst);
27733ec4245SRichard Henderson }
27833ec4245SRichard Henderson 
279fcf5ef2aSThomas Huth static void gen_op_store_QT0_fpr(unsigned int dst)
280fcf5ef2aSThomas Huth {
281ad75a51eSRichard Henderson     tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
282fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.upper));
283ad75a51eSRichard Henderson     tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
284fcf5ef2aSThomas Huth                    offsetof(CPU_QuadU, ll.lower));
285fcf5ef2aSThomas Huth }
286fcf5ef2aSThomas Huth 
287fcf5ef2aSThomas Huth /* moves */
288fcf5ef2aSThomas Huth #ifdef CONFIG_USER_ONLY
289fcf5ef2aSThomas Huth #define supervisor(dc) 0
290fcf5ef2aSThomas Huth #define hypervisor(dc) 0
291fcf5ef2aSThomas Huth #else
292fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
293c9b459aaSArtyom Tarasenko #define hypervisor(dc) (dc->hypervisor)
294c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor | dc->hypervisor)
295fcf5ef2aSThomas Huth #else
296c9b459aaSArtyom Tarasenko #define supervisor(dc) (dc->supervisor)
297668bb9b7SRichard Henderson #define hypervisor(dc) 0
298fcf5ef2aSThomas Huth #endif
299fcf5ef2aSThomas Huth #endif
300fcf5ef2aSThomas Huth 
301b1bc09eaSRichard Henderson #if !defined(TARGET_SPARC64)
302b1bc09eaSRichard Henderson # define AM_CHECK(dc)  false
303b1bc09eaSRichard Henderson #elif defined(TARGET_ABI32)
304b1bc09eaSRichard Henderson # define AM_CHECK(dc)  true
305b1bc09eaSRichard Henderson #elif defined(CONFIG_USER_ONLY)
306b1bc09eaSRichard Henderson # define AM_CHECK(dc)  false
307fcf5ef2aSThomas Huth #else
308b1bc09eaSRichard Henderson # define AM_CHECK(dc)  ((dc)->address_mask_32bit)
309fcf5ef2aSThomas Huth #endif
310fcf5ef2aSThomas Huth 
3110c2e96c1SRichard Henderson static void gen_address_mask(DisasContext *dc, TCGv addr)
312fcf5ef2aSThomas Huth {
313b1bc09eaSRichard Henderson     if (AM_CHECK(dc)) {
314fcf5ef2aSThomas Huth         tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
315b1bc09eaSRichard Henderson     }
316fcf5ef2aSThomas Huth }
317fcf5ef2aSThomas Huth 
31823ada1b1SRichard Henderson static target_ulong address_mask_i(DisasContext *dc, target_ulong addr)
31923ada1b1SRichard Henderson {
32023ada1b1SRichard Henderson     return AM_CHECK(dc) ? (uint32_t)addr : addr;
32123ada1b1SRichard Henderson }
32223ada1b1SRichard Henderson 
3230c2e96c1SRichard Henderson static TCGv gen_load_gpr(DisasContext *dc, int reg)
324fcf5ef2aSThomas Huth {
325fcf5ef2aSThomas Huth     if (reg > 0) {
326fcf5ef2aSThomas Huth         assert(reg < 32);
327fcf5ef2aSThomas Huth         return cpu_regs[reg];
328fcf5ef2aSThomas Huth     } else {
32952123f14SRichard Henderson         TCGv t = tcg_temp_new();
330fcf5ef2aSThomas Huth         tcg_gen_movi_tl(t, 0);
331fcf5ef2aSThomas Huth         return t;
332fcf5ef2aSThomas Huth     }
333fcf5ef2aSThomas Huth }
334fcf5ef2aSThomas Huth 
3350c2e96c1SRichard Henderson static void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
336fcf5ef2aSThomas Huth {
337fcf5ef2aSThomas Huth     if (reg > 0) {
338fcf5ef2aSThomas Huth         assert(reg < 32);
339fcf5ef2aSThomas Huth         tcg_gen_mov_tl(cpu_regs[reg], v);
340fcf5ef2aSThomas Huth     }
341fcf5ef2aSThomas Huth }
342fcf5ef2aSThomas Huth 
3430c2e96c1SRichard Henderson static TCGv gen_dest_gpr(DisasContext *dc, int reg)
344fcf5ef2aSThomas Huth {
345fcf5ef2aSThomas Huth     if (reg > 0) {
346fcf5ef2aSThomas Huth         assert(reg < 32);
347fcf5ef2aSThomas Huth         return cpu_regs[reg];
348fcf5ef2aSThomas Huth     } else {
34952123f14SRichard Henderson         return tcg_temp_new();
350fcf5ef2aSThomas Huth     }
351fcf5ef2aSThomas Huth }
352fcf5ef2aSThomas Huth 
3535645aa2eSRichard Henderson static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
354fcf5ef2aSThomas Huth {
3555645aa2eSRichard Henderson     return translator_use_goto_tb(&s->base, pc) &&
3565645aa2eSRichard Henderson            translator_use_goto_tb(&s->base, npc);
357fcf5ef2aSThomas Huth }
358fcf5ef2aSThomas Huth 
3595645aa2eSRichard Henderson static void gen_goto_tb(DisasContext *s, int tb_num,
360fcf5ef2aSThomas Huth                         target_ulong pc, target_ulong npc)
361fcf5ef2aSThomas Huth {
362fcf5ef2aSThomas Huth     if (use_goto_tb(s, pc, npc))  {
363fcf5ef2aSThomas Huth         /* jump to same page: we can use a direct jump */
364fcf5ef2aSThomas Huth         tcg_gen_goto_tb(tb_num);
365fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_pc, pc);
366fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, npc);
36707ea28b4SRichard Henderson         tcg_gen_exit_tb(s->base.tb, tb_num);
368fcf5ef2aSThomas Huth     } else {
369f67ccb2fSRichard Henderson         /* jump to another page: we can use an indirect jump */
370fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_pc, pc);
371fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, npc);
372f67ccb2fSRichard Henderson         tcg_gen_lookup_and_goto_ptr();
373fcf5ef2aSThomas Huth     }
374fcf5ef2aSThomas Huth }
375fcf5ef2aSThomas Huth 
376b989ce73SRichard Henderson static TCGv gen_carry32(void)
377fcf5ef2aSThomas Huth {
378b989ce73SRichard Henderson     if (TARGET_LONG_BITS == 64) {
379b989ce73SRichard Henderson         TCGv t = tcg_temp_new();
380b989ce73SRichard Henderson         tcg_gen_extract_tl(t, cpu_icc_C, 32, 1);
381b989ce73SRichard Henderson         return t;
382b989ce73SRichard Henderson     }
383b989ce73SRichard Henderson     return cpu_icc_C;
384fcf5ef2aSThomas Huth }
385fcf5ef2aSThomas Huth 
386b989ce73SRichard Henderson static void gen_op_addcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin)
387fcf5ef2aSThomas Huth {
388b989ce73SRichard Henderson     TCGv z = tcg_constant_tl(0);
389fcf5ef2aSThomas Huth 
390b989ce73SRichard Henderson     if (cin) {
391b989ce73SRichard Henderson         tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, cin, z);
392b989ce73SRichard Henderson         tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, cpu_cc_N, cpu_cc_C, src2, z);
393b989ce73SRichard Henderson     } else {
394b989ce73SRichard Henderson         tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, src2, z);
395b989ce73SRichard Henderson     }
396b989ce73SRichard Henderson     tcg_gen_xor_tl(cpu_cc_Z, src1, src2);
397b989ce73SRichard Henderson     tcg_gen_xor_tl(cpu_cc_V, cpu_cc_N, src2);
398b989ce73SRichard Henderson     tcg_gen_andc_tl(cpu_cc_V, cpu_cc_V, cpu_cc_Z);
399b989ce73SRichard Henderson     if (TARGET_LONG_BITS == 64) {
400b989ce73SRichard Henderson         /*
401b989ce73SRichard Henderson          * Carry-in to bit 32 is result ^ src1 ^ src2.
402b989ce73SRichard Henderson          * We already have the src xor term in Z, from computation of V.
403b989ce73SRichard Henderson          */
404b989ce73SRichard Henderson         tcg_gen_xor_tl(cpu_icc_C, cpu_cc_Z, cpu_cc_N);
405b989ce73SRichard Henderson         tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N);
406b989ce73SRichard Henderson     }
407b989ce73SRichard Henderson     tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
408b989ce73SRichard Henderson     tcg_gen_mov_tl(dst, cpu_cc_N);
409b989ce73SRichard Henderson }
410fcf5ef2aSThomas Huth 
411b989ce73SRichard Henderson static void gen_op_addcc(TCGv dst, TCGv src1, TCGv src2)
412b989ce73SRichard Henderson {
413b989ce73SRichard Henderson     gen_op_addcc_int(dst, src1, src2, NULL);
414b989ce73SRichard Henderson }
415fcf5ef2aSThomas Huth 
416b989ce73SRichard Henderson static void gen_op_taddcc(TCGv dst, TCGv src1, TCGv src2)
417b989ce73SRichard Henderson {
418b989ce73SRichard Henderson     TCGv t = tcg_temp_new();
419b989ce73SRichard Henderson 
420b989ce73SRichard Henderson     /* Save the tag bits around modification of dst. */
421b989ce73SRichard Henderson     tcg_gen_or_tl(t, src1, src2);
422b989ce73SRichard Henderson 
423b989ce73SRichard Henderson     gen_op_addcc(dst, src1, src2);
424b989ce73SRichard Henderson 
425b989ce73SRichard Henderson     /* Incorprate tag bits into icc.V */
426b989ce73SRichard Henderson     tcg_gen_andi_tl(t, t, 3);
427b989ce73SRichard Henderson     tcg_gen_neg_tl(t, t);
428b989ce73SRichard Henderson     tcg_gen_ext32u_tl(t, t);
429b989ce73SRichard Henderson     tcg_gen_or_tl(cpu_cc_V, cpu_cc_V, t);
430b989ce73SRichard Henderson }
431b989ce73SRichard Henderson 
432b989ce73SRichard Henderson static void gen_op_addc(TCGv dst, TCGv src1, TCGv src2)
433b989ce73SRichard Henderson {
434b989ce73SRichard Henderson     tcg_gen_add_tl(dst, src1, src2);
435b989ce73SRichard Henderson     tcg_gen_add_tl(dst, dst, gen_carry32());
436b989ce73SRichard Henderson }
437b989ce73SRichard Henderson 
438b989ce73SRichard Henderson static void gen_op_addccc(TCGv dst, TCGv src1, TCGv src2)
439b989ce73SRichard Henderson {
440b989ce73SRichard Henderson     gen_op_addcc_int(dst, src1, src2, gen_carry32());
441fcf5ef2aSThomas Huth }
442fcf5ef2aSThomas Huth 
443f828df74SRichard Henderson static void gen_op_subcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin)
444fcf5ef2aSThomas Huth {
445f828df74SRichard Henderson     TCGv z = tcg_constant_tl(0);
446fcf5ef2aSThomas Huth 
447f828df74SRichard Henderson     if (cin) {
448f828df74SRichard Henderson         tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, src1, z, cin, z);
449f828df74SRichard Henderson         tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, cpu_cc_N, cpu_cc_C, src2, z);
450f828df74SRichard Henderson     } else {
451f828df74SRichard Henderson         tcg_gen_sub2_tl(cpu_cc_N, cpu_cc_C, src1, z, src2, z);
452f828df74SRichard Henderson     }
453f828df74SRichard Henderson     tcg_gen_neg_tl(cpu_cc_C, cpu_cc_C);
454f828df74SRichard Henderson     tcg_gen_xor_tl(cpu_cc_Z, src1, src2);
455f828df74SRichard Henderson     tcg_gen_xor_tl(cpu_cc_V, cpu_cc_N, src1);
456f828df74SRichard Henderson     tcg_gen_and_tl(cpu_cc_V, cpu_cc_V, cpu_cc_Z);
457f828df74SRichard Henderson #ifdef TARGET_SPARC64
458f828df74SRichard Henderson     tcg_gen_xor_tl(cpu_icc_C, cpu_cc_Z, cpu_cc_N);
459f828df74SRichard Henderson     tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N);
460fcf5ef2aSThomas Huth #endif
461f828df74SRichard Henderson     tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
462f828df74SRichard Henderson     tcg_gen_mov_tl(dst, cpu_cc_N);
463fcf5ef2aSThomas Huth }
464fcf5ef2aSThomas Huth 
465f828df74SRichard Henderson static void gen_op_subcc(TCGv dst, TCGv src1, TCGv src2)
466fcf5ef2aSThomas Huth {
467f828df74SRichard Henderson     gen_op_subcc_int(dst, src1, src2, NULL);
468fcf5ef2aSThomas Huth }
469fcf5ef2aSThomas Huth 
470f828df74SRichard Henderson static void gen_op_tsubcc(TCGv dst, TCGv src1, TCGv src2)
471fcf5ef2aSThomas Huth {
472f828df74SRichard Henderson     TCGv t = tcg_temp_new();
473fcf5ef2aSThomas Huth 
474f828df74SRichard Henderson     /* Save the tag bits around modification of dst. */
475f828df74SRichard Henderson     tcg_gen_or_tl(t, src1, src2);
476fcf5ef2aSThomas Huth 
477f828df74SRichard Henderson     gen_op_subcc(dst, src1, src2);
478f828df74SRichard Henderson 
479f828df74SRichard Henderson     /* Incorprate tag bits into icc.V */
480f828df74SRichard Henderson     tcg_gen_andi_tl(t, t, 3);
481f828df74SRichard Henderson     tcg_gen_neg_tl(t, t);
482f828df74SRichard Henderson     tcg_gen_ext32u_tl(t, t);
483f828df74SRichard Henderson     tcg_gen_or_tl(cpu_cc_V, cpu_cc_V, t);
484f828df74SRichard Henderson }
485f828df74SRichard Henderson 
486f828df74SRichard Henderson static void gen_op_subc(TCGv dst, TCGv src1, TCGv src2)
487f828df74SRichard Henderson {
488fcf5ef2aSThomas Huth     tcg_gen_sub_tl(dst, src1, src2);
489f828df74SRichard Henderson     tcg_gen_sub_tl(dst, dst, gen_carry32());
490fcf5ef2aSThomas Huth }
491fcf5ef2aSThomas Huth 
492f828df74SRichard Henderson static void gen_op_subccc(TCGv dst, TCGv src1, TCGv src2)
493dfebb950SRichard Henderson {
494f828df74SRichard Henderson     gen_op_subcc_int(dst, src1, src2, gen_carry32());
495dfebb950SRichard Henderson }
496dfebb950SRichard Henderson 
4970c2e96c1SRichard Henderson static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
498fcf5ef2aSThomas Huth {
499b989ce73SRichard Henderson     TCGv zero = tcg_constant_tl(0);
500b989ce73SRichard Henderson     TCGv t_src1 = tcg_temp_new();
501b989ce73SRichard Henderson     TCGv t_src2 = tcg_temp_new();
502b989ce73SRichard Henderson     TCGv t0 = tcg_temp_new();
503fcf5ef2aSThomas Huth 
504b989ce73SRichard Henderson     tcg_gen_ext32u_tl(t_src1, src1);
505b989ce73SRichard Henderson     tcg_gen_ext32u_tl(t_src2, src2);
506fcf5ef2aSThomas Huth 
507b989ce73SRichard Henderson     /*
508b989ce73SRichard Henderson      * if (!(env->y & 1))
509b989ce73SRichard Henderson      *   src2 = 0;
510fcf5ef2aSThomas Huth      */
511b989ce73SRichard Henderson     tcg_gen_andi_tl(t0, cpu_y, 0x1);
512b989ce73SRichard Henderson     tcg_gen_movcond_tl(TCG_COND_EQ, t_src2, t0, zero, zero, t_src2);
513fcf5ef2aSThomas Huth 
514b989ce73SRichard Henderson     /*
515b989ce73SRichard Henderson      * b2 = src1 & 1;
516b989ce73SRichard Henderson      * y = (b2 << 31) | (y >> 1);
517b989ce73SRichard Henderson      */
5180b1183e3SPhilippe Mathieu-Daudé     tcg_gen_extract_tl(t0, cpu_y, 1, 31);
519b989ce73SRichard Henderson     tcg_gen_deposit_tl(cpu_y, t0, src1, 31, 1);
520fcf5ef2aSThomas Huth 
521fcf5ef2aSThomas Huth     // b1 = N ^ V;
5222a1905c7SRichard Henderson     tcg_gen_xor_tl(t0, cpu_cc_N, cpu_cc_V);
523fcf5ef2aSThomas Huth 
524b989ce73SRichard Henderson     /*
525b989ce73SRichard Henderson      * src1 = (b1 << 31) | (src1 >> 1)
526b989ce73SRichard Henderson      */
5272a1905c7SRichard Henderson     tcg_gen_andi_tl(t0, t0, 1u << 31);
528b989ce73SRichard Henderson     tcg_gen_shri_tl(t_src1, t_src1, 1);
529b989ce73SRichard Henderson     tcg_gen_or_tl(t_src1, t_src1, t0);
530fcf5ef2aSThomas Huth 
531b989ce73SRichard Henderson     gen_op_addcc(dst, t_src1, t_src2);
532fcf5ef2aSThomas Huth }
533fcf5ef2aSThomas Huth 
5340c2e96c1SRichard Henderson static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
535fcf5ef2aSThomas Huth {
536fcf5ef2aSThomas Huth #if TARGET_LONG_BITS == 32
537fcf5ef2aSThomas Huth     if (sign_ext) {
538fcf5ef2aSThomas Huth         tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
539fcf5ef2aSThomas Huth     } else {
540fcf5ef2aSThomas Huth         tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
541fcf5ef2aSThomas Huth     }
542fcf5ef2aSThomas Huth #else
543fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new_i64();
544fcf5ef2aSThomas Huth     TCGv t1 = tcg_temp_new_i64();
545fcf5ef2aSThomas Huth 
546fcf5ef2aSThomas Huth     if (sign_ext) {
547fcf5ef2aSThomas Huth         tcg_gen_ext32s_i64(t0, src1);
548fcf5ef2aSThomas Huth         tcg_gen_ext32s_i64(t1, src2);
549fcf5ef2aSThomas Huth     } else {
550fcf5ef2aSThomas Huth         tcg_gen_ext32u_i64(t0, src1);
551fcf5ef2aSThomas Huth         tcg_gen_ext32u_i64(t1, src2);
552fcf5ef2aSThomas Huth     }
553fcf5ef2aSThomas Huth 
554fcf5ef2aSThomas Huth     tcg_gen_mul_i64(dst, t0, t1);
555fcf5ef2aSThomas Huth     tcg_gen_shri_i64(cpu_y, dst, 32);
556fcf5ef2aSThomas Huth #endif
557fcf5ef2aSThomas Huth }
558fcf5ef2aSThomas Huth 
5590c2e96c1SRichard Henderson static void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
560fcf5ef2aSThomas Huth {
561fcf5ef2aSThomas Huth     /* zero-extend truncated operands before multiplication */
562fcf5ef2aSThomas Huth     gen_op_multiply(dst, src1, src2, 0);
563fcf5ef2aSThomas Huth }
564fcf5ef2aSThomas Huth 
5650c2e96c1SRichard Henderson static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
566fcf5ef2aSThomas Huth {
567fcf5ef2aSThomas Huth     /* sign-extend truncated operands before multiplication */
568fcf5ef2aSThomas Huth     gen_op_multiply(dst, src1, src2, 1);
569fcf5ef2aSThomas Huth }
570fcf5ef2aSThomas Huth 
571c2636853SRichard Henderson static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
572c2636853SRichard Henderson {
57313260103SRichard Henderson #ifdef TARGET_SPARC64
574c2636853SRichard Henderson     gen_helper_sdiv(dst, tcg_env, src1, src2);
57513260103SRichard Henderson     tcg_gen_ext32s_tl(dst, dst);
57613260103SRichard Henderson #else
57713260103SRichard Henderson     TCGv_i64 t64 = tcg_temp_new_i64();
57813260103SRichard Henderson     gen_helper_sdiv(t64, tcg_env, src1, src2);
57913260103SRichard Henderson     tcg_gen_trunc_i64_tl(dst, t64);
58013260103SRichard Henderson #endif
581c2636853SRichard Henderson }
582c2636853SRichard Henderson 
583c2636853SRichard Henderson static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
584c2636853SRichard Henderson {
58513260103SRichard Henderson     TCGv_i64 t64;
58613260103SRichard Henderson 
58713260103SRichard Henderson #ifdef TARGET_SPARC64
58813260103SRichard Henderson     t64 = cpu_cc_V;
58913260103SRichard Henderson #else
59013260103SRichard Henderson     t64 = tcg_temp_new_i64();
59113260103SRichard Henderson #endif
59213260103SRichard Henderson 
59313260103SRichard Henderson     gen_helper_udiv(t64, tcg_env, src1, src2);
59413260103SRichard Henderson 
59513260103SRichard Henderson #ifdef TARGET_SPARC64
59613260103SRichard Henderson     tcg_gen_ext32u_tl(cpu_cc_N, t64);
59713260103SRichard Henderson     tcg_gen_shri_tl(cpu_cc_V, t64, 32);
59813260103SRichard Henderson     tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N);
59913260103SRichard Henderson     tcg_gen_movi_tl(cpu_icc_C, 0);
60013260103SRichard Henderson #else
60113260103SRichard Henderson     tcg_gen_extr_i64_tl(cpu_cc_N, cpu_cc_V, t64);
60213260103SRichard Henderson #endif
60313260103SRichard Henderson     tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
60413260103SRichard Henderson     tcg_gen_movi_tl(cpu_cc_C, 0);
60513260103SRichard Henderson     tcg_gen_mov_tl(dst, cpu_cc_N);
606c2636853SRichard Henderson }
607c2636853SRichard Henderson 
608c2636853SRichard Henderson static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
609c2636853SRichard Henderson {
61013260103SRichard Henderson     TCGv_i64 t64;
61113260103SRichard Henderson 
61213260103SRichard Henderson #ifdef TARGET_SPARC64
61313260103SRichard Henderson     t64 = cpu_cc_V;
61413260103SRichard Henderson #else
61513260103SRichard Henderson     t64 = tcg_temp_new_i64();
61613260103SRichard Henderson #endif
61713260103SRichard Henderson 
61813260103SRichard Henderson     gen_helper_sdiv(t64, tcg_env, src1, src2);
61913260103SRichard Henderson 
62013260103SRichard Henderson #ifdef TARGET_SPARC64
62113260103SRichard Henderson     tcg_gen_ext32s_tl(cpu_cc_N, t64);
62213260103SRichard Henderson     tcg_gen_shri_tl(cpu_cc_V, t64, 32);
62313260103SRichard Henderson     tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N);
62413260103SRichard Henderson     tcg_gen_movi_tl(cpu_icc_C, 0);
62513260103SRichard Henderson #else
62613260103SRichard Henderson     tcg_gen_extr_i64_tl(cpu_cc_N, cpu_cc_V, t64);
62713260103SRichard Henderson #endif
62813260103SRichard Henderson     tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
62913260103SRichard Henderson     tcg_gen_movi_tl(cpu_cc_C, 0);
63013260103SRichard Henderson     tcg_gen_mov_tl(dst, cpu_cc_N);
631c2636853SRichard Henderson }
632c2636853SRichard Henderson 
633a9aba13dSRichard Henderson static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2)
634a9aba13dSRichard Henderson {
635a9aba13dSRichard Henderson     gen_helper_taddcctv(dst, tcg_env, src1, src2);
636a9aba13dSRichard Henderson }
637a9aba13dSRichard Henderson 
638a9aba13dSRichard Henderson static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2)
639a9aba13dSRichard Henderson {
640a9aba13dSRichard Henderson     gen_helper_tsubcctv(dst, tcg_env, src1, src2);
641a9aba13dSRichard Henderson }
642a9aba13dSRichard Henderson 
6439c6ec5bcSRichard Henderson static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2)
6449c6ec5bcSRichard Henderson {
6459c6ec5bcSRichard Henderson     tcg_gen_ctpop_tl(dst, src2);
6469c6ec5bcSRichard Henderson }
6479c6ec5bcSRichard Henderson 
64845bfed3bSRichard Henderson #ifndef TARGET_SPARC64
64945bfed3bSRichard Henderson static void gen_helper_array8(TCGv dst, TCGv src1, TCGv src2)
65045bfed3bSRichard Henderson {
65145bfed3bSRichard Henderson     g_assert_not_reached();
65245bfed3bSRichard Henderson }
65345bfed3bSRichard Henderson #endif
65445bfed3bSRichard Henderson 
65545bfed3bSRichard Henderson static void gen_op_array16(TCGv dst, TCGv src1, TCGv src2)
65645bfed3bSRichard Henderson {
65745bfed3bSRichard Henderson     gen_helper_array8(dst, src1, src2);
65845bfed3bSRichard Henderson     tcg_gen_shli_tl(dst, dst, 1);
65945bfed3bSRichard Henderson }
66045bfed3bSRichard Henderson 
66145bfed3bSRichard Henderson static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2)
66245bfed3bSRichard Henderson {
66345bfed3bSRichard Henderson     gen_helper_array8(dst, src1, src2);
66445bfed3bSRichard Henderson     tcg_gen_shli_tl(dst, dst, 2);
66545bfed3bSRichard Henderson }
66645bfed3bSRichard Henderson 
6672f722641SRichard Henderson static void gen_op_fpack16(TCGv_i32 dst, TCGv_i64 src)
6682f722641SRichard Henderson {
6692f722641SRichard Henderson #ifdef TARGET_SPARC64
6702f722641SRichard Henderson     gen_helper_fpack16(dst, cpu_gsr, src);
6712f722641SRichard Henderson #else
6722f722641SRichard Henderson     g_assert_not_reached();
6732f722641SRichard Henderson #endif
6742f722641SRichard Henderson }
6752f722641SRichard Henderson 
6762f722641SRichard Henderson static void gen_op_fpackfix(TCGv_i32 dst, TCGv_i64 src)
6772f722641SRichard Henderson {
6782f722641SRichard Henderson #ifdef TARGET_SPARC64
6792f722641SRichard Henderson     gen_helper_fpackfix(dst, cpu_gsr, src);
6802f722641SRichard Henderson #else
6812f722641SRichard Henderson     g_assert_not_reached();
6822f722641SRichard Henderson #endif
6832f722641SRichard Henderson }
6842f722641SRichard Henderson 
6854b6edc0aSRichard Henderson static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
6864b6edc0aSRichard Henderson {
6874b6edc0aSRichard Henderson #ifdef TARGET_SPARC64
6884b6edc0aSRichard Henderson     gen_helper_fpack32(dst, cpu_gsr, src1, src2);
6894b6edc0aSRichard Henderson #else
6904b6edc0aSRichard Henderson     g_assert_not_reached();
6914b6edc0aSRichard Henderson #endif
6924b6edc0aSRichard Henderson }
6934b6edc0aSRichard Henderson 
6944b6edc0aSRichard Henderson static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2)
6954b6edc0aSRichard Henderson {
6964b6edc0aSRichard Henderson #ifdef TARGET_SPARC64
6974b6edc0aSRichard Henderson     TCGv t1, t2, shift;
6984b6edc0aSRichard Henderson 
6994b6edc0aSRichard Henderson     t1 = tcg_temp_new();
7004b6edc0aSRichard Henderson     t2 = tcg_temp_new();
7014b6edc0aSRichard Henderson     shift = tcg_temp_new();
7024b6edc0aSRichard Henderson 
7034b6edc0aSRichard Henderson     tcg_gen_andi_tl(shift, cpu_gsr, 7);
7044b6edc0aSRichard Henderson     tcg_gen_shli_tl(shift, shift, 3);
7054b6edc0aSRichard Henderson     tcg_gen_shl_tl(t1, s1, shift);
7064b6edc0aSRichard Henderson 
7074b6edc0aSRichard Henderson     /*
7084b6edc0aSRichard Henderson      * A shift of 64 does not produce 0 in TCG.  Divide this into a
7094b6edc0aSRichard Henderson      * shift of (up to 63) followed by a constant shift of 1.
7104b6edc0aSRichard Henderson      */
7114b6edc0aSRichard Henderson     tcg_gen_xori_tl(shift, shift, 63);
7124b6edc0aSRichard Henderson     tcg_gen_shr_tl(t2, s2, shift);
7134b6edc0aSRichard Henderson     tcg_gen_shri_tl(t2, t2, 1);
7144b6edc0aSRichard Henderson 
7154b6edc0aSRichard Henderson     tcg_gen_or_tl(dst, t1, t2);
7164b6edc0aSRichard Henderson #else
7174b6edc0aSRichard Henderson     g_assert_not_reached();
7184b6edc0aSRichard Henderson #endif
7194b6edc0aSRichard Henderson }
7204b6edc0aSRichard Henderson 
7214b6edc0aSRichard Henderson static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
7224b6edc0aSRichard Henderson {
7234b6edc0aSRichard Henderson #ifdef TARGET_SPARC64
7244b6edc0aSRichard Henderson     gen_helper_bshuffle(dst, cpu_gsr, src1, src2);
7254b6edc0aSRichard Henderson #else
7264b6edc0aSRichard Henderson     g_assert_not_reached();
7274b6edc0aSRichard Henderson #endif
7284b6edc0aSRichard Henderson }
7294b6edc0aSRichard Henderson 
730fcf5ef2aSThomas Huth // 1
7310c2e96c1SRichard Henderson static void gen_op_eval_ba(TCGv dst)
732fcf5ef2aSThomas Huth {
733fcf5ef2aSThomas Huth     tcg_gen_movi_tl(dst, 1);
734fcf5ef2aSThomas Huth }
735fcf5ef2aSThomas Huth 
736fcf5ef2aSThomas Huth // 0
7370c2e96c1SRichard Henderson static void gen_op_eval_bn(TCGv dst)
738fcf5ef2aSThomas Huth {
739fcf5ef2aSThomas Huth     tcg_gen_movi_tl(dst, 0);
740fcf5ef2aSThomas Huth }
741fcf5ef2aSThomas Huth 
742fcf5ef2aSThomas Huth /*
743fcf5ef2aSThomas Huth   FPSR bit field FCC1 | FCC0:
744fcf5ef2aSThomas Huth    0 =
745fcf5ef2aSThomas Huth    1 <
746fcf5ef2aSThomas Huth    2 >
747fcf5ef2aSThomas Huth    3 unordered
748fcf5ef2aSThomas Huth */
7490c2e96c1SRichard Henderson static void gen_mov_reg_FCC0(TCGv reg, TCGv src,
750fcf5ef2aSThomas Huth                                     unsigned int fcc_offset)
751fcf5ef2aSThomas Huth {
752fcf5ef2aSThomas Huth     tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
753fcf5ef2aSThomas Huth     tcg_gen_andi_tl(reg, reg, 0x1);
754fcf5ef2aSThomas Huth }
755fcf5ef2aSThomas Huth 
7560c2e96c1SRichard Henderson static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset)
757fcf5ef2aSThomas Huth {
758fcf5ef2aSThomas Huth     tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
759fcf5ef2aSThomas Huth     tcg_gen_andi_tl(reg, reg, 0x1);
760fcf5ef2aSThomas Huth }
761fcf5ef2aSThomas Huth 
762fcf5ef2aSThomas Huth // !0: FCC0 | FCC1
7630c2e96c1SRichard Henderson static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset)
764fcf5ef2aSThomas Huth {
765fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
766fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
767fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
768fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
769fcf5ef2aSThomas Huth }
770fcf5ef2aSThomas Huth 
771fcf5ef2aSThomas Huth // 1 or 2: FCC0 ^ FCC1
7720c2e96c1SRichard Henderson static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset)
773fcf5ef2aSThomas Huth {
774fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
775fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
776fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
777fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
778fcf5ef2aSThomas Huth }
779fcf5ef2aSThomas Huth 
780fcf5ef2aSThomas Huth // 1 or 3: FCC0
7810c2e96c1SRichard Henderson static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset)
782fcf5ef2aSThomas Huth {
783fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
784fcf5ef2aSThomas Huth }
785fcf5ef2aSThomas Huth 
786fcf5ef2aSThomas Huth // 1: FCC0 & !FCC1
7870c2e96c1SRichard Henderson static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset)
788fcf5ef2aSThomas Huth {
789fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
790fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
791fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
792fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, dst, t0);
793fcf5ef2aSThomas Huth }
794fcf5ef2aSThomas Huth 
795fcf5ef2aSThomas Huth // 2 or 3: FCC1
7960c2e96c1SRichard Henderson static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset)
797fcf5ef2aSThomas Huth {
798fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(dst, src, fcc_offset);
799fcf5ef2aSThomas Huth }
800fcf5ef2aSThomas Huth 
801fcf5ef2aSThomas Huth // 2: !FCC0 & FCC1
8020c2e96c1SRichard Henderson static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset)
803fcf5ef2aSThomas Huth {
804fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
805fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
806fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
807fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, t0, dst);
808fcf5ef2aSThomas Huth }
809fcf5ef2aSThomas Huth 
810fcf5ef2aSThomas Huth // 3: FCC0 & FCC1
8110c2e96c1SRichard Henderson static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset)
812fcf5ef2aSThomas Huth {
813fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
814fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
815fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
816fcf5ef2aSThomas Huth     tcg_gen_and_tl(dst, dst, t0);
817fcf5ef2aSThomas Huth }
818fcf5ef2aSThomas Huth 
819fcf5ef2aSThomas Huth // 0: !(FCC0 | FCC1)
8200c2e96c1SRichard Henderson static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset)
821fcf5ef2aSThomas Huth {
822fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
823fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
824fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
825fcf5ef2aSThomas Huth     tcg_gen_or_tl(dst, dst, t0);
826fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
827fcf5ef2aSThomas Huth }
828fcf5ef2aSThomas Huth 
829fcf5ef2aSThomas Huth // 0 or 3: !(FCC0 ^ FCC1)
8300c2e96c1SRichard Henderson static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset)
831fcf5ef2aSThomas Huth {
832fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
833fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
834fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
835fcf5ef2aSThomas Huth     tcg_gen_xor_tl(dst, dst, t0);
836fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
837fcf5ef2aSThomas Huth }
838fcf5ef2aSThomas Huth 
839fcf5ef2aSThomas Huth // 0 or 2: !FCC0
8400c2e96c1SRichard Henderson static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset)
841fcf5ef2aSThomas Huth {
842fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
843fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
844fcf5ef2aSThomas Huth }
845fcf5ef2aSThomas Huth 
846fcf5ef2aSThomas Huth // !1: !(FCC0 & !FCC1)
8470c2e96c1SRichard Henderson static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset)
848fcf5ef2aSThomas Huth {
849fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
850fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
851fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
852fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, dst, t0);
853fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
854fcf5ef2aSThomas Huth }
855fcf5ef2aSThomas Huth 
856fcf5ef2aSThomas Huth // 0 or 1: !FCC1
8570c2e96c1SRichard Henderson static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset)
858fcf5ef2aSThomas Huth {
859fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(dst, src, fcc_offset);
860fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
861fcf5ef2aSThomas Huth }
862fcf5ef2aSThomas Huth 
863fcf5ef2aSThomas Huth // !2: !(!FCC0 & FCC1)
8640c2e96c1SRichard Henderson static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset)
865fcf5ef2aSThomas Huth {
866fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
867fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
868fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
869fcf5ef2aSThomas Huth     tcg_gen_andc_tl(dst, t0, dst);
870fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
871fcf5ef2aSThomas Huth }
872fcf5ef2aSThomas Huth 
873fcf5ef2aSThomas Huth // !3: !(FCC0 & FCC1)
8740c2e96c1SRichard Henderson static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset)
875fcf5ef2aSThomas Huth {
876fcf5ef2aSThomas Huth     TCGv t0 = tcg_temp_new();
877fcf5ef2aSThomas Huth     gen_mov_reg_FCC0(dst, src, fcc_offset);
878fcf5ef2aSThomas Huth     gen_mov_reg_FCC1(t0, src, fcc_offset);
879fcf5ef2aSThomas Huth     tcg_gen_and_tl(dst, dst, t0);
880fcf5ef2aSThomas Huth     tcg_gen_xori_tl(dst, dst, 0x1);
881fcf5ef2aSThomas Huth }
882fcf5ef2aSThomas Huth 
88389527e3aSRichard Henderson static void finishing_insn(DisasContext *dc)
88489527e3aSRichard Henderson {
88589527e3aSRichard Henderson     /*
88689527e3aSRichard Henderson      * From here, there is no future path through an unwinding exception.
88789527e3aSRichard Henderson      * If the current insn cannot raise an exception, the computation of
88889527e3aSRichard Henderson      * cpu_cond may be able to be elided.
88989527e3aSRichard Henderson      */
89089527e3aSRichard Henderson     if (dc->cpu_cond_live) {
89189527e3aSRichard Henderson         tcg_gen_discard_tl(cpu_cond);
89289527e3aSRichard Henderson         dc->cpu_cond_live = false;
89389527e3aSRichard Henderson     }
89489527e3aSRichard Henderson }
89589527e3aSRichard Henderson 
8960c2e96c1SRichard Henderson static void gen_generic_branch(DisasContext *dc)
897fcf5ef2aSThomas Huth {
89800ab7e61SRichard Henderson     TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
89900ab7e61SRichard Henderson     TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]);
900533f042fSRichard Henderson     TCGv c2 = tcg_constant_tl(dc->jump.c2);
901fcf5ef2aSThomas Huth 
902533f042fSRichard Henderson     tcg_gen_movcond_tl(dc->jump.cond, cpu_npc, dc->jump.c1, c2, npc0, npc1);
903fcf5ef2aSThomas Huth }
904fcf5ef2aSThomas Huth 
905fcf5ef2aSThomas Huth /* call this function before using the condition register as it may
906fcf5ef2aSThomas Huth    have been set for a jump */
9070c2e96c1SRichard Henderson static void flush_cond(DisasContext *dc)
908fcf5ef2aSThomas Huth {
909fcf5ef2aSThomas Huth     if (dc->npc == JUMP_PC) {
910fcf5ef2aSThomas Huth         gen_generic_branch(dc);
91199c82c47SRichard Henderson         dc->npc = DYNAMIC_PC_LOOKUP;
912fcf5ef2aSThomas Huth     }
913fcf5ef2aSThomas Huth }
914fcf5ef2aSThomas Huth 
9150c2e96c1SRichard Henderson static void save_npc(DisasContext *dc)
916fcf5ef2aSThomas Huth {
917633c4283SRichard Henderson     if (dc->npc & 3) {
918633c4283SRichard Henderson         switch (dc->npc) {
919633c4283SRichard Henderson         case JUMP_PC:
920fcf5ef2aSThomas Huth             gen_generic_branch(dc);
92199c82c47SRichard Henderson             dc->npc = DYNAMIC_PC_LOOKUP;
922633c4283SRichard Henderson             break;
923633c4283SRichard Henderson         case DYNAMIC_PC:
924633c4283SRichard Henderson         case DYNAMIC_PC_LOOKUP:
925633c4283SRichard Henderson             break;
926633c4283SRichard Henderson         default:
927633c4283SRichard Henderson             g_assert_not_reached();
928633c4283SRichard Henderson         }
929633c4283SRichard Henderson     } else {
930fcf5ef2aSThomas Huth         tcg_gen_movi_tl(cpu_npc, dc->npc);
931fcf5ef2aSThomas Huth     }
932fcf5ef2aSThomas Huth }
933fcf5ef2aSThomas Huth 
9340c2e96c1SRichard Henderson static void save_state(DisasContext *dc)
935fcf5ef2aSThomas Huth {
936fcf5ef2aSThomas Huth     tcg_gen_movi_tl(cpu_pc, dc->pc);
937fcf5ef2aSThomas Huth     save_npc(dc);
938fcf5ef2aSThomas Huth }
939fcf5ef2aSThomas Huth 
940fcf5ef2aSThomas Huth static void gen_exception(DisasContext *dc, int which)
941fcf5ef2aSThomas Huth {
94289527e3aSRichard Henderson     finishing_insn(dc);
943fcf5ef2aSThomas Huth     save_state(dc);
944ad75a51eSRichard Henderson     gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
945af00be49SEmilio G. Cota     dc->base.is_jmp = DISAS_NORETURN;
946fcf5ef2aSThomas Huth }
947fcf5ef2aSThomas Huth 
948186e7890SRichard Henderson static TCGLabel *delay_exceptionv(DisasContext *dc, TCGv_i32 excp)
949fcf5ef2aSThomas Huth {
950186e7890SRichard Henderson     DisasDelayException *e = g_new0(DisasDelayException, 1);
951186e7890SRichard Henderson 
952186e7890SRichard Henderson     e->next = dc->delay_excp_list;
953186e7890SRichard Henderson     dc->delay_excp_list = e;
954186e7890SRichard Henderson 
955186e7890SRichard Henderson     e->lab = gen_new_label();
956186e7890SRichard Henderson     e->excp = excp;
957186e7890SRichard Henderson     e->pc = dc->pc;
958186e7890SRichard Henderson     /* Caller must have used flush_cond before branch. */
959186e7890SRichard Henderson     assert(e->npc != JUMP_PC);
960186e7890SRichard Henderson     e->npc = dc->npc;
961186e7890SRichard Henderson 
962186e7890SRichard Henderson     return e->lab;
963186e7890SRichard Henderson }
964186e7890SRichard Henderson 
965186e7890SRichard Henderson static TCGLabel *delay_exception(DisasContext *dc, int excp)
966186e7890SRichard Henderson {
967186e7890SRichard Henderson     return delay_exceptionv(dc, tcg_constant_i32(excp));
968186e7890SRichard Henderson }
969186e7890SRichard Henderson 
970186e7890SRichard Henderson static void gen_check_align(DisasContext *dc, TCGv addr, int mask)
971186e7890SRichard Henderson {
972186e7890SRichard Henderson     TCGv t = tcg_temp_new();
973186e7890SRichard Henderson     TCGLabel *lab;
974186e7890SRichard Henderson 
975186e7890SRichard Henderson     tcg_gen_andi_tl(t, addr, mask);
976186e7890SRichard Henderson 
977186e7890SRichard Henderson     flush_cond(dc);
978186e7890SRichard Henderson     lab = delay_exception(dc, TT_UNALIGNED);
979186e7890SRichard Henderson     tcg_gen_brcondi_tl(TCG_COND_NE, t, 0, lab);
980fcf5ef2aSThomas Huth }
981fcf5ef2aSThomas Huth 
9820c2e96c1SRichard Henderson static void gen_mov_pc_npc(DisasContext *dc)
983fcf5ef2aSThomas Huth {
98489527e3aSRichard Henderson     finishing_insn(dc);
98589527e3aSRichard Henderson 
986633c4283SRichard Henderson     if (dc->npc & 3) {
987633c4283SRichard Henderson         switch (dc->npc) {
988633c4283SRichard Henderson         case JUMP_PC:
989fcf5ef2aSThomas Huth             gen_generic_branch(dc);
990fcf5ef2aSThomas Huth             tcg_gen_mov_tl(cpu_pc, cpu_npc);
99199c82c47SRichard Henderson             dc->pc = DYNAMIC_PC_LOOKUP;
992633c4283SRichard Henderson             break;
993633c4283SRichard Henderson         case DYNAMIC_PC:
994633c4283SRichard Henderson         case DYNAMIC_PC_LOOKUP:
995fcf5ef2aSThomas Huth             tcg_gen_mov_tl(cpu_pc, cpu_npc);
996633c4283SRichard Henderson             dc->pc = dc->npc;
997633c4283SRichard Henderson             break;
998633c4283SRichard Henderson         default:
999633c4283SRichard Henderson             g_assert_not_reached();
1000633c4283SRichard Henderson         }
1001fcf5ef2aSThomas Huth     } else {
1002fcf5ef2aSThomas Huth         dc->pc = dc->npc;
1003fcf5ef2aSThomas Huth     }
1004fcf5ef2aSThomas Huth }
1005fcf5ef2aSThomas Huth 
1006fcf5ef2aSThomas Huth static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
1007fcf5ef2aSThomas Huth                         DisasContext *dc)
1008fcf5ef2aSThomas Huth {
1009b597eedcSRichard Henderson     TCGv t1;
1010fcf5ef2aSThomas Huth 
10112a1905c7SRichard Henderson     cmp->c1 = t1 = tcg_temp_new();
1012c8507ebfSRichard Henderson     cmp->c2 = 0;
10132a1905c7SRichard Henderson 
10142a1905c7SRichard Henderson     switch (cond & 7) {
10152a1905c7SRichard Henderson     case 0x0: /* never */
10162a1905c7SRichard Henderson         cmp->cond = TCG_COND_NEVER;
1017c8507ebfSRichard Henderson         cmp->c1 = tcg_constant_tl(0);
1018fcf5ef2aSThomas Huth         break;
10192a1905c7SRichard Henderson 
10202a1905c7SRichard Henderson     case 0x1: /* eq: Z */
10212a1905c7SRichard Henderson         cmp->cond = TCG_COND_EQ;
10222a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 32 || xcc) {
10232a1905c7SRichard Henderson             tcg_gen_mov_tl(t1, cpu_cc_Z);
10242a1905c7SRichard Henderson         } else {
10252a1905c7SRichard Henderson             tcg_gen_ext32u_tl(t1, cpu_icc_Z);
10262a1905c7SRichard Henderson         }
10272a1905c7SRichard Henderson         break;
10282a1905c7SRichard Henderson 
10292a1905c7SRichard Henderson     case 0x2: /* le: Z | (N ^ V) */
10302a1905c7SRichard Henderson         /*
10312a1905c7SRichard Henderson          * Simplify:
10322a1905c7SRichard Henderson          *   cc_Z || (N ^ V) < 0        NE
10332a1905c7SRichard Henderson          *   cc_Z && !((N ^ V) < 0)     EQ
10342a1905c7SRichard Henderson          *   cc_Z & ~((N ^ V) >> TLB)   EQ
10352a1905c7SRichard Henderson          */
10362a1905c7SRichard Henderson         cmp->cond = TCG_COND_EQ;
10372a1905c7SRichard Henderson         tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V);
10382a1905c7SRichard Henderson         tcg_gen_sextract_tl(t1, t1, xcc ? 63 : 31, 1);
10392a1905c7SRichard Henderson         tcg_gen_andc_tl(t1, xcc ? cpu_cc_Z : cpu_icc_Z, t1);
10402a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 64 && !xcc) {
10412a1905c7SRichard Henderson             tcg_gen_ext32u_tl(t1, t1);
10422a1905c7SRichard Henderson         }
10432a1905c7SRichard Henderson         break;
10442a1905c7SRichard Henderson 
10452a1905c7SRichard Henderson     case 0x3: /* lt: N ^ V */
10462a1905c7SRichard Henderson         cmp->cond = TCG_COND_LT;
10472a1905c7SRichard Henderson         tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V);
10482a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 64 && !xcc) {
10492a1905c7SRichard Henderson             tcg_gen_ext32s_tl(t1, t1);
10502a1905c7SRichard Henderson         }
10512a1905c7SRichard Henderson         break;
10522a1905c7SRichard Henderson 
10532a1905c7SRichard Henderson     case 0x4: /* leu: Z | C */
10542a1905c7SRichard Henderson         /*
10552a1905c7SRichard Henderson          * Simplify:
10562a1905c7SRichard Henderson          *   cc_Z == 0 || cc_C != 0     NE
10572a1905c7SRichard Henderson          *   cc_Z != 0 && cc_C == 0     EQ
10582a1905c7SRichard Henderson          *   cc_Z & (cc_C ? 0 : -1)     EQ
10592a1905c7SRichard Henderson          *   cc_Z & (cc_C - 1)          EQ
10602a1905c7SRichard Henderson          */
10612a1905c7SRichard Henderson         cmp->cond = TCG_COND_EQ;
10622a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 32 || xcc) {
10632a1905c7SRichard Henderson             tcg_gen_subi_tl(t1, cpu_cc_C, 1);
10642a1905c7SRichard Henderson             tcg_gen_and_tl(t1, t1, cpu_cc_Z);
10652a1905c7SRichard Henderson         } else {
10662a1905c7SRichard Henderson             tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1);
10672a1905c7SRichard Henderson             tcg_gen_subi_tl(t1, t1, 1);
10682a1905c7SRichard Henderson             tcg_gen_and_tl(t1, t1, cpu_icc_Z);
10692a1905c7SRichard Henderson             tcg_gen_ext32u_tl(t1, t1);
10702a1905c7SRichard Henderson         }
10712a1905c7SRichard Henderson         break;
10722a1905c7SRichard Henderson 
10732a1905c7SRichard Henderson     case 0x5: /* ltu: C */
10742a1905c7SRichard Henderson         cmp->cond = TCG_COND_NE;
10752a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 32 || xcc) {
10762a1905c7SRichard Henderson             tcg_gen_mov_tl(t1, cpu_cc_C);
10772a1905c7SRichard Henderson         } else {
10782a1905c7SRichard Henderson             tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1);
10792a1905c7SRichard Henderson         }
10802a1905c7SRichard Henderson         break;
10812a1905c7SRichard Henderson 
10822a1905c7SRichard Henderson     case 0x6: /* neg: N */
10832a1905c7SRichard Henderson         cmp->cond = TCG_COND_LT;
10842a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 32 || xcc) {
10852a1905c7SRichard Henderson             tcg_gen_mov_tl(t1, cpu_cc_N);
10862a1905c7SRichard Henderson         } else {
10872a1905c7SRichard Henderson             tcg_gen_ext32s_tl(t1, cpu_cc_N);
10882a1905c7SRichard Henderson         }
10892a1905c7SRichard Henderson         break;
10902a1905c7SRichard Henderson 
10912a1905c7SRichard Henderson     case 0x7: /* vs: V */
10922a1905c7SRichard Henderson         cmp->cond = TCG_COND_LT;
10932a1905c7SRichard Henderson         if (TARGET_LONG_BITS == 32 || xcc) {
10942a1905c7SRichard Henderson             tcg_gen_mov_tl(t1, cpu_cc_V);
10952a1905c7SRichard Henderson         } else {
10962a1905c7SRichard Henderson             tcg_gen_ext32s_tl(t1, cpu_cc_V);
10972a1905c7SRichard Henderson         }
10982a1905c7SRichard Henderson         break;
10992a1905c7SRichard Henderson     }
11002a1905c7SRichard Henderson     if (cond & 8) {
11012a1905c7SRichard Henderson         cmp->cond = tcg_invert_cond(cmp->cond);
1102fcf5ef2aSThomas Huth     }
1103fcf5ef2aSThomas Huth }
1104fcf5ef2aSThomas Huth 
1105fcf5ef2aSThomas Huth static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
1106fcf5ef2aSThomas Huth {
1107fcf5ef2aSThomas Huth     unsigned int offset;
1108fcf5ef2aSThomas Huth     TCGv r_dst;
1109fcf5ef2aSThomas Huth 
1110fcf5ef2aSThomas Huth     /* For now we still generate a straight boolean result.  */
1111fcf5ef2aSThomas Huth     cmp->cond = TCG_COND_NE;
1112fcf5ef2aSThomas Huth     cmp->c1 = r_dst = tcg_temp_new();
1113c8507ebfSRichard Henderson     cmp->c2 = 0;
1114fcf5ef2aSThomas Huth 
1115fcf5ef2aSThomas Huth     switch (cc) {
1116fcf5ef2aSThomas Huth     default:
1117fcf5ef2aSThomas Huth     case 0x0:
1118fcf5ef2aSThomas Huth         offset = 0;
1119fcf5ef2aSThomas Huth         break;
1120fcf5ef2aSThomas Huth     case 0x1:
1121fcf5ef2aSThomas Huth         offset = 32 - 10;
1122fcf5ef2aSThomas Huth         break;
1123fcf5ef2aSThomas Huth     case 0x2:
1124fcf5ef2aSThomas Huth         offset = 34 - 10;
1125fcf5ef2aSThomas Huth         break;
1126fcf5ef2aSThomas Huth     case 0x3:
1127fcf5ef2aSThomas Huth         offset = 36 - 10;
1128fcf5ef2aSThomas Huth         break;
1129fcf5ef2aSThomas Huth     }
1130fcf5ef2aSThomas Huth 
1131fcf5ef2aSThomas Huth     switch (cond) {
1132fcf5ef2aSThomas Huth     case 0x0:
1133fcf5ef2aSThomas Huth         gen_op_eval_bn(r_dst);
1134fcf5ef2aSThomas Huth         break;
1135fcf5ef2aSThomas Huth     case 0x1:
1136fcf5ef2aSThomas Huth         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1137fcf5ef2aSThomas Huth         break;
1138fcf5ef2aSThomas Huth     case 0x2:
1139fcf5ef2aSThomas Huth         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1140fcf5ef2aSThomas Huth         break;
1141fcf5ef2aSThomas Huth     case 0x3:
1142fcf5ef2aSThomas Huth         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1143fcf5ef2aSThomas Huth         break;
1144fcf5ef2aSThomas Huth     case 0x4:
1145fcf5ef2aSThomas Huth         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1146fcf5ef2aSThomas Huth         break;
1147fcf5ef2aSThomas Huth     case 0x5:
1148fcf5ef2aSThomas Huth         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1149fcf5ef2aSThomas Huth         break;
1150fcf5ef2aSThomas Huth     case 0x6:
1151fcf5ef2aSThomas Huth         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1152fcf5ef2aSThomas Huth         break;
1153fcf5ef2aSThomas Huth     case 0x7:
1154fcf5ef2aSThomas Huth         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1155fcf5ef2aSThomas Huth         break;
1156fcf5ef2aSThomas Huth     case 0x8:
1157fcf5ef2aSThomas Huth         gen_op_eval_ba(r_dst);
1158fcf5ef2aSThomas Huth         break;
1159fcf5ef2aSThomas Huth     case 0x9:
1160fcf5ef2aSThomas Huth         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1161fcf5ef2aSThomas Huth         break;
1162fcf5ef2aSThomas Huth     case 0xa:
1163fcf5ef2aSThomas Huth         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1164fcf5ef2aSThomas Huth         break;
1165fcf5ef2aSThomas Huth     case 0xb:
1166fcf5ef2aSThomas Huth         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1167fcf5ef2aSThomas Huth         break;
1168fcf5ef2aSThomas Huth     case 0xc:
1169fcf5ef2aSThomas Huth         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1170fcf5ef2aSThomas Huth         break;
1171fcf5ef2aSThomas Huth     case 0xd:
1172fcf5ef2aSThomas Huth         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1173fcf5ef2aSThomas Huth         break;
1174fcf5ef2aSThomas Huth     case 0xe:
1175fcf5ef2aSThomas Huth         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1176fcf5ef2aSThomas Huth         break;
1177fcf5ef2aSThomas Huth     case 0xf:
1178fcf5ef2aSThomas Huth         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1179fcf5ef2aSThomas Huth         break;
1180fcf5ef2aSThomas Huth     }
1181fcf5ef2aSThomas Huth }
1182fcf5ef2aSThomas Huth 
11832c4f56c9SRichard Henderson static bool gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
11842c4f56c9SRichard Henderson {
11852c4f56c9SRichard Henderson     static const TCGCond cond_reg[4] = {
1186ab9ffe98SRichard Henderson         TCG_COND_NEVER,  /* reserved */
1187fcf5ef2aSThomas Huth         TCG_COND_EQ,
1188fcf5ef2aSThomas Huth         TCG_COND_LE,
1189fcf5ef2aSThomas Huth         TCG_COND_LT,
1190fcf5ef2aSThomas Huth     };
11912c4f56c9SRichard Henderson     TCGCond tcond;
1192fcf5ef2aSThomas Huth 
11932c4f56c9SRichard Henderson     if ((cond & 3) == 0) {
11942c4f56c9SRichard Henderson         return false;
11952c4f56c9SRichard Henderson     }
11962c4f56c9SRichard Henderson     tcond = cond_reg[cond & 3];
11972c4f56c9SRichard Henderson     if (cond & 4) {
11982c4f56c9SRichard Henderson         tcond = tcg_invert_cond(tcond);
11992c4f56c9SRichard Henderson     }
12002c4f56c9SRichard Henderson 
12012c4f56c9SRichard Henderson     cmp->cond = tcond;
1202816f89b7SRichard Henderson     cmp->c1 = tcg_temp_new();
1203c8507ebfSRichard Henderson     cmp->c2 = 0;
1204816f89b7SRichard Henderson     tcg_gen_mov_tl(cmp->c1, r_src);
12052c4f56c9SRichard Henderson     return true;
1206fcf5ef2aSThomas Huth }
1207fcf5ef2aSThomas Huth 
1208baf3dbf2SRichard Henderson static void gen_op_clear_ieee_excp_and_FTT(void)
1209baf3dbf2SRichard Henderson {
1210baf3dbf2SRichard Henderson     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1211baf3dbf2SRichard Henderson }
1212baf3dbf2SRichard Henderson 
1213baf3dbf2SRichard Henderson static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src)
1214baf3dbf2SRichard Henderson {
1215baf3dbf2SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1216baf3dbf2SRichard Henderson     tcg_gen_mov_i32(dst, src);
1217baf3dbf2SRichard Henderson }
1218baf3dbf2SRichard Henderson 
1219baf3dbf2SRichard Henderson static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src)
1220baf3dbf2SRichard Henderson {
1221baf3dbf2SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1222daf457d4SRichard Henderson     tcg_gen_xori_i32(dst, src, 1u << 31);
1223baf3dbf2SRichard Henderson }
1224baf3dbf2SRichard Henderson 
1225baf3dbf2SRichard Henderson static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src)
1226baf3dbf2SRichard Henderson {
1227baf3dbf2SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1228daf457d4SRichard Henderson     tcg_gen_andi_i32(dst, src, ~(1u << 31));
1229baf3dbf2SRichard Henderson }
1230baf3dbf2SRichard Henderson 
1231c6d83e4fSRichard Henderson static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src)
1232c6d83e4fSRichard Henderson {
1233c6d83e4fSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1234c6d83e4fSRichard Henderson     tcg_gen_mov_i64(dst, src);
1235c6d83e4fSRichard Henderson }
1236c6d83e4fSRichard Henderson 
1237c6d83e4fSRichard Henderson static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src)
1238c6d83e4fSRichard Henderson {
1239c6d83e4fSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1240daf457d4SRichard Henderson     tcg_gen_xori_i64(dst, src, 1ull << 63);
1241c6d83e4fSRichard Henderson }
1242c6d83e4fSRichard Henderson 
1243c6d83e4fSRichard Henderson static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src)
1244c6d83e4fSRichard Henderson {
1245c6d83e4fSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
1246daf457d4SRichard Henderson     tcg_gen_andi_i64(dst, src, ~(1ull << 63));
1247daf457d4SRichard Henderson }
1248daf457d4SRichard Henderson 
1249daf457d4SRichard Henderson static void gen_op_fnegq(TCGv_i128 dst, TCGv_i128 src)
1250daf457d4SRichard Henderson {
1251daf457d4SRichard Henderson     TCGv_i64 l = tcg_temp_new_i64();
1252daf457d4SRichard Henderson     TCGv_i64 h = tcg_temp_new_i64();
1253daf457d4SRichard Henderson 
1254daf457d4SRichard Henderson     tcg_gen_extr_i128_i64(l, h, src);
1255daf457d4SRichard Henderson     tcg_gen_xori_i64(h, h, 1ull << 63);
1256daf457d4SRichard Henderson     tcg_gen_concat_i64_i128(dst, l, h);
1257daf457d4SRichard Henderson }
1258daf457d4SRichard Henderson 
1259daf457d4SRichard Henderson static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src)
1260daf457d4SRichard Henderson {
1261daf457d4SRichard Henderson     TCGv_i64 l = tcg_temp_new_i64();
1262daf457d4SRichard Henderson     TCGv_i64 h = tcg_temp_new_i64();
1263daf457d4SRichard Henderson 
1264daf457d4SRichard Henderson     tcg_gen_extr_i128_i64(l, h, src);
1265daf457d4SRichard Henderson     tcg_gen_andi_i64(h, h, ~(1ull << 63));
1266daf457d4SRichard Henderson     tcg_gen_concat_i64_i128(dst, l, h);
1267c6d83e4fSRichard Henderson }
1268c6d83e4fSRichard Henderson 
1269fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
12700c2e96c1SRichard Henderson static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1271fcf5ef2aSThomas Huth {
1272fcf5ef2aSThomas Huth     switch (fccno) {
1273fcf5ef2aSThomas Huth     case 0:
1274ad75a51eSRichard Henderson         gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
1275fcf5ef2aSThomas Huth         break;
1276fcf5ef2aSThomas Huth     case 1:
1277ad75a51eSRichard Henderson         gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1278fcf5ef2aSThomas Huth         break;
1279fcf5ef2aSThomas Huth     case 2:
1280ad75a51eSRichard Henderson         gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1281fcf5ef2aSThomas Huth         break;
1282fcf5ef2aSThomas Huth     case 3:
1283ad75a51eSRichard Henderson         gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1284fcf5ef2aSThomas Huth         break;
1285fcf5ef2aSThomas Huth     }
1286fcf5ef2aSThomas Huth }
1287fcf5ef2aSThomas Huth 
12880c2e96c1SRichard Henderson static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1289fcf5ef2aSThomas Huth {
1290fcf5ef2aSThomas Huth     switch (fccno) {
1291fcf5ef2aSThomas Huth     case 0:
1292ad75a51eSRichard Henderson         gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
1293fcf5ef2aSThomas Huth         break;
1294fcf5ef2aSThomas Huth     case 1:
1295ad75a51eSRichard Henderson         gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1296fcf5ef2aSThomas Huth         break;
1297fcf5ef2aSThomas Huth     case 2:
1298ad75a51eSRichard Henderson         gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1299fcf5ef2aSThomas Huth         break;
1300fcf5ef2aSThomas Huth     case 3:
1301ad75a51eSRichard Henderson         gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1302fcf5ef2aSThomas Huth         break;
1303fcf5ef2aSThomas Huth     }
1304fcf5ef2aSThomas Huth }
1305fcf5ef2aSThomas Huth 
1306f3ceafadSRichard Henderson static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
1307fcf5ef2aSThomas Huth {
1308fcf5ef2aSThomas Huth     switch (fccno) {
1309fcf5ef2aSThomas Huth     case 0:
1310f3ceafadSRichard Henderson         gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2);
1311fcf5ef2aSThomas Huth         break;
1312fcf5ef2aSThomas Huth     case 1:
1313f3ceafadSRichard Henderson         gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1314fcf5ef2aSThomas Huth         break;
1315fcf5ef2aSThomas Huth     case 2:
1316f3ceafadSRichard Henderson         gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1317fcf5ef2aSThomas Huth         break;
1318fcf5ef2aSThomas Huth     case 3:
1319f3ceafadSRichard Henderson         gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1320fcf5ef2aSThomas Huth         break;
1321fcf5ef2aSThomas Huth     }
1322fcf5ef2aSThomas Huth }
1323fcf5ef2aSThomas Huth 
13240c2e96c1SRichard Henderson static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1325fcf5ef2aSThomas Huth {
1326fcf5ef2aSThomas Huth     switch (fccno) {
1327fcf5ef2aSThomas Huth     case 0:
1328ad75a51eSRichard Henderson         gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
1329fcf5ef2aSThomas Huth         break;
1330fcf5ef2aSThomas Huth     case 1:
1331ad75a51eSRichard Henderson         gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1332fcf5ef2aSThomas Huth         break;
1333fcf5ef2aSThomas Huth     case 2:
1334ad75a51eSRichard Henderson         gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1335fcf5ef2aSThomas Huth         break;
1336fcf5ef2aSThomas Huth     case 3:
1337ad75a51eSRichard Henderson         gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1338fcf5ef2aSThomas Huth         break;
1339fcf5ef2aSThomas Huth     }
1340fcf5ef2aSThomas Huth }
1341fcf5ef2aSThomas Huth 
13420c2e96c1SRichard Henderson static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1343fcf5ef2aSThomas Huth {
1344fcf5ef2aSThomas Huth     switch (fccno) {
1345fcf5ef2aSThomas Huth     case 0:
1346ad75a51eSRichard Henderson         gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
1347fcf5ef2aSThomas Huth         break;
1348fcf5ef2aSThomas Huth     case 1:
1349ad75a51eSRichard Henderson         gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1350fcf5ef2aSThomas Huth         break;
1351fcf5ef2aSThomas Huth     case 2:
1352ad75a51eSRichard Henderson         gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1353fcf5ef2aSThomas Huth         break;
1354fcf5ef2aSThomas Huth     case 3:
1355ad75a51eSRichard Henderson         gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1356fcf5ef2aSThomas Huth         break;
1357fcf5ef2aSThomas Huth     }
1358fcf5ef2aSThomas Huth }
1359fcf5ef2aSThomas Huth 
1360f3ceafadSRichard Henderson static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
1361fcf5ef2aSThomas Huth {
1362fcf5ef2aSThomas Huth     switch (fccno) {
1363fcf5ef2aSThomas Huth     case 0:
1364f3ceafadSRichard Henderson         gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2);
1365fcf5ef2aSThomas Huth         break;
1366fcf5ef2aSThomas Huth     case 1:
1367f3ceafadSRichard Henderson         gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
1368fcf5ef2aSThomas Huth         break;
1369fcf5ef2aSThomas Huth     case 2:
1370f3ceafadSRichard Henderson         gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
1371fcf5ef2aSThomas Huth         break;
1372fcf5ef2aSThomas Huth     case 3:
1373f3ceafadSRichard Henderson         gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
1374fcf5ef2aSThomas Huth         break;
1375fcf5ef2aSThomas Huth     }
1376fcf5ef2aSThomas Huth }
1377fcf5ef2aSThomas Huth 
1378fcf5ef2aSThomas Huth #else
1379fcf5ef2aSThomas Huth 
13800c2e96c1SRichard Henderson static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1381fcf5ef2aSThomas Huth {
1382ad75a51eSRichard Henderson     gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
1383fcf5ef2aSThomas Huth }
1384fcf5ef2aSThomas Huth 
13850c2e96c1SRichard Henderson static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1386fcf5ef2aSThomas Huth {
1387ad75a51eSRichard Henderson     gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
1388fcf5ef2aSThomas Huth }
1389fcf5ef2aSThomas Huth 
1390f3ceafadSRichard Henderson static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
1391fcf5ef2aSThomas Huth {
1392f3ceafadSRichard Henderson     gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2);
1393fcf5ef2aSThomas Huth }
1394fcf5ef2aSThomas Huth 
13950c2e96c1SRichard Henderson static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1396fcf5ef2aSThomas Huth {
1397ad75a51eSRichard Henderson     gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
1398fcf5ef2aSThomas Huth }
1399fcf5ef2aSThomas Huth 
14000c2e96c1SRichard Henderson static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1401fcf5ef2aSThomas Huth {
1402ad75a51eSRichard Henderson     gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
1403fcf5ef2aSThomas Huth }
1404fcf5ef2aSThomas Huth 
1405f3ceafadSRichard Henderson static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
1406fcf5ef2aSThomas Huth {
1407f3ceafadSRichard Henderson     gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2);
1408fcf5ef2aSThomas Huth }
1409fcf5ef2aSThomas Huth #endif
1410fcf5ef2aSThomas Huth 
1411fcf5ef2aSThomas Huth static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
1412fcf5ef2aSThomas Huth {
1413fcf5ef2aSThomas Huth     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1414fcf5ef2aSThomas Huth     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1415fcf5ef2aSThomas Huth     gen_exception(dc, TT_FP_EXCP);
1416fcf5ef2aSThomas Huth }
1417fcf5ef2aSThomas Huth 
1418fcf5ef2aSThomas Huth static int gen_trap_ifnofpu(DisasContext *dc)
1419fcf5ef2aSThomas Huth {
1420fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY)
1421fcf5ef2aSThomas Huth     if (!dc->fpu_enabled) {
1422fcf5ef2aSThomas Huth         gen_exception(dc, TT_NFPU_INSN);
1423fcf5ef2aSThomas Huth         return 1;
1424fcf5ef2aSThomas Huth     }
1425fcf5ef2aSThomas Huth #endif
1426fcf5ef2aSThomas Huth     return 0;
1427fcf5ef2aSThomas Huth }
1428fcf5ef2aSThomas Huth 
1429fcf5ef2aSThomas Huth /* asi moves */
1430fcf5ef2aSThomas Huth typedef enum {
1431fcf5ef2aSThomas Huth     GET_ASI_HELPER,
1432fcf5ef2aSThomas Huth     GET_ASI_EXCP,
1433fcf5ef2aSThomas Huth     GET_ASI_DIRECT,
1434fcf5ef2aSThomas Huth     GET_ASI_DTWINX,
1435fcf5ef2aSThomas Huth     GET_ASI_BLOCK,
1436fcf5ef2aSThomas Huth     GET_ASI_SHORT,
1437fcf5ef2aSThomas Huth     GET_ASI_BCOPY,
1438fcf5ef2aSThomas Huth     GET_ASI_BFILL,
1439fcf5ef2aSThomas Huth } ASIType;
1440fcf5ef2aSThomas Huth 
1441fcf5ef2aSThomas Huth typedef struct {
1442fcf5ef2aSThomas Huth     ASIType type;
1443fcf5ef2aSThomas Huth     int asi;
1444fcf5ef2aSThomas Huth     int mem_idx;
144514776ab5STony Nguyen     MemOp memop;
1446fcf5ef2aSThomas Huth } DisasASI;
1447fcf5ef2aSThomas Huth 
1448811cc0b0SRichard Henderson /*
1449811cc0b0SRichard Henderson  * Build DisasASI.
1450811cc0b0SRichard Henderson  * For asi == -1, treat as non-asi.
1451811cc0b0SRichard Henderson  * For ask == -2, treat as immediate offset (v8 error, v9 %asi).
1452811cc0b0SRichard Henderson  */
1453811cc0b0SRichard Henderson static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)
1454fcf5ef2aSThomas Huth {
1455fcf5ef2aSThomas Huth     ASIType type = GET_ASI_HELPER;
1456fcf5ef2aSThomas Huth     int mem_idx = dc->mem_idx;
1457fcf5ef2aSThomas Huth 
1458811cc0b0SRichard Henderson     if (asi == -1) {
1459811cc0b0SRichard Henderson         /* Artificial "non-asi" case. */
1460811cc0b0SRichard Henderson         type = GET_ASI_DIRECT;
1461811cc0b0SRichard Henderson         goto done;
1462811cc0b0SRichard Henderson     }
1463811cc0b0SRichard Henderson 
1464fcf5ef2aSThomas Huth #ifndef TARGET_SPARC64
1465fcf5ef2aSThomas Huth     /* Before v9, all asis are immediate and privileged.  */
1466811cc0b0SRichard Henderson     if (asi < 0) {
1467fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
1468fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
1469fcf5ef2aSThomas Huth     } else if (supervisor(dc)
1470fcf5ef2aSThomas Huth                /* Note that LEON accepts ASI_USERDATA in user mode, for
1471fcf5ef2aSThomas Huth                   use with CASA.  Also note that previous versions of
1472fcf5ef2aSThomas Huth                   QEMU allowed (and old versions of gcc emitted) ASI_P
1473fcf5ef2aSThomas Huth                   for LEON, which is incorrect.  */
1474fcf5ef2aSThomas Huth                || (asi == ASI_USERDATA
1475fcf5ef2aSThomas Huth                    && (dc->def->features & CPU_FEATURE_CASA))) {
1476fcf5ef2aSThomas Huth         switch (asi) {
1477fcf5ef2aSThomas Huth         case ASI_USERDATA:   /* User data access */
1478fcf5ef2aSThomas Huth             mem_idx = MMU_USER_IDX;
1479fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
1480fcf5ef2aSThomas Huth             break;
1481fcf5ef2aSThomas Huth         case ASI_KERNELDATA: /* Supervisor data access */
1482fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
1483fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
1484fcf5ef2aSThomas Huth             break;
1485fcf5ef2aSThomas Huth         case ASI_M_BYPASS:    /* MMU passthrough */
1486fcf5ef2aSThomas Huth         case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1487fcf5ef2aSThomas Huth             mem_idx = MMU_PHYS_IDX;
1488fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
1489fcf5ef2aSThomas Huth             break;
1490fcf5ef2aSThomas Huth         case ASI_M_BCOPY: /* Block copy, sta access */
1491fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
1492fcf5ef2aSThomas Huth             type = GET_ASI_BCOPY;
1493fcf5ef2aSThomas Huth             break;
1494fcf5ef2aSThomas Huth         case ASI_M_BFILL: /* Block fill, stda access */
1495fcf5ef2aSThomas Huth             mem_idx = MMU_KERNEL_IDX;
1496fcf5ef2aSThomas Huth             type = GET_ASI_BFILL;
1497fcf5ef2aSThomas Huth             break;
1498fcf5ef2aSThomas Huth         }
14996e10f37cSKONRAD Frederic 
15006e10f37cSKONRAD Frederic         /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
15016e10f37cSKONRAD Frederic          * permissions check in get_physical_address(..).
15026e10f37cSKONRAD Frederic          */
15036e10f37cSKONRAD Frederic         mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx;
1504fcf5ef2aSThomas Huth     } else {
1505fcf5ef2aSThomas Huth         gen_exception(dc, TT_PRIV_INSN);
1506fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
1507fcf5ef2aSThomas Huth     }
1508fcf5ef2aSThomas Huth #else
1509811cc0b0SRichard Henderson     if (asi < 0) {
1510fcf5ef2aSThomas Huth         asi = dc->asi;
1511fcf5ef2aSThomas Huth     }
1512fcf5ef2aSThomas Huth     /* With v9, all asis below 0x80 are privileged.  */
1513fcf5ef2aSThomas Huth     /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
1514fcf5ef2aSThomas Huth        down that bit into DisasContext.  For the moment that's ok,
1515fcf5ef2aSThomas Huth        since the direct implementations below doesn't have any ASIs
1516fcf5ef2aSThomas Huth        in the restricted [0x30, 0x7f] range, and the check will be
1517fcf5ef2aSThomas Huth        done properly in the helper.  */
1518fcf5ef2aSThomas Huth     if (!supervisor(dc) && asi < 0x80) {
1519fcf5ef2aSThomas Huth         gen_exception(dc, TT_PRIV_ACT);
1520fcf5ef2aSThomas Huth         type = GET_ASI_EXCP;
1521fcf5ef2aSThomas Huth     } else {
1522fcf5ef2aSThomas Huth         switch (asi) {
1523fcf5ef2aSThomas Huth         case ASI_REAL:      /* Bypass */
1524fcf5ef2aSThomas Huth         case ASI_REAL_IO:   /* Bypass, non-cacheable */
1525fcf5ef2aSThomas Huth         case ASI_REAL_L:    /* Bypass LE */
1526fcf5ef2aSThomas Huth         case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1527fcf5ef2aSThomas Huth         case ASI_TWINX_REAL:   /* Real address, twinx */
1528fcf5ef2aSThomas Huth         case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1529fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS:
1530fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS_L:
1531fcf5ef2aSThomas Huth             mem_idx = MMU_PHYS_IDX;
1532fcf5ef2aSThomas Huth             break;
1533fcf5ef2aSThomas Huth         case ASI_N:  /* Nucleus */
1534fcf5ef2aSThomas Huth         case ASI_NL: /* Nucleus LE */
1535fcf5ef2aSThomas Huth         case ASI_TWINX_N:
1536fcf5ef2aSThomas Huth         case ASI_TWINX_NL:
1537fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD:
1538fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD_L:
15399a10756dSArtyom Tarasenko             if (hypervisor(dc)) {
154084f8f587SArtyom Tarasenko                 mem_idx = MMU_PHYS_IDX;
15419a10756dSArtyom Tarasenko             } else {
1542fcf5ef2aSThomas Huth                 mem_idx = MMU_NUCLEUS_IDX;
15439a10756dSArtyom Tarasenko             }
1544fcf5ef2aSThomas Huth             break;
1545fcf5ef2aSThomas Huth         case ASI_AIUP:  /* As if user primary */
1546fcf5ef2aSThomas Huth         case ASI_AIUPL: /* As if user primary LE */
1547fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP:
1548fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP_L:
1549fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_4V:
1550fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_L_4V:
1551fcf5ef2aSThomas Huth         case ASI_BLK_AIUP:
1552fcf5ef2aSThomas Huth         case ASI_BLK_AIUPL:
1553fcf5ef2aSThomas Huth             mem_idx = MMU_USER_IDX;
1554fcf5ef2aSThomas Huth             break;
1555fcf5ef2aSThomas Huth         case ASI_AIUS:  /* As if user secondary */
1556fcf5ef2aSThomas Huth         case ASI_AIUSL: /* As if user secondary LE */
1557fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS:
1558fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS_L:
1559fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_4V:
1560fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_L_4V:
1561fcf5ef2aSThomas Huth         case ASI_BLK_AIUS:
1562fcf5ef2aSThomas Huth         case ASI_BLK_AIUSL:
1563fcf5ef2aSThomas Huth             mem_idx = MMU_USER_SECONDARY_IDX;
1564fcf5ef2aSThomas Huth             break;
1565fcf5ef2aSThomas Huth         case ASI_S:  /* Secondary */
1566fcf5ef2aSThomas Huth         case ASI_SL: /* Secondary LE */
1567fcf5ef2aSThomas Huth         case ASI_TWINX_S:
1568fcf5ef2aSThomas Huth         case ASI_TWINX_SL:
1569fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_S:
1570fcf5ef2aSThomas Huth         case ASI_BLK_S:
1571fcf5ef2aSThomas Huth         case ASI_BLK_SL:
1572fcf5ef2aSThomas Huth         case ASI_FL8_S:
1573fcf5ef2aSThomas Huth         case ASI_FL8_SL:
1574fcf5ef2aSThomas Huth         case ASI_FL16_S:
1575fcf5ef2aSThomas Huth         case ASI_FL16_SL:
1576fcf5ef2aSThomas Huth             if (mem_idx == MMU_USER_IDX) {
1577fcf5ef2aSThomas Huth                 mem_idx = MMU_USER_SECONDARY_IDX;
1578fcf5ef2aSThomas Huth             } else if (mem_idx == MMU_KERNEL_IDX) {
1579fcf5ef2aSThomas Huth                 mem_idx = MMU_KERNEL_SECONDARY_IDX;
1580fcf5ef2aSThomas Huth             }
1581fcf5ef2aSThomas Huth             break;
1582fcf5ef2aSThomas Huth         case ASI_P:  /* Primary */
1583fcf5ef2aSThomas Huth         case ASI_PL: /* Primary LE */
1584fcf5ef2aSThomas Huth         case ASI_TWINX_P:
1585fcf5ef2aSThomas Huth         case ASI_TWINX_PL:
1586fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_P:
1587fcf5ef2aSThomas Huth         case ASI_BLK_P:
1588fcf5ef2aSThomas Huth         case ASI_BLK_PL:
1589fcf5ef2aSThomas Huth         case ASI_FL8_P:
1590fcf5ef2aSThomas Huth         case ASI_FL8_PL:
1591fcf5ef2aSThomas Huth         case ASI_FL16_P:
1592fcf5ef2aSThomas Huth         case ASI_FL16_PL:
1593fcf5ef2aSThomas Huth             break;
1594fcf5ef2aSThomas Huth         }
1595fcf5ef2aSThomas Huth         switch (asi) {
1596fcf5ef2aSThomas Huth         case ASI_REAL:
1597fcf5ef2aSThomas Huth         case ASI_REAL_IO:
1598fcf5ef2aSThomas Huth         case ASI_REAL_L:
1599fcf5ef2aSThomas Huth         case ASI_REAL_IO_L:
1600fcf5ef2aSThomas Huth         case ASI_N:
1601fcf5ef2aSThomas Huth         case ASI_NL:
1602fcf5ef2aSThomas Huth         case ASI_AIUP:
1603fcf5ef2aSThomas Huth         case ASI_AIUPL:
1604fcf5ef2aSThomas Huth         case ASI_AIUS:
1605fcf5ef2aSThomas Huth         case ASI_AIUSL:
1606fcf5ef2aSThomas Huth         case ASI_S:
1607fcf5ef2aSThomas Huth         case ASI_SL:
1608fcf5ef2aSThomas Huth         case ASI_P:
1609fcf5ef2aSThomas Huth         case ASI_PL:
1610fcf5ef2aSThomas Huth             type = GET_ASI_DIRECT;
1611fcf5ef2aSThomas Huth             break;
1612fcf5ef2aSThomas Huth         case ASI_TWINX_REAL:
1613fcf5ef2aSThomas Huth         case ASI_TWINX_REAL_L:
1614fcf5ef2aSThomas Huth         case ASI_TWINX_N:
1615fcf5ef2aSThomas Huth         case ASI_TWINX_NL:
1616fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP:
1617fcf5ef2aSThomas Huth         case ASI_TWINX_AIUP_L:
1618fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS:
1619fcf5ef2aSThomas Huth         case ASI_TWINX_AIUS_L:
1620fcf5ef2aSThomas Huth         case ASI_TWINX_P:
1621fcf5ef2aSThomas Huth         case ASI_TWINX_PL:
1622fcf5ef2aSThomas Huth         case ASI_TWINX_S:
1623fcf5ef2aSThomas Huth         case ASI_TWINX_SL:
1624fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS:
1625fcf5ef2aSThomas Huth         case ASI_QUAD_LDD_PHYS_L:
1626fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD:
1627fcf5ef2aSThomas Huth         case ASI_NUCLEUS_QUAD_LDD_L:
1628fcf5ef2aSThomas Huth             type = GET_ASI_DTWINX;
1629fcf5ef2aSThomas Huth             break;
1630fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_P:
1631fcf5ef2aSThomas Huth         case ASI_BLK_COMMIT_S:
1632fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_4V:
1633fcf5ef2aSThomas Huth         case ASI_BLK_AIUP_L_4V:
1634fcf5ef2aSThomas Huth         case ASI_BLK_AIUP:
1635fcf5ef2aSThomas Huth         case ASI_BLK_AIUPL:
1636fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_4V:
1637fcf5ef2aSThomas Huth         case ASI_BLK_AIUS_L_4V:
1638fcf5ef2aSThomas Huth         case ASI_BLK_AIUS:
1639fcf5ef2aSThomas Huth         case ASI_BLK_AIUSL:
1640fcf5ef2aSThomas Huth         case ASI_BLK_S:
1641fcf5ef2aSThomas Huth         case ASI_BLK_SL:
1642fcf5ef2aSThomas Huth         case ASI_BLK_P:
1643fcf5ef2aSThomas Huth         case ASI_BLK_PL:
1644fcf5ef2aSThomas Huth             type = GET_ASI_BLOCK;
1645fcf5ef2aSThomas Huth             break;
1646fcf5ef2aSThomas Huth         case ASI_FL8_S:
1647fcf5ef2aSThomas Huth         case ASI_FL8_SL:
1648fcf5ef2aSThomas Huth         case ASI_FL8_P:
1649fcf5ef2aSThomas Huth         case ASI_FL8_PL:
1650fcf5ef2aSThomas Huth             memop = MO_UB;
1651fcf5ef2aSThomas Huth             type = GET_ASI_SHORT;
1652fcf5ef2aSThomas Huth             break;
1653fcf5ef2aSThomas Huth         case ASI_FL16_S:
1654fcf5ef2aSThomas Huth         case ASI_FL16_SL:
1655fcf5ef2aSThomas Huth         case ASI_FL16_P:
1656fcf5ef2aSThomas Huth         case ASI_FL16_PL:
1657fcf5ef2aSThomas Huth             memop = MO_TEUW;
1658fcf5ef2aSThomas Huth             type = GET_ASI_SHORT;
1659fcf5ef2aSThomas Huth             break;
1660fcf5ef2aSThomas Huth         }
1661fcf5ef2aSThomas Huth         /* The little-endian asis all have bit 3 set.  */
1662fcf5ef2aSThomas Huth         if (asi & 8) {
1663fcf5ef2aSThomas Huth             memop ^= MO_BSWAP;
1664fcf5ef2aSThomas Huth         }
1665fcf5ef2aSThomas Huth     }
1666fcf5ef2aSThomas Huth #endif
1667fcf5ef2aSThomas Huth 
1668811cc0b0SRichard Henderson  done:
1669fcf5ef2aSThomas Huth     return (DisasASI){ type, asi, mem_idx, memop };
1670fcf5ef2aSThomas Huth }
1671fcf5ef2aSThomas Huth 
1672a76779eeSRichard Henderson #if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
1673a76779eeSRichard Henderson static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
1674a76779eeSRichard Henderson                               TCGv_i32 asi, TCGv_i32 mop)
1675a76779eeSRichard Henderson {
1676a76779eeSRichard Henderson     g_assert_not_reached();
1677a76779eeSRichard Henderson }
1678a76779eeSRichard Henderson 
1679a76779eeSRichard Henderson static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,
1680a76779eeSRichard Henderson                               TCGv_i32 asi, TCGv_i32 mop)
1681a76779eeSRichard Henderson {
1682a76779eeSRichard Henderson     g_assert_not_reached();
1683a76779eeSRichard Henderson }
1684a76779eeSRichard Henderson #endif
1685a76779eeSRichard Henderson 
168642071fc1SRichard Henderson static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
1687fcf5ef2aSThomas Huth {
1688c03a0fd1SRichard Henderson     switch (da->type) {
1689fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1690fcf5ef2aSThomas Huth         break;
1691fcf5ef2aSThomas Huth     case GET_ASI_DTWINX: /* Reserved for ldda.  */
1692fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
1693fcf5ef2aSThomas Huth         break;
1694fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
1695c03a0fd1SRichard Henderson         tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN);
1696fcf5ef2aSThomas Huth         break;
1697fcf5ef2aSThomas Huth     default:
1698fcf5ef2aSThomas Huth         {
1699c03a0fd1SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
1700c03a0fd1SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
1701fcf5ef2aSThomas Huth 
1702fcf5ef2aSThomas Huth             save_state(dc);
1703fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1704ad75a51eSRichard Henderson             gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop);
1705fcf5ef2aSThomas Huth #else
1706fcf5ef2aSThomas Huth             {
1707fcf5ef2aSThomas Huth                 TCGv_i64 t64 = tcg_temp_new_i64();
1708ad75a51eSRichard Henderson                 gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
1709fcf5ef2aSThomas Huth                 tcg_gen_trunc_i64_tl(dst, t64);
1710fcf5ef2aSThomas Huth             }
1711fcf5ef2aSThomas Huth #endif
1712fcf5ef2aSThomas Huth         }
1713fcf5ef2aSThomas Huth         break;
1714fcf5ef2aSThomas Huth     }
1715fcf5ef2aSThomas Huth }
1716fcf5ef2aSThomas Huth 
171742071fc1SRichard Henderson static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
1718c03a0fd1SRichard Henderson {
1719c03a0fd1SRichard Henderson     switch (da->type) {
1720fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1721fcf5ef2aSThomas Huth         break;
1722c03a0fd1SRichard Henderson 
1723fcf5ef2aSThomas Huth     case GET_ASI_DTWINX: /* Reserved for stda.  */
1724c03a0fd1SRichard Henderson         if (TARGET_LONG_BITS == 32) {
1725fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
1726fcf5ef2aSThomas Huth             break;
1727c03a0fd1SRichard Henderson         } else if (!(dc->def->features & CPU_FEATURE_HYPV)) {
17283390537bSArtyom Tarasenko             /* Pre OpenSPARC CPUs don't have these */
17293390537bSArtyom Tarasenko             gen_exception(dc, TT_ILL_INSN);
1730fcf5ef2aSThomas Huth             break;
1731c03a0fd1SRichard Henderson         }
1732c03a0fd1SRichard Henderson         /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */
1733c03a0fd1SRichard Henderson         /* fall through */
1734c03a0fd1SRichard Henderson 
1735c03a0fd1SRichard Henderson     case GET_ASI_DIRECT:
1736c03a0fd1SRichard Henderson         tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN);
1737c03a0fd1SRichard Henderson         break;
1738c03a0fd1SRichard Henderson 
1739fcf5ef2aSThomas Huth     case GET_ASI_BCOPY:
1740c03a0fd1SRichard Henderson         assert(TARGET_LONG_BITS == 32);
174198271007SRichard Henderson         /*
174298271007SRichard Henderson          * Copy 32 bytes from the address in SRC to ADDR.
174398271007SRichard Henderson          *
174498271007SRichard Henderson          * From Ross RT625 hyperSPARC manual, section 4.6:
174598271007SRichard Henderson          * "Block Copy and Block Fill will work only on cache line boundaries."
174698271007SRichard Henderson          *
174798271007SRichard Henderson          * It does not specify if an unaliged address is truncated or trapped.
174898271007SRichard Henderson          * Previous qemu behaviour was to truncate to 4 byte alignment, which
174998271007SRichard Henderson          * is obviously wrong.  The only place I can see this used is in the
175098271007SRichard Henderson          * Linux kernel which begins with page alignment, advancing by 32,
175198271007SRichard Henderson          * so is always aligned.  Assume truncation as the simpler option.
175298271007SRichard Henderson          *
175398271007SRichard Henderson          * Since the loads and stores are paired, allow the copy to happen
175498271007SRichard Henderson          * in the host endianness.  The copy need not be atomic.
175598271007SRichard Henderson          */
1756fcf5ef2aSThomas Huth         {
175798271007SRichard Henderson             MemOp mop = MO_128 | MO_ATOM_IFALIGN_PAIR;
1758fcf5ef2aSThomas Huth             TCGv saddr = tcg_temp_new();
1759fcf5ef2aSThomas Huth             TCGv daddr = tcg_temp_new();
176098271007SRichard Henderson             TCGv_i128 tmp = tcg_temp_new_i128();
1761fcf5ef2aSThomas Huth 
176298271007SRichard Henderson             tcg_gen_andi_tl(saddr, src, -32);
176398271007SRichard Henderson             tcg_gen_andi_tl(daddr, addr, -32);
176498271007SRichard Henderson             tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop);
176598271007SRichard Henderson             tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop);
176698271007SRichard Henderson             tcg_gen_addi_tl(saddr, saddr, 16);
176798271007SRichard Henderson             tcg_gen_addi_tl(daddr, daddr, 16);
176898271007SRichard Henderson             tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop);
176998271007SRichard Henderson             tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop);
1770fcf5ef2aSThomas Huth         }
1771fcf5ef2aSThomas Huth         break;
1772c03a0fd1SRichard Henderson 
1773fcf5ef2aSThomas Huth     default:
1774fcf5ef2aSThomas Huth         {
1775c03a0fd1SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
1776c03a0fd1SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
1777fcf5ef2aSThomas Huth 
1778fcf5ef2aSThomas Huth             save_state(dc);
1779fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
1780ad75a51eSRichard Henderson             gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop);
1781fcf5ef2aSThomas Huth #else
1782fcf5ef2aSThomas Huth             {
1783fcf5ef2aSThomas Huth                 TCGv_i64 t64 = tcg_temp_new_i64();
1784fcf5ef2aSThomas Huth                 tcg_gen_extu_tl_i64(t64, src);
1785ad75a51eSRichard Henderson                 gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
1786fcf5ef2aSThomas Huth             }
1787fcf5ef2aSThomas Huth #endif
1788fcf5ef2aSThomas Huth 
1789fcf5ef2aSThomas Huth             /* A write to a TLB register may alter page maps.  End the TB. */
1790fcf5ef2aSThomas Huth             dc->npc = DYNAMIC_PC;
1791fcf5ef2aSThomas Huth         }
1792fcf5ef2aSThomas Huth         break;
1793fcf5ef2aSThomas Huth     }
1794fcf5ef2aSThomas Huth }
1795fcf5ef2aSThomas Huth 
1796dca544b9SRichard Henderson static void gen_swap_asi(DisasContext *dc, DisasASI *da,
1797c03a0fd1SRichard Henderson                          TCGv dst, TCGv src, TCGv addr)
1798c03a0fd1SRichard Henderson {
1799c03a0fd1SRichard Henderson     switch (da->type) {
1800c03a0fd1SRichard Henderson     case GET_ASI_EXCP:
1801c03a0fd1SRichard Henderson         break;
1802c03a0fd1SRichard Henderson     case GET_ASI_DIRECT:
1803dca544b9SRichard Henderson         tcg_gen_atomic_xchg_tl(dst, addr, src,
1804dca544b9SRichard Henderson                                da->mem_idx, da->memop | MO_ALIGN);
1805c03a0fd1SRichard Henderson         break;
1806c03a0fd1SRichard Henderson     default:
1807c03a0fd1SRichard Henderson         /* ??? Should be DAE_invalid_asi.  */
1808c03a0fd1SRichard Henderson         gen_exception(dc, TT_DATA_ACCESS);
1809c03a0fd1SRichard Henderson         break;
1810c03a0fd1SRichard Henderson     }
1811c03a0fd1SRichard Henderson }
1812c03a0fd1SRichard Henderson 
1813d0a11d25SRichard Henderson static void gen_cas_asi(DisasContext *dc, DisasASI *da,
1814c03a0fd1SRichard Henderson                         TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
1815c03a0fd1SRichard Henderson {
1816c03a0fd1SRichard Henderson     switch (da->type) {
1817fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1818c03a0fd1SRichard Henderson         return;
1819fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
1820c03a0fd1SRichard Henderson         tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv,
1821c03a0fd1SRichard Henderson                                   da->mem_idx, da->memop | MO_ALIGN);
1822fcf5ef2aSThomas Huth         break;
1823fcf5ef2aSThomas Huth     default:
1824fcf5ef2aSThomas Huth         /* ??? Should be DAE_invalid_asi.  */
1825fcf5ef2aSThomas Huth         gen_exception(dc, TT_DATA_ACCESS);
1826fcf5ef2aSThomas Huth         break;
1827fcf5ef2aSThomas Huth     }
1828fcf5ef2aSThomas Huth }
1829fcf5ef2aSThomas Huth 
1830cf07cd1eSRichard Henderson static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
1831c03a0fd1SRichard Henderson {
1832c03a0fd1SRichard Henderson     switch (da->type) {
1833fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1834fcf5ef2aSThomas Huth         break;
1835fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
1836cf07cd1eSRichard Henderson         tcg_gen_atomic_xchg_tl(dst, addr, tcg_constant_tl(0xff),
1837cf07cd1eSRichard Henderson                                da->mem_idx, MO_UB);
1838fcf5ef2aSThomas Huth         break;
1839fcf5ef2aSThomas Huth     default:
18403db010c3SRichard Henderson         /* ??? In theory, this should be raise DAE_invalid_asi.
18413db010c3SRichard Henderson            But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1.  */
1842af00be49SEmilio G. Cota         if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
1843ad75a51eSRichard Henderson             gen_helper_exit_atomic(tcg_env);
18443db010c3SRichard Henderson         } else {
1845c03a0fd1SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
184600ab7e61SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(MO_UB);
18473db010c3SRichard Henderson             TCGv_i64 s64, t64;
18483db010c3SRichard Henderson 
18493db010c3SRichard Henderson             save_state(dc);
18503db010c3SRichard Henderson             t64 = tcg_temp_new_i64();
1851ad75a51eSRichard Henderson             gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
18523db010c3SRichard Henderson 
185300ab7e61SRichard Henderson             s64 = tcg_constant_i64(0xff);
1854ad75a51eSRichard Henderson             gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop);
18553db010c3SRichard Henderson 
18563db010c3SRichard Henderson             tcg_gen_trunc_i64_tl(dst, t64);
18573db010c3SRichard Henderson 
18583db010c3SRichard Henderson             /* End the TB.  */
18593db010c3SRichard Henderson             dc->npc = DYNAMIC_PC;
18603db010c3SRichard Henderson         }
1861fcf5ef2aSThomas Huth         break;
1862fcf5ef2aSThomas Huth     }
1863fcf5ef2aSThomas Huth }
1864fcf5ef2aSThomas Huth 
1865287b1152SRichard Henderson static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
18663259b9e2SRichard Henderson                         TCGv addr, int rd)
1867fcf5ef2aSThomas Huth {
18683259b9e2SRichard Henderson     MemOp memop = da->memop;
18693259b9e2SRichard Henderson     MemOp size = memop & MO_SIZE;
1870fcf5ef2aSThomas Huth     TCGv_i32 d32;
1871fcf5ef2aSThomas Huth     TCGv_i64 d64;
1872287b1152SRichard Henderson     TCGv addr_tmp;
1873fcf5ef2aSThomas Huth 
18743259b9e2SRichard Henderson     /* TODO: Use 128-bit load/store below. */
18753259b9e2SRichard Henderson     if (size == MO_128) {
18763259b9e2SRichard Henderson         memop = (memop & ~MO_SIZE) | MO_64;
18773259b9e2SRichard Henderson     }
18783259b9e2SRichard Henderson 
18793259b9e2SRichard Henderson     switch (da->type) {
1880fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1881fcf5ef2aSThomas Huth         break;
1882fcf5ef2aSThomas Huth 
1883fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
18843259b9e2SRichard Henderson         memop |= MO_ALIGN_4;
1885fcf5ef2aSThomas Huth         switch (size) {
18863259b9e2SRichard Henderson         case MO_32:
1887388a6465SRichard Henderson             d32 = tcg_temp_new_i32();
18883259b9e2SRichard Henderson             tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop);
1889fcf5ef2aSThomas Huth             gen_store_fpr_F(dc, rd, d32);
1890fcf5ef2aSThomas Huth             break;
18913259b9e2SRichard Henderson 
18923259b9e2SRichard Henderson         case MO_64:
18933259b9e2SRichard Henderson             tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop);
1894fcf5ef2aSThomas Huth             break;
18953259b9e2SRichard Henderson 
18963259b9e2SRichard Henderson         case MO_128:
1897fcf5ef2aSThomas Huth             d64 = tcg_temp_new_i64();
18983259b9e2SRichard Henderson             tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
1899287b1152SRichard Henderson             addr_tmp = tcg_temp_new();
1900287b1152SRichard Henderson             tcg_gen_addi_tl(addr_tmp, addr, 8);
1901287b1152SRichard Henderson             tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
1902fcf5ef2aSThomas Huth             tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
1903fcf5ef2aSThomas Huth             break;
1904fcf5ef2aSThomas Huth         default:
1905fcf5ef2aSThomas Huth             g_assert_not_reached();
1906fcf5ef2aSThomas Huth         }
1907fcf5ef2aSThomas Huth         break;
1908fcf5ef2aSThomas Huth 
1909fcf5ef2aSThomas Huth     case GET_ASI_BLOCK:
1910fcf5ef2aSThomas Huth         /* Valid for lddfa on aligned registers only.  */
19113259b9e2SRichard Henderson         if (orig_size == MO_64 && (rd & 7) == 0) {
1912fcf5ef2aSThomas Huth             /* The first operation checks required alignment.  */
1913287b1152SRichard Henderson             addr_tmp = tcg_temp_new();
1914287b1152SRichard Henderson             for (int i = 0; ; ++i) {
19153259b9e2SRichard Henderson                 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
19163259b9e2SRichard Henderson                                     memop | (i == 0 ? MO_ALIGN_64 : 0));
1917fcf5ef2aSThomas Huth                 if (i == 7) {
1918fcf5ef2aSThomas Huth                     break;
1919fcf5ef2aSThomas Huth                 }
1920287b1152SRichard Henderson                 tcg_gen_addi_tl(addr_tmp, addr, 8);
1921287b1152SRichard Henderson                 addr = addr_tmp;
1922fcf5ef2aSThomas Huth             }
1923fcf5ef2aSThomas Huth         } else {
1924fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
1925fcf5ef2aSThomas Huth         }
1926fcf5ef2aSThomas Huth         break;
1927fcf5ef2aSThomas Huth 
1928fcf5ef2aSThomas Huth     case GET_ASI_SHORT:
1929fcf5ef2aSThomas Huth         /* Valid for lddfa only.  */
19303259b9e2SRichard Henderson         if (orig_size == MO_64) {
19313259b9e2SRichard Henderson             tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
19323259b9e2SRichard Henderson                                 memop | MO_ALIGN);
1933fcf5ef2aSThomas Huth         } else {
1934fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
1935fcf5ef2aSThomas Huth         }
1936fcf5ef2aSThomas Huth         break;
1937fcf5ef2aSThomas Huth 
1938fcf5ef2aSThomas Huth     default:
1939fcf5ef2aSThomas Huth         {
19403259b9e2SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
19413259b9e2SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
1942fcf5ef2aSThomas Huth 
1943fcf5ef2aSThomas Huth             save_state(dc);
1944fcf5ef2aSThomas Huth             /* According to the table in the UA2011 manual, the only
1945fcf5ef2aSThomas Huth                other asis that are valid for ldfa/lddfa/ldqfa are
1946fcf5ef2aSThomas Huth                the NO_FAULT asis.  We still need a helper for these,
1947fcf5ef2aSThomas Huth                but we can just use the integer asi helper for them.  */
1948fcf5ef2aSThomas Huth             switch (size) {
19493259b9e2SRichard Henderson             case MO_32:
1950fcf5ef2aSThomas Huth                 d64 = tcg_temp_new_i64();
1951ad75a51eSRichard Henderson                 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
1952388a6465SRichard Henderson                 d32 = tcg_temp_new_i32();
1953fcf5ef2aSThomas Huth                 tcg_gen_extrl_i64_i32(d32, d64);
1954fcf5ef2aSThomas Huth                 gen_store_fpr_F(dc, rd, d32);
1955fcf5ef2aSThomas Huth                 break;
19563259b9e2SRichard Henderson             case MO_64:
19573259b9e2SRichard Henderson                 gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr,
19583259b9e2SRichard Henderson                                   r_asi, r_mop);
1959fcf5ef2aSThomas Huth                 break;
19603259b9e2SRichard Henderson             case MO_128:
1961fcf5ef2aSThomas Huth                 d64 = tcg_temp_new_i64();
1962ad75a51eSRichard Henderson                 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
1963287b1152SRichard Henderson                 addr_tmp = tcg_temp_new();
1964287b1152SRichard Henderson                 tcg_gen_addi_tl(addr_tmp, addr, 8);
1965287b1152SRichard Henderson                 gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp,
19663259b9e2SRichard Henderson                                   r_asi, r_mop);
1967fcf5ef2aSThomas Huth                 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
1968fcf5ef2aSThomas Huth                 break;
1969fcf5ef2aSThomas Huth             default:
1970fcf5ef2aSThomas Huth                 g_assert_not_reached();
1971fcf5ef2aSThomas Huth             }
1972fcf5ef2aSThomas Huth         }
1973fcf5ef2aSThomas Huth         break;
1974fcf5ef2aSThomas Huth     }
1975fcf5ef2aSThomas Huth }
1976fcf5ef2aSThomas Huth 
1977287b1152SRichard Henderson static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
19783259b9e2SRichard Henderson                         TCGv addr, int rd)
19793259b9e2SRichard Henderson {
19803259b9e2SRichard Henderson     MemOp memop = da->memop;
19813259b9e2SRichard Henderson     MemOp size = memop & MO_SIZE;
1982fcf5ef2aSThomas Huth     TCGv_i32 d32;
1983287b1152SRichard Henderson     TCGv addr_tmp;
1984fcf5ef2aSThomas Huth 
19853259b9e2SRichard Henderson     /* TODO: Use 128-bit load/store below. */
19863259b9e2SRichard Henderson     if (size == MO_128) {
19873259b9e2SRichard Henderson         memop = (memop & ~MO_SIZE) | MO_64;
19883259b9e2SRichard Henderson     }
19893259b9e2SRichard Henderson 
19903259b9e2SRichard Henderson     switch (da->type) {
1991fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
1992fcf5ef2aSThomas Huth         break;
1993fcf5ef2aSThomas Huth 
1994fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
19953259b9e2SRichard Henderson         memop |= MO_ALIGN_4;
1996fcf5ef2aSThomas Huth         switch (size) {
19973259b9e2SRichard Henderson         case MO_32:
1998fcf5ef2aSThomas Huth             d32 = gen_load_fpr_F(dc, rd);
19993259b9e2SRichard Henderson             tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN);
2000fcf5ef2aSThomas Huth             break;
20013259b9e2SRichard Henderson         case MO_64:
20023259b9e2SRichard Henderson             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
20033259b9e2SRichard Henderson                                 memop | MO_ALIGN_4);
2004fcf5ef2aSThomas Huth             break;
20053259b9e2SRichard Henderson         case MO_128:
2006fcf5ef2aSThomas Huth             /* Only 4-byte alignment required.  However, it is legal for the
2007fcf5ef2aSThomas Huth                cpu to signal the alignment fault, and the OS trap handler is
2008fcf5ef2aSThomas Huth                required to fix it up.  Requiring 16-byte alignment here avoids
2009fcf5ef2aSThomas Huth                having to probe the second page before performing the first
2010fcf5ef2aSThomas Huth                write.  */
20113259b9e2SRichard Henderson             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
20123259b9e2SRichard Henderson                                 memop | MO_ALIGN_16);
2013287b1152SRichard Henderson             addr_tmp = tcg_temp_new();
2014287b1152SRichard Henderson             tcg_gen_addi_tl(addr_tmp, addr, 8);
2015287b1152SRichard Henderson             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
2016fcf5ef2aSThomas Huth             break;
2017fcf5ef2aSThomas Huth         default:
2018fcf5ef2aSThomas Huth             g_assert_not_reached();
2019fcf5ef2aSThomas Huth         }
2020fcf5ef2aSThomas Huth         break;
2021fcf5ef2aSThomas Huth 
2022fcf5ef2aSThomas Huth     case GET_ASI_BLOCK:
2023fcf5ef2aSThomas Huth         /* Valid for stdfa on aligned registers only.  */
20243259b9e2SRichard Henderson         if (orig_size == MO_64 && (rd & 7) == 0) {
2025fcf5ef2aSThomas Huth             /* The first operation checks required alignment.  */
2026287b1152SRichard Henderson             addr_tmp = tcg_temp_new();
2027287b1152SRichard Henderson             for (int i = 0; ; ++i) {
20283259b9e2SRichard Henderson                 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
20293259b9e2SRichard Henderson                                     memop | (i == 0 ? MO_ALIGN_64 : 0));
2030fcf5ef2aSThomas Huth                 if (i == 7) {
2031fcf5ef2aSThomas Huth                     break;
2032fcf5ef2aSThomas Huth                 }
2033287b1152SRichard Henderson                 tcg_gen_addi_tl(addr_tmp, addr, 8);
2034287b1152SRichard Henderson                 addr = addr_tmp;
2035fcf5ef2aSThomas Huth             }
2036fcf5ef2aSThomas Huth         } else {
2037fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2038fcf5ef2aSThomas Huth         }
2039fcf5ef2aSThomas Huth         break;
2040fcf5ef2aSThomas Huth 
2041fcf5ef2aSThomas Huth     case GET_ASI_SHORT:
2042fcf5ef2aSThomas Huth         /* Valid for stdfa only.  */
20433259b9e2SRichard Henderson         if (orig_size == MO_64) {
20443259b9e2SRichard Henderson             tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
20453259b9e2SRichard Henderson                                 memop | MO_ALIGN);
2046fcf5ef2aSThomas Huth         } else {
2047fcf5ef2aSThomas Huth             gen_exception(dc, TT_ILL_INSN);
2048fcf5ef2aSThomas Huth         }
2049fcf5ef2aSThomas Huth         break;
2050fcf5ef2aSThomas Huth 
2051fcf5ef2aSThomas Huth     default:
2052fcf5ef2aSThomas Huth         /* According to the table in the UA2011 manual, the only
2053fcf5ef2aSThomas Huth            other asis that are valid for ldfa/lddfa/ldqfa are
2054fcf5ef2aSThomas Huth            the PST* asis, which aren't currently handled.  */
2055fcf5ef2aSThomas Huth         gen_exception(dc, TT_ILL_INSN);
2056fcf5ef2aSThomas Huth         break;
2057fcf5ef2aSThomas Huth     }
2058fcf5ef2aSThomas Huth }
2059fcf5ef2aSThomas Huth 
206042071fc1SRichard Henderson static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
2061fcf5ef2aSThomas Huth {
2062a76779eeSRichard Henderson     TCGv hi = gen_dest_gpr(dc, rd);
2063a76779eeSRichard Henderson     TCGv lo = gen_dest_gpr(dc, rd + 1);
2064fcf5ef2aSThomas Huth 
2065c03a0fd1SRichard Henderson     switch (da->type) {
2066fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2067fcf5ef2aSThomas Huth         return;
2068fcf5ef2aSThomas Huth 
2069fcf5ef2aSThomas Huth     case GET_ASI_DTWINX:
2070ebbbec92SRichard Henderson #ifdef TARGET_SPARC64
2071ebbbec92SRichard Henderson         {
2072ebbbec92SRichard Henderson             MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
2073ebbbec92SRichard Henderson             TCGv_i128 t = tcg_temp_new_i128();
2074ebbbec92SRichard Henderson 
2075ebbbec92SRichard Henderson             tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop);
2076ebbbec92SRichard Henderson             /*
2077ebbbec92SRichard Henderson              * Note that LE twinx acts as if each 64-bit register result is
2078ebbbec92SRichard Henderson              * byte swapped.  We perform one 128-bit LE load, so must swap
2079ebbbec92SRichard Henderson              * the order of the writebacks.
2080ebbbec92SRichard Henderson              */
2081ebbbec92SRichard Henderson             if ((mop & MO_BSWAP) == MO_TE) {
2082ebbbec92SRichard Henderson                 tcg_gen_extr_i128_i64(lo, hi, t);
2083ebbbec92SRichard Henderson             } else {
2084ebbbec92SRichard Henderson                 tcg_gen_extr_i128_i64(hi, lo, t);
2085ebbbec92SRichard Henderson             }
2086ebbbec92SRichard Henderson         }
2087fcf5ef2aSThomas Huth         break;
2088ebbbec92SRichard Henderson #else
2089ebbbec92SRichard Henderson         g_assert_not_reached();
2090ebbbec92SRichard Henderson #endif
2091fcf5ef2aSThomas Huth 
2092fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2093fcf5ef2aSThomas Huth         {
2094fcf5ef2aSThomas Huth             TCGv_i64 tmp = tcg_temp_new_i64();
2095fcf5ef2aSThomas Huth 
2096c03a0fd1SRichard Henderson             tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALIGN);
2097fcf5ef2aSThomas Huth 
2098fcf5ef2aSThomas Huth             /* Note that LE ldda acts as if each 32-bit register
2099fcf5ef2aSThomas Huth                result is byte swapped.  Having just performed one
2100fcf5ef2aSThomas Huth                64-bit bswap, we need now to swap the writebacks.  */
2101c03a0fd1SRichard Henderson             if ((da->memop & MO_BSWAP) == MO_TE) {
2102a76779eeSRichard Henderson                 tcg_gen_extr_i64_tl(lo, hi, tmp);
2103fcf5ef2aSThomas Huth             } else {
2104a76779eeSRichard Henderson                 tcg_gen_extr_i64_tl(hi, lo, tmp);
2105fcf5ef2aSThomas Huth             }
2106fcf5ef2aSThomas Huth         }
2107fcf5ef2aSThomas Huth         break;
2108fcf5ef2aSThomas Huth 
2109fcf5ef2aSThomas Huth     default:
2110fcf5ef2aSThomas Huth         /* ??? In theory we've handled all of the ASIs that are valid
2111fcf5ef2aSThomas Huth            for ldda, and this should raise DAE_invalid_asi.  However,
2112fcf5ef2aSThomas Huth            real hardware allows others.  This can be seen with e.g.
2113fcf5ef2aSThomas Huth            FreeBSD 10.3 wrt ASI_IC_TAG.  */
2114fcf5ef2aSThomas Huth         {
2115c03a0fd1SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2116c03a0fd1SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(da->memop);
2117fcf5ef2aSThomas Huth             TCGv_i64 tmp = tcg_temp_new_i64();
2118fcf5ef2aSThomas Huth 
2119fcf5ef2aSThomas Huth             save_state(dc);
2120ad75a51eSRichard Henderson             gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
2121fcf5ef2aSThomas Huth 
2122fcf5ef2aSThomas Huth             /* See above.  */
2123c03a0fd1SRichard Henderson             if ((da->memop & MO_BSWAP) == MO_TE) {
2124a76779eeSRichard Henderson                 tcg_gen_extr_i64_tl(lo, hi, tmp);
2125fcf5ef2aSThomas Huth             } else {
2126a76779eeSRichard Henderson                 tcg_gen_extr_i64_tl(hi, lo, tmp);
2127fcf5ef2aSThomas Huth             }
2128fcf5ef2aSThomas Huth         }
2129fcf5ef2aSThomas Huth         break;
2130fcf5ef2aSThomas Huth     }
2131fcf5ef2aSThomas Huth 
2132fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd, hi);
2133fcf5ef2aSThomas Huth     gen_store_gpr(dc, rd + 1, lo);
2134fcf5ef2aSThomas Huth }
2135fcf5ef2aSThomas Huth 
213642071fc1SRichard Henderson static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
2137c03a0fd1SRichard Henderson {
2138c03a0fd1SRichard Henderson     TCGv hi = gen_load_gpr(dc, rd);
2139fcf5ef2aSThomas Huth     TCGv lo = gen_load_gpr(dc, rd + 1);
2140fcf5ef2aSThomas Huth 
2141c03a0fd1SRichard Henderson     switch (da->type) {
2142fcf5ef2aSThomas Huth     case GET_ASI_EXCP:
2143fcf5ef2aSThomas Huth         break;
2144fcf5ef2aSThomas Huth 
2145fcf5ef2aSThomas Huth     case GET_ASI_DTWINX:
2146ebbbec92SRichard Henderson #ifdef TARGET_SPARC64
2147ebbbec92SRichard Henderson         {
2148ebbbec92SRichard Henderson             MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
2149ebbbec92SRichard Henderson             TCGv_i128 t = tcg_temp_new_i128();
2150ebbbec92SRichard Henderson 
2151ebbbec92SRichard Henderson             /*
2152ebbbec92SRichard Henderson              * Note that LE twinx acts as if each 64-bit register result is
2153ebbbec92SRichard Henderson              * byte swapped.  We perform one 128-bit LE store, so must swap
2154ebbbec92SRichard Henderson              * the order of the construction.
2155ebbbec92SRichard Henderson              */
2156ebbbec92SRichard Henderson             if ((mop & MO_BSWAP) == MO_TE) {
2157ebbbec92SRichard Henderson                 tcg_gen_concat_i64_i128(t, lo, hi);
2158ebbbec92SRichard Henderson             } else {
2159ebbbec92SRichard Henderson                 tcg_gen_concat_i64_i128(t, hi, lo);
2160ebbbec92SRichard Henderson             }
2161ebbbec92SRichard Henderson             tcg_gen_qemu_st_i128(t, addr, da->mem_idx, mop);
2162ebbbec92SRichard Henderson         }
2163fcf5ef2aSThomas Huth         break;
2164ebbbec92SRichard Henderson #else
2165ebbbec92SRichard Henderson         g_assert_not_reached();
2166ebbbec92SRichard Henderson #endif
2167fcf5ef2aSThomas Huth 
2168fcf5ef2aSThomas Huth     case GET_ASI_DIRECT:
2169fcf5ef2aSThomas Huth         {
2170fcf5ef2aSThomas Huth             TCGv_i64 t64 = tcg_temp_new_i64();
2171fcf5ef2aSThomas Huth 
2172fcf5ef2aSThomas Huth             /* Note that LE stda acts as if each 32-bit register result is
2173fcf5ef2aSThomas Huth                byte swapped.  We will perform one 64-bit LE store, so now
2174fcf5ef2aSThomas Huth                we must swap the order of the construction.  */
2175c03a0fd1SRichard Henderson             if ((da->memop & MO_BSWAP) == MO_TE) {
2176a76779eeSRichard Henderson                 tcg_gen_concat_tl_i64(t64, lo, hi);
2177fcf5ef2aSThomas Huth             } else {
2178a76779eeSRichard Henderson                 tcg_gen_concat_tl_i64(t64, hi, lo);
2179fcf5ef2aSThomas Huth             }
2180c03a0fd1SRichard Henderson             tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALIGN);
2181fcf5ef2aSThomas Huth         }
2182fcf5ef2aSThomas Huth         break;
2183fcf5ef2aSThomas Huth 
2184a76779eeSRichard Henderson     case GET_ASI_BFILL:
2185a76779eeSRichard Henderson         assert(TARGET_LONG_BITS == 32);
218654c3e953SRichard Henderson         /*
218754c3e953SRichard Henderson          * Store 32 bytes of [rd:rd+1] to ADDR.
218854c3e953SRichard Henderson          * See comments for GET_ASI_COPY above.
218954c3e953SRichard Henderson          */
2190a76779eeSRichard Henderson         {
219154c3e953SRichard Henderson             MemOp mop = MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR;
219254c3e953SRichard Henderson             TCGv_i64 t8 = tcg_temp_new_i64();
219354c3e953SRichard Henderson             TCGv_i128 t16 = tcg_temp_new_i128();
219454c3e953SRichard Henderson             TCGv daddr = tcg_temp_new();
2195a76779eeSRichard Henderson 
219654c3e953SRichard Henderson             tcg_gen_concat_tl_i64(t8, lo, hi);
219754c3e953SRichard Henderson             tcg_gen_concat_i64_i128(t16, t8, t8);
219854c3e953SRichard Henderson             tcg_gen_andi_tl(daddr, addr, -32);
219954c3e953SRichard Henderson             tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop);
220054c3e953SRichard Henderson             tcg_gen_addi_tl(daddr, daddr, 16);
220154c3e953SRichard Henderson             tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop);
2202a76779eeSRichard Henderson         }
2203a76779eeSRichard Henderson         break;
2204a76779eeSRichard Henderson 
2205fcf5ef2aSThomas Huth     default:
2206fcf5ef2aSThomas Huth         /* ??? In theory we've handled all of the ASIs that are valid
2207fcf5ef2aSThomas Huth            for stda, and this should raise DAE_invalid_asi.  */
2208fcf5ef2aSThomas Huth         {
2209c03a0fd1SRichard Henderson             TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2210c03a0fd1SRichard Henderson             TCGv_i32 r_mop = tcg_constant_i32(da->memop);
2211fcf5ef2aSThomas Huth             TCGv_i64 t64 = tcg_temp_new_i64();
2212fcf5ef2aSThomas Huth 
2213fcf5ef2aSThomas Huth             /* See above.  */
2214c03a0fd1SRichard Henderson             if ((da->memop & MO_BSWAP) == MO_TE) {
2215a76779eeSRichard Henderson                 tcg_gen_concat_tl_i64(t64, lo, hi);
2216fcf5ef2aSThomas Huth             } else {
2217a76779eeSRichard Henderson                 tcg_gen_concat_tl_i64(t64, hi, lo);
2218fcf5ef2aSThomas Huth             }
2219fcf5ef2aSThomas Huth 
2220fcf5ef2aSThomas Huth             save_state(dc);
2221ad75a51eSRichard Henderson             gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
2222fcf5ef2aSThomas Huth         }
2223fcf5ef2aSThomas Huth         break;
2224fcf5ef2aSThomas Huth     }
2225fcf5ef2aSThomas Huth }
2226fcf5ef2aSThomas Huth 
2227fcf5ef2aSThomas Huth static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2228fcf5ef2aSThomas Huth {
2229f7ec8155SRichard Henderson #ifdef TARGET_SPARC64
2230fcf5ef2aSThomas Huth     TCGv_i32 c32, zero, dst, s1, s2;
2231dd7dbfccSRichard Henderson     TCGv_i64 c64 = tcg_temp_new_i64();
2232fcf5ef2aSThomas Huth 
2233fcf5ef2aSThomas Huth     /* We have two choices here: extend the 32 bit data and use movcond_i64,
2234fcf5ef2aSThomas Huth        or fold the comparison down to 32 bits and use movcond_i32.  Choose
2235fcf5ef2aSThomas Huth        the later.  */
2236fcf5ef2aSThomas Huth     c32 = tcg_temp_new_i32();
2237c8507ebfSRichard Henderson     tcg_gen_setcondi_i64(cmp->cond, c64, cmp->c1, cmp->c2);
2238fcf5ef2aSThomas Huth     tcg_gen_extrl_i64_i32(c32, c64);
2239fcf5ef2aSThomas Huth 
2240fcf5ef2aSThomas Huth     s1 = gen_load_fpr_F(dc, rs);
2241fcf5ef2aSThomas Huth     s2 = gen_load_fpr_F(dc, rd);
2242388a6465SRichard Henderson     dst = tcg_temp_new_i32();
224300ab7e61SRichard Henderson     zero = tcg_constant_i32(0);
2244fcf5ef2aSThomas Huth 
2245fcf5ef2aSThomas Huth     tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2246fcf5ef2aSThomas Huth 
2247fcf5ef2aSThomas Huth     gen_store_fpr_F(dc, rd, dst);
2248f7ec8155SRichard Henderson #else
2249f7ec8155SRichard Henderson     qemu_build_not_reached();
2250f7ec8155SRichard Henderson #endif
2251fcf5ef2aSThomas Huth }
2252fcf5ef2aSThomas Huth 
2253fcf5ef2aSThomas Huth static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2254fcf5ef2aSThomas Huth {
2255f7ec8155SRichard Henderson #ifdef TARGET_SPARC64
2256fcf5ef2aSThomas Huth     TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
2257c8507ebfSRichard Henderson     tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, tcg_constant_tl(cmp->c2),
2258fcf5ef2aSThomas Huth                         gen_load_fpr_D(dc, rs),
2259fcf5ef2aSThomas Huth                         gen_load_fpr_D(dc, rd));
2260fcf5ef2aSThomas Huth     gen_store_fpr_D(dc, rd, dst);
2261f7ec8155SRichard Henderson #else
2262f7ec8155SRichard Henderson     qemu_build_not_reached();
2263f7ec8155SRichard Henderson #endif
2264fcf5ef2aSThomas Huth }
2265fcf5ef2aSThomas Huth 
2266fcf5ef2aSThomas Huth static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2267fcf5ef2aSThomas Huth {
2268f7ec8155SRichard Henderson #ifdef TARGET_SPARC64
2269fcf5ef2aSThomas Huth     int qd = QFPREG(rd);
2270fcf5ef2aSThomas Huth     int qs = QFPREG(rs);
2271c8507ebfSRichard Henderson     TCGv c2 = tcg_constant_tl(cmp->c2);
2272fcf5ef2aSThomas Huth 
2273c8507ebfSRichard Henderson     tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, c2,
2274fcf5ef2aSThomas Huth                         cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2275c8507ebfSRichard Henderson     tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, c2,
2276fcf5ef2aSThomas Huth                         cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2277fcf5ef2aSThomas Huth 
2278fcf5ef2aSThomas Huth     gen_update_fprs_dirty(dc, qd);
2279f7ec8155SRichard Henderson #else
2280f7ec8155SRichard Henderson     qemu_build_not_reached();
2281f7ec8155SRichard Henderson #endif
2282fcf5ef2aSThomas Huth }
2283fcf5ef2aSThomas Huth 
2284f7ec8155SRichard Henderson #ifdef TARGET_SPARC64
22855d617bfbSRichard Henderson static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
2286fcf5ef2aSThomas Huth {
2287fcf5ef2aSThomas Huth     TCGv_i32 r_tl = tcg_temp_new_i32();
2288fcf5ef2aSThomas Huth 
2289fcf5ef2aSThomas Huth     /* load env->tl into r_tl */
2290ad75a51eSRichard Henderson     tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl));
2291fcf5ef2aSThomas Huth 
2292fcf5ef2aSThomas Huth     /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2293fcf5ef2aSThomas Huth     tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
2294fcf5ef2aSThomas Huth 
2295fcf5ef2aSThomas Huth     /* calculate offset to current trap state from env->ts, reuse r_tl */
2296fcf5ef2aSThomas Huth     tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
2297ad75a51eSRichard Henderson     tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts));
2298fcf5ef2aSThomas Huth 
2299fcf5ef2aSThomas Huth     /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2300fcf5ef2aSThomas Huth     {
2301fcf5ef2aSThomas Huth         TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2302fcf5ef2aSThomas Huth         tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2303fcf5ef2aSThomas Huth         tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
2304fcf5ef2aSThomas Huth     }
2305fcf5ef2aSThomas Huth }
2306fcf5ef2aSThomas Huth #endif
2307fcf5ef2aSThomas Huth 
230806c060d9SRichard Henderson static int extract_dfpreg(DisasContext *dc, int x)
230906c060d9SRichard Henderson {
231006c060d9SRichard Henderson     return DFPREG(x);
231106c060d9SRichard Henderson }
231206c060d9SRichard Henderson 
231306c060d9SRichard Henderson static int extract_qfpreg(DisasContext *dc, int x)
231406c060d9SRichard Henderson {
231506c060d9SRichard Henderson     return QFPREG(x);
231606c060d9SRichard Henderson }
231706c060d9SRichard Henderson 
2318878cc677SRichard Henderson /* Include the auto-generated decoder.  */
2319878cc677SRichard Henderson #include "decode-insns.c.inc"
2320878cc677SRichard Henderson 
2321878cc677SRichard Henderson #define TRANS(NAME, AVAIL, FUNC, ...) \
2322878cc677SRichard Henderson     static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \
2323878cc677SRichard Henderson     { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); }
2324878cc677SRichard Henderson 
2325878cc677SRichard Henderson #define avail_ALL(C)      true
2326878cc677SRichard Henderson #ifdef TARGET_SPARC64
2327878cc677SRichard Henderson # define avail_32(C)      false
2328af25071cSRichard Henderson # define avail_ASR17(C)   false
2329d0a11d25SRichard Henderson # define avail_CASA(C)    true
2330c2636853SRichard Henderson # define avail_DIV(C)     true
2331b5372650SRichard Henderson # define avail_MUL(C)     true
23320faef01bSRichard Henderson # define avail_POWERDOWN(C) false
2333878cc677SRichard Henderson # define avail_64(C)      true
23345d617bfbSRichard Henderson # define avail_GL(C)      ((C)->def->features & CPU_FEATURE_GL)
2335af25071cSRichard Henderson # define avail_HYPV(C)    ((C)->def->features & CPU_FEATURE_HYPV)
2336b88ce6f2SRichard Henderson # define avail_VIS1(C)    ((C)->def->features & CPU_FEATURE_VIS1)
2337b88ce6f2SRichard Henderson # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
2338878cc677SRichard Henderson #else
2339878cc677SRichard Henderson # define avail_32(C)      true
2340af25071cSRichard Henderson # define avail_ASR17(C)   ((C)->def->features & CPU_FEATURE_ASR17)
2341d0a11d25SRichard Henderson # define avail_CASA(C)    ((C)->def->features & CPU_FEATURE_CASA)
2342c2636853SRichard Henderson # define avail_DIV(C)     ((C)->def->features & CPU_FEATURE_DIV)
2343b5372650SRichard Henderson # define avail_MUL(C)     ((C)->def->features & CPU_FEATURE_MUL)
23440faef01bSRichard Henderson # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
2345878cc677SRichard Henderson # define avail_64(C)      false
23465d617bfbSRichard Henderson # define avail_GL(C)      false
2347af25071cSRichard Henderson # define avail_HYPV(C)    false
2348b88ce6f2SRichard Henderson # define avail_VIS1(C)    false
2349b88ce6f2SRichard Henderson # define avail_VIS2(C)    false
2350878cc677SRichard Henderson #endif
2351878cc677SRichard Henderson 
2352878cc677SRichard Henderson /* Default case for non jump instructions. */
2353878cc677SRichard Henderson static bool advance_pc(DisasContext *dc)
2354878cc677SRichard Henderson {
23554a8d145dSRichard Henderson     TCGLabel *l1;
23564a8d145dSRichard Henderson 
235789527e3aSRichard Henderson     finishing_insn(dc);
235889527e3aSRichard Henderson 
2359878cc677SRichard Henderson     if (dc->npc & 3) {
2360878cc677SRichard Henderson         switch (dc->npc) {
2361878cc677SRichard Henderson         case DYNAMIC_PC:
2362878cc677SRichard Henderson         case DYNAMIC_PC_LOOKUP:
2363878cc677SRichard Henderson             dc->pc = dc->npc;
2364444d8b30SRichard Henderson             tcg_gen_mov_tl(cpu_pc, cpu_npc);
2365444d8b30SRichard Henderson             tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
2366878cc677SRichard Henderson             break;
23674a8d145dSRichard Henderson 
2368878cc677SRichard Henderson         case JUMP_PC:
2369878cc677SRichard Henderson             /* we can do a static jump */
23704a8d145dSRichard Henderson             l1 = gen_new_label();
2371533f042fSRichard Henderson             tcg_gen_brcondi_tl(dc->jump.cond, dc->jump.c1, dc->jump.c2, l1);
23724a8d145dSRichard Henderson 
23734a8d145dSRichard Henderson             /* jump not taken */
23744a8d145dSRichard Henderson             gen_goto_tb(dc, 1, dc->jump_pc[1], dc->jump_pc[1] + 4);
23754a8d145dSRichard Henderson 
23764a8d145dSRichard Henderson             /* jump taken */
23774a8d145dSRichard Henderson             gen_set_label(l1);
23784a8d145dSRichard Henderson             gen_goto_tb(dc, 0, dc->jump_pc[0], dc->jump_pc[0] + 4);
23794a8d145dSRichard Henderson 
2380878cc677SRichard Henderson             dc->base.is_jmp = DISAS_NORETURN;
2381878cc677SRichard Henderson             break;
23824a8d145dSRichard Henderson 
2383878cc677SRichard Henderson         default:
2384878cc677SRichard Henderson             g_assert_not_reached();
2385878cc677SRichard Henderson         }
2386878cc677SRichard Henderson     } else {
2387878cc677SRichard Henderson         dc->pc = dc->npc;
2388878cc677SRichard Henderson         dc->npc = dc->npc + 4;
2389878cc677SRichard Henderson     }
2390878cc677SRichard Henderson     return true;
2391878cc677SRichard Henderson }
2392878cc677SRichard Henderson 
23936d2a0768SRichard Henderson /*
23946d2a0768SRichard Henderson  * Major opcodes 00 and 01 -- branches, call, and sethi
23956d2a0768SRichard Henderson  */
23966d2a0768SRichard Henderson 
23979d4e2bc7SRichard Henderson static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
23983951b7a8SRichard Henderson                               bool annul, int disp)
2399276567aaSRichard Henderson {
24003951b7a8SRichard Henderson     target_ulong dest = address_mask_i(dc, dc->pc + disp * 4);
2401c76c8045SRichard Henderson     target_ulong npc;
2402c76c8045SRichard Henderson 
240389527e3aSRichard Henderson     finishing_insn(dc);
240489527e3aSRichard Henderson 
24052d9bb237SRichard Henderson     if (cmp->cond == TCG_COND_ALWAYS) {
24062d9bb237SRichard Henderson         if (annul) {
24072d9bb237SRichard Henderson             dc->pc = dest;
24082d9bb237SRichard Henderson             dc->npc = dest + 4;
24092d9bb237SRichard Henderson         } else {
24102d9bb237SRichard Henderson             gen_mov_pc_npc(dc);
24112d9bb237SRichard Henderson             dc->npc = dest;
24122d9bb237SRichard Henderson         }
24132d9bb237SRichard Henderson         return true;
24142d9bb237SRichard Henderson     }
24152d9bb237SRichard Henderson 
24162d9bb237SRichard Henderson     if (cmp->cond == TCG_COND_NEVER) {
24172d9bb237SRichard Henderson         npc = dc->npc;
24182d9bb237SRichard Henderson         if (npc & 3) {
24192d9bb237SRichard Henderson             gen_mov_pc_npc(dc);
24202d9bb237SRichard Henderson             if (annul) {
24212d9bb237SRichard Henderson                 tcg_gen_addi_tl(cpu_pc, cpu_pc, 4);
24222d9bb237SRichard Henderson             }
24232d9bb237SRichard Henderson             tcg_gen_addi_tl(cpu_npc, cpu_pc, 4);
24242d9bb237SRichard Henderson         } else {
24252d9bb237SRichard Henderson             dc->pc = npc + (annul ? 4 : 0);
24262d9bb237SRichard Henderson             dc->npc = dc->pc + 4;
24272d9bb237SRichard Henderson         }
24282d9bb237SRichard Henderson         return true;
24292d9bb237SRichard Henderson     }
24302d9bb237SRichard Henderson 
2431c76c8045SRichard Henderson     flush_cond(dc);
2432c76c8045SRichard Henderson     npc = dc->npc;
24336b3e4cc6SRichard Henderson 
2434276567aaSRichard Henderson     if (annul) {
24356b3e4cc6SRichard Henderson         TCGLabel *l1 = gen_new_label();
24366b3e4cc6SRichard Henderson 
2437c8507ebfSRichard Henderson         tcg_gen_brcondi_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
24386b3e4cc6SRichard Henderson         gen_goto_tb(dc, 0, npc, dest);
24396b3e4cc6SRichard Henderson         gen_set_label(l1);
24406b3e4cc6SRichard Henderson         gen_goto_tb(dc, 1, npc + 4, npc + 8);
24416b3e4cc6SRichard Henderson 
24426b3e4cc6SRichard Henderson         dc->base.is_jmp = DISAS_NORETURN;
2443276567aaSRichard Henderson     } else {
24446b3e4cc6SRichard Henderson         if (npc & 3) {
24456b3e4cc6SRichard Henderson             switch (npc) {
24466b3e4cc6SRichard Henderson             case DYNAMIC_PC:
24476b3e4cc6SRichard Henderson             case DYNAMIC_PC_LOOKUP:
24486b3e4cc6SRichard Henderson                 tcg_gen_mov_tl(cpu_pc, cpu_npc);
24496b3e4cc6SRichard Henderson                 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
24509d4e2bc7SRichard Henderson                 tcg_gen_movcond_tl(cmp->cond, cpu_npc,
2451c8507ebfSRichard Henderson                                    cmp->c1, tcg_constant_tl(cmp->c2),
24526b3e4cc6SRichard Henderson                                    tcg_constant_tl(dest), cpu_npc);
24536b3e4cc6SRichard Henderson                 dc->pc = npc;
24546b3e4cc6SRichard Henderson                 break;
24556b3e4cc6SRichard Henderson             default:
24566b3e4cc6SRichard Henderson                 g_assert_not_reached();
24576b3e4cc6SRichard Henderson             }
24586b3e4cc6SRichard Henderson         } else {
24596b3e4cc6SRichard Henderson             dc->pc = npc;
2460533f042fSRichard Henderson             dc->npc = JUMP_PC;
2461533f042fSRichard Henderson             dc->jump = *cmp;
24626b3e4cc6SRichard Henderson             dc->jump_pc[0] = dest;
24636b3e4cc6SRichard Henderson             dc->jump_pc[1] = npc + 4;
2464dd7dbfccSRichard Henderson 
2465dd7dbfccSRichard Henderson             /* The condition for cpu_cond is always NE -- normalize. */
2466dd7dbfccSRichard Henderson             if (cmp->cond == TCG_COND_NE) {
2467c8507ebfSRichard Henderson                 tcg_gen_xori_tl(cpu_cond, cmp->c1, cmp->c2);
24689d4e2bc7SRichard Henderson             } else {
2469c8507ebfSRichard Henderson                 tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
24709d4e2bc7SRichard Henderson             }
247189527e3aSRichard Henderson             dc->cpu_cond_live = true;
24726b3e4cc6SRichard Henderson         }
2473276567aaSRichard Henderson     }
2474276567aaSRichard Henderson     return true;
2475276567aaSRichard Henderson }
2476276567aaSRichard Henderson 
2477af25071cSRichard Henderson static bool raise_priv(DisasContext *dc)
2478af25071cSRichard Henderson {
2479af25071cSRichard Henderson     gen_exception(dc, TT_PRIV_INSN);
2480af25071cSRichard Henderson     return true;
2481af25071cSRichard Henderson }
2482af25071cSRichard Henderson 
248306c060d9SRichard Henderson static bool raise_unimpfpop(DisasContext *dc)
248406c060d9SRichard Henderson {
248506c060d9SRichard Henderson     gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
248606c060d9SRichard Henderson     return true;
248706c060d9SRichard Henderson }
248806c060d9SRichard Henderson 
248906c060d9SRichard Henderson static bool gen_trap_float128(DisasContext *dc)
249006c060d9SRichard Henderson {
249106c060d9SRichard Henderson     if (dc->def->features & CPU_FEATURE_FLOAT128) {
249206c060d9SRichard Henderson         return false;
249306c060d9SRichard Henderson     }
249406c060d9SRichard Henderson     return raise_unimpfpop(dc);
249506c060d9SRichard Henderson }
249606c060d9SRichard Henderson 
2497276567aaSRichard Henderson static bool do_bpcc(DisasContext *dc, arg_bcc *a)
2498276567aaSRichard Henderson {
24991ea9c62aSRichard Henderson     DisasCompare cmp;
2500276567aaSRichard Henderson 
25011ea9c62aSRichard Henderson     gen_compare(&cmp, a->cc, a->cond, dc);
25023951b7a8SRichard Henderson     return advance_jump_cond(dc, &cmp, a->a, a->i);
2503276567aaSRichard Henderson }
2504276567aaSRichard Henderson 
2505276567aaSRichard Henderson TRANS(Bicc, ALL, do_bpcc, a)
2506276567aaSRichard Henderson TRANS(BPcc,  64, do_bpcc, a)
2507276567aaSRichard Henderson 
250845196ea4SRichard Henderson static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
250945196ea4SRichard Henderson {
2510d5471936SRichard Henderson     DisasCompare cmp;
251145196ea4SRichard Henderson 
251245196ea4SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
251345196ea4SRichard Henderson         return true;
251445196ea4SRichard Henderson     }
2515d5471936SRichard Henderson     gen_fcompare(&cmp, a->cc, a->cond);
25163951b7a8SRichard Henderson     return advance_jump_cond(dc, &cmp, a->a, a->i);
251745196ea4SRichard Henderson }
251845196ea4SRichard Henderson 
251945196ea4SRichard Henderson TRANS(FBPfcc,  64, do_fbpfcc, a)
252045196ea4SRichard Henderson TRANS(FBfcc,  ALL, do_fbpfcc, a)
252145196ea4SRichard Henderson 
2522ab9ffe98SRichard Henderson static bool trans_BPr(DisasContext *dc, arg_BPr *a)
2523ab9ffe98SRichard Henderson {
2524ab9ffe98SRichard Henderson     DisasCompare cmp;
2525ab9ffe98SRichard Henderson 
2526ab9ffe98SRichard Henderson     if (!avail_64(dc)) {
2527ab9ffe98SRichard Henderson         return false;
2528ab9ffe98SRichard Henderson     }
25292c4f56c9SRichard Henderson     if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
2530ab9ffe98SRichard Henderson         return false;
2531ab9ffe98SRichard Henderson     }
25323951b7a8SRichard Henderson     return advance_jump_cond(dc, &cmp, a->a, a->i);
2533ab9ffe98SRichard Henderson }
2534ab9ffe98SRichard Henderson 
253523ada1b1SRichard Henderson static bool trans_CALL(DisasContext *dc, arg_CALL *a)
253623ada1b1SRichard Henderson {
253723ada1b1SRichard Henderson     target_long target = address_mask_i(dc, dc->pc + a->i * 4);
253823ada1b1SRichard Henderson 
253923ada1b1SRichard Henderson     gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc));
254023ada1b1SRichard Henderson     gen_mov_pc_npc(dc);
254123ada1b1SRichard Henderson     dc->npc = target;
254223ada1b1SRichard Henderson     return true;
254323ada1b1SRichard Henderson }
254423ada1b1SRichard Henderson 
254545196ea4SRichard Henderson static bool trans_NCP(DisasContext *dc, arg_NCP *a)
254645196ea4SRichard Henderson {
254745196ea4SRichard Henderson     /*
254845196ea4SRichard Henderson      * For sparc32, always generate the no-coprocessor exception.
254945196ea4SRichard Henderson      * For sparc64, always generate illegal instruction.
255045196ea4SRichard Henderson      */
255145196ea4SRichard Henderson #ifdef TARGET_SPARC64
255245196ea4SRichard Henderson     return false;
255345196ea4SRichard Henderson #else
255445196ea4SRichard Henderson     gen_exception(dc, TT_NCP_INSN);
255545196ea4SRichard Henderson     return true;
255645196ea4SRichard Henderson #endif
255745196ea4SRichard Henderson }
255845196ea4SRichard Henderson 
25596d2a0768SRichard Henderson static bool trans_SETHI(DisasContext *dc, arg_SETHI *a)
25606d2a0768SRichard Henderson {
25616d2a0768SRichard Henderson     /* Special-case %g0 because that's the canonical nop.  */
25626d2a0768SRichard Henderson     if (a->rd) {
25636d2a0768SRichard Henderson         gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10));
25646d2a0768SRichard Henderson     }
25656d2a0768SRichard Henderson     return advance_pc(dc);
25666d2a0768SRichard Henderson }
25676d2a0768SRichard Henderson 
25680faef01bSRichard Henderson /*
25690faef01bSRichard Henderson  * Major Opcode 10 -- integer, floating-point, vis, and system insns.
25700faef01bSRichard Henderson  */
25710faef01bSRichard Henderson 
257230376636SRichard Henderson static bool do_tcc(DisasContext *dc, int cond, int cc,
257330376636SRichard Henderson                    int rs1, bool imm, int rs2_or_imm)
257430376636SRichard Henderson {
257530376636SRichard Henderson     int mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
257630376636SRichard Henderson                 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
257730376636SRichard Henderson     DisasCompare cmp;
257830376636SRichard Henderson     TCGLabel *lab;
257930376636SRichard Henderson     TCGv_i32 trap;
258030376636SRichard Henderson 
258130376636SRichard Henderson     /* Trap never.  */
258230376636SRichard Henderson     if (cond == 0) {
258330376636SRichard Henderson         return advance_pc(dc);
258430376636SRichard Henderson     }
258530376636SRichard Henderson 
258630376636SRichard Henderson     /*
258730376636SRichard Henderson      * Immediate traps are the most common case.  Since this value is
258830376636SRichard Henderson      * live across the branch, it really pays to evaluate the constant.
258930376636SRichard Henderson      */
259030376636SRichard Henderson     if (rs1 == 0 && (imm || rs2_or_imm == 0)) {
259130376636SRichard Henderson         trap = tcg_constant_i32((rs2_or_imm & mask) + TT_TRAP);
259230376636SRichard Henderson     } else {
259330376636SRichard Henderson         trap = tcg_temp_new_i32();
259430376636SRichard Henderson         tcg_gen_trunc_tl_i32(trap, gen_load_gpr(dc, rs1));
259530376636SRichard Henderson         if (imm) {
259630376636SRichard Henderson             tcg_gen_addi_i32(trap, trap, rs2_or_imm);
259730376636SRichard Henderson         } else {
259830376636SRichard Henderson             TCGv_i32 t2 = tcg_temp_new_i32();
259930376636SRichard Henderson             tcg_gen_trunc_tl_i32(t2, gen_load_gpr(dc, rs2_or_imm));
260030376636SRichard Henderson             tcg_gen_add_i32(trap, trap, t2);
260130376636SRichard Henderson         }
260230376636SRichard Henderson         tcg_gen_andi_i32(trap, trap, mask);
260330376636SRichard Henderson         tcg_gen_addi_i32(trap, trap, TT_TRAP);
260430376636SRichard Henderson     }
260530376636SRichard Henderson 
260689527e3aSRichard Henderson     finishing_insn(dc);
260789527e3aSRichard Henderson 
260830376636SRichard Henderson     /* Trap always.  */
260930376636SRichard Henderson     if (cond == 8) {
261030376636SRichard Henderson         save_state(dc);
261130376636SRichard Henderson         gen_helper_raise_exception(tcg_env, trap);
261230376636SRichard Henderson         dc->base.is_jmp = DISAS_NORETURN;
261330376636SRichard Henderson         return true;
261430376636SRichard Henderson     }
261530376636SRichard Henderson 
261630376636SRichard Henderson     /* Conditional trap.  */
261730376636SRichard Henderson     flush_cond(dc);
261830376636SRichard Henderson     lab = delay_exceptionv(dc, trap);
261930376636SRichard Henderson     gen_compare(&cmp, cc, cond, dc);
2620c8507ebfSRichard Henderson     tcg_gen_brcondi_tl(cmp.cond, cmp.c1, cmp.c2, lab);
262130376636SRichard Henderson 
262230376636SRichard Henderson     return advance_pc(dc);
262330376636SRichard Henderson }
262430376636SRichard Henderson 
262530376636SRichard Henderson static bool trans_Tcc_r(DisasContext *dc, arg_Tcc_r *a)
262630376636SRichard Henderson {
262730376636SRichard Henderson     if (avail_32(dc) && a->cc) {
262830376636SRichard Henderson         return false;
262930376636SRichard Henderson     }
263030376636SRichard Henderson     return do_tcc(dc, a->cond, a->cc, a->rs1, false, a->rs2);
263130376636SRichard Henderson }
263230376636SRichard Henderson 
263330376636SRichard Henderson static bool trans_Tcc_i_v7(DisasContext *dc, arg_Tcc_i_v7 *a)
263430376636SRichard Henderson {
263530376636SRichard Henderson     if (avail_64(dc)) {
263630376636SRichard Henderson         return false;
263730376636SRichard Henderson     }
263830376636SRichard Henderson     return do_tcc(dc, a->cond, 0, a->rs1, true, a->i);
263930376636SRichard Henderson }
264030376636SRichard Henderson 
264130376636SRichard Henderson static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tcc_i_v9 *a)
264230376636SRichard Henderson {
264330376636SRichard Henderson     if (avail_32(dc)) {
264430376636SRichard Henderson         return false;
264530376636SRichard Henderson     }
264630376636SRichard Henderson     return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i);
264730376636SRichard Henderson }
264830376636SRichard Henderson 
2649af25071cSRichard Henderson static bool trans_STBAR(DisasContext *dc, arg_STBAR *a)
2650af25071cSRichard Henderson {
2651af25071cSRichard Henderson     tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
2652af25071cSRichard Henderson     return advance_pc(dc);
2653af25071cSRichard Henderson }
2654af25071cSRichard Henderson 
2655af25071cSRichard Henderson static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a)
2656af25071cSRichard Henderson {
2657af25071cSRichard Henderson     if (avail_32(dc)) {
2658af25071cSRichard Henderson         return false;
2659af25071cSRichard Henderson     }
2660af25071cSRichard Henderson     if (a->mmask) {
2661af25071cSRichard Henderson         /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */
2662af25071cSRichard Henderson         tcg_gen_mb(a->mmask | TCG_BAR_SC);
2663af25071cSRichard Henderson     }
2664af25071cSRichard Henderson     if (a->cmask) {
2665af25071cSRichard Henderson         /* For #Sync, etc, end the TB to recognize interrupts. */
2666af25071cSRichard Henderson         dc->base.is_jmp = DISAS_EXIT;
2667af25071cSRichard Henderson     }
2668af25071cSRichard Henderson     return advance_pc(dc);
2669af25071cSRichard Henderson }
2670af25071cSRichard Henderson 
2671af25071cSRichard Henderson static bool do_rd_special(DisasContext *dc, bool priv, int rd,
2672af25071cSRichard Henderson                           TCGv (*func)(DisasContext *, TCGv))
2673af25071cSRichard Henderson {
2674af25071cSRichard Henderson     if (!priv) {
2675af25071cSRichard Henderson         return raise_priv(dc);
2676af25071cSRichard Henderson     }
2677af25071cSRichard Henderson     gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd)));
2678af25071cSRichard Henderson     return advance_pc(dc);
2679af25071cSRichard Henderson }
2680af25071cSRichard Henderson 
2681af25071cSRichard Henderson static TCGv do_rdy(DisasContext *dc, TCGv dst)
2682af25071cSRichard Henderson {
2683af25071cSRichard Henderson     return cpu_y;
2684af25071cSRichard Henderson }
2685af25071cSRichard Henderson 
2686af25071cSRichard Henderson static bool trans_RDY(DisasContext *dc, arg_RDY *a)
2687af25071cSRichard Henderson {
2688af25071cSRichard Henderson     /*
2689af25071cSRichard Henderson      * TODO: Need a feature bit for sparcv8.  In the meantime, treat all
2690af25071cSRichard Henderson      * 32-bit cpus like sparcv7, which ignores the rs1 field.
2691af25071cSRichard Henderson      * This matches after all other ASR, so Leon3 Asr17 is handled first.
2692af25071cSRichard Henderson      */
2693af25071cSRichard Henderson     if (avail_64(dc) && a->rs1 != 0) {
2694af25071cSRichard Henderson         return false;
2695af25071cSRichard Henderson     }
2696af25071cSRichard Henderson     return do_rd_special(dc, true, a->rd, do_rdy);
2697af25071cSRichard Henderson }
2698af25071cSRichard Henderson 
2699af25071cSRichard Henderson static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
2700af25071cSRichard Henderson {
2701af25071cSRichard Henderson     uint32_t val;
2702af25071cSRichard Henderson 
2703af25071cSRichard Henderson     /*
2704af25071cSRichard Henderson      * TODO: There are many more fields to be filled,
2705af25071cSRichard Henderson      * some of which are writable.
2706af25071cSRichard Henderson      */
2707af25071cSRichard Henderson     val = dc->def->nwindows - 1;   /* [4:0] NWIN */
2708af25071cSRichard Henderson     val |= 1 << 8;                 /* [8]   V8   */
2709af25071cSRichard Henderson 
2710af25071cSRichard Henderson     return tcg_constant_tl(val);
2711af25071cSRichard Henderson }
2712af25071cSRichard Henderson 
2713af25071cSRichard Henderson TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
2714af25071cSRichard Henderson 
2715af25071cSRichard Henderson static TCGv do_rdccr(DisasContext *dc, TCGv dst)
2716af25071cSRichard Henderson {
2717af25071cSRichard Henderson     gen_helper_rdccr(dst, tcg_env);
2718af25071cSRichard Henderson     return dst;
2719af25071cSRichard Henderson }
2720af25071cSRichard Henderson 
2721af25071cSRichard Henderson TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
2722af25071cSRichard Henderson 
2723af25071cSRichard Henderson static TCGv do_rdasi(DisasContext *dc, TCGv dst)
2724af25071cSRichard Henderson {
2725af25071cSRichard Henderson #ifdef TARGET_SPARC64
2726af25071cSRichard Henderson     return tcg_constant_tl(dc->asi);
2727af25071cSRichard Henderson #else
2728af25071cSRichard Henderson     qemu_build_not_reached();
2729af25071cSRichard Henderson #endif
2730af25071cSRichard Henderson }
2731af25071cSRichard Henderson 
2732af25071cSRichard Henderson TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi)
2733af25071cSRichard Henderson 
2734af25071cSRichard Henderson static TCGv do_rdtick(DisasContext *dc, TCGv dst)
2735af25071cSRichard Henderson {
2736af25071cSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
2737af25071cSRichard Henderson 
2738af25071cSRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
2739af25071cSRichard Henderson     if (translator_io_start(&dc->base)) {
2740af25071cSRichard Henderson         dc->base.is_jmp = DISAS_EXIT;
2741af25071cSRichard Henderson     }
2742af25071cSRichard Henderson     gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
2743af25071cSRichard Henderson                               tcg_constant_i32(dc->mem_idx));
2744af25071cSRichard Henderson     return dst;
2745af25071cSRichard Henderson }
2746af25071cSRichard Henderson 
2747af25071cSRichard Henderson /* TODO: non-priv access only allowed when enabled. */
2748af25071cSRichard Henderson TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick)
2749af25071cSRichard Henderson 
2750af25071cSRichard Henderson static TCGv do_rdpc(DisasContext *dc, TCGv dst)
2751af25071cSRichard Henderson {
2752af25071cSRichard Henderson     return tcg_constant_tl(address_mask_i(dc, dc->pc));
2753af25071cSRichard Henderson }
2754af25071cSRichard Henderson 
2755af25071cSRichard Henderson TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc)
2756af25071cSRichard Henderson 
2757af25071cSRichard Henderson static TCGv do_rdfprs(DisasContext *dc, TCGv dst)
2758af25071cSRichard Henderson {
2759af25071cSRichard Henderson     tcg_gen_ext_i32_tl(dst, cpu_fprs);
2760af25071cSRichard Henderson     return dst;
2761af25071cSRichard Henderson }
2762af25071cSRichard Henderson 
2763af25071cSRichard Henderson TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs)
2764af25071cSRichard Henderson 
2765af25071cSRichard Henderson static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
2766af25071cSRichard Henderson {
2767af25071cSRichard Henderson     gen_trap_ifnofpu(dc);
2768af25071cSRichard Henderson     return cpu_gsr;
2769af25071cSRichard Henderson }
2770af25071cSRichard Henderson 
2771af25071cSRichard Henderson TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr)
2772af25071cSRichard Henderson 
2773af25071cSRichard Henderson static TCGv do_rdsoftint(DisasContext *dc, TCGv dst)
2774af25071cSRichard Henderson {
2775af25071cSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(softint));
2776af25071cSRichard Henderson     return dst;
2777af25071cSRichard Henderson }
2778af25071cSRichard Henderson 
2779af25071cSRichard Henderson TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint)
2780af25071cSRichard Henderson 
2781af25071cSRichard Henderson static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst)
2782af25071cSRichard Henderson {
2783577efa45SRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(tick_cmpr));
2784577efa45SRichard Henderson     return dst;
2785af25071cSRichard Henderson }
2786af25071cSRichard Henderson 
2787af25071cSRichard Henderson /* TODO: non-priv access only allowed when enabled. */
2788af25071cSRichard Henderson TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr)
2789af25071cSRichard Henderson 
2790af25071cSRichard Henderson static TCGv do_rdstick(DisasContext *dc, TCGv dst)
2791af25071cSRichard Henderson {
2792af25071cSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
2793af25071cSRichard Henderson 
2794af25071cSRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
2795af25071cSRichard Henderson     if (translator_io_start(&dc->base)) {
2796af25071cSRichard Henderson         dc->base.is_jmp = DISAS_EXIT;
2797af25071cSRichard Henderson     }
2798af25071cSRichard Henderson     gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
2799af25071cSRichard Henderson                               tcg_constant_i32(dc->mem_idx));
2800af25071cSRichard Henderson     return dst;
2801af25071cSRichard Henderson }
2802af25071cSRichard Henderson 
2803af25071cSRichard Henderson /* TODO: non-priv access only allowed when enabled. */
2804af25071cSRichard Henderson TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick)
2805af25071cSRichard Henderson 
2806af25071cSRichard Henderson static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst)
2807af25071cSRichard Henderson {
2808577efa45SRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(stick_cmpr));
2809577efa45SRichard Henderson     return dst;
2810af25071cSRichard Henderson }
2811af25071cSRichard Henderson 
2812af25071cSRichard Henderson /* TODO: supervisor access only allowed when enabled by hypervisor. */
2813af25071cSRichard Henderson TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_cmpr)
2814af25071cSRichard Henderson 
2815af25071cSRichard Henderson /*
2816af25071cSRichard Henderson  * UltraSPARC-T1 Strand status.
2817af25071cSRichard Henderson  * HYPV check maybe not enough, UA2005 & UA2007 describe
2818af25071cSRichard Henderson  * this ASR as impl. dep
2819af25071cSRichard Henderson  */
2820af25071cSRichard Henderson static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst)
2821af25071cSRichard Henderson {
2822af25071cSRichard Henderson     return tcg_constant_tl(1);
2823af25071cSRichard Henderson }
2824af25071cSRichard Henderson 
2825af25071cSRichard Henderson TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
2826af25071cSRichard Henderson 
2827668bb9b7SRichard Henderson static TCGv do_rdpsr(DisasContext *dc, TCGv dst)
2828668bb9b7SRichard Henderson {
2829668bb9b7SRichard Henderson     gen_helper_rdpsr(dst, tcg_env);
2830668bb9b7SRichard Henderson     return dst;
2831668bb9b7SRichard Henderson }
2832668bb9b7SRichard Henderson 
2833668bb9b7SRichard Henderson TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr)
2834668bb9b7SRichard Henderson 
2835668bb9b7SRichard Henderson static TCGv do_rdhpstate(DisasContext *dc, TCGv dst)
2836668bb9b7SRichard Henderson {
2837668bb9b7SRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hpstate));
2838668bb9b7SRichard Henderson     return dst;
2839668bb9b7SRichard Henderson }
2840668bb9b7SRichard Henderson 
2841668bb9b7SRichard Henderson TRANS(RDHPR_hpstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhpstate)
2842668bb9b7SRichard Henderson 
2843668bb9b7SRichard Henderson static TCGv do_rdhtstate(DisasContext *dc, TCGv dst)
2844668bb9b7SRichard Henderson {
2845668bb9b7SRichard Henderson     TCGv_i32 tl = tcg_temp_new_i32();
2846668bb9b7SRichard Henderson     TCGv_ptr tp = tcg_temp_new_ptr();
2847668bb9b7SRichard Henderson 
2848668bb9b7SRichard Henderson     tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
2849668bb9b7SRichard Henderson     tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
2850668bb9b7SRichard Henderson     tcg_gen_shli_i32(tl, tl, 3);
2851668bb9b7SRichard Henderson     tcg_gen_ext_i32_ptr(tp, tl);
2852668bb9b7SRichard Henderson     tcg_gen_add_ptr(tp, tp, tcg_env);
2853668bb9b7SRichard Henderson 
2854668bb9b7SRichard Henderson     tcg_gen_ld_tl(dst, tp, env64_field_offsetof(htstate));
2855668bb9b7SRichard Henderson     return dst;
2856668bb9b7SRichard Henderson }
2857668bb9b7SRichard Henderson 
2858668bb9b7SRichard Henderson TRANS(RDHPR_htstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtstate)
2859668bb9b7SRichard Henderson 
2860668bb9b7SRichard Henderson static TCGv do_rdhintp(DisasContext *dc, TCGv dst)
2861668bb9b7SRichard Henderson {
28622da789deSRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hintp));
28632da789deSRichard Henderson     return dst;
2864668bb9b7SRichard Henderson }
2865668bb9b7SRichard Henderson 
2866668bb9b7SRichard Henderson TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp)
2867668bb9b7SRichard Henderson 
2868668bb9b7SRichard Henderson static TCGv do_rdhtba(DisasContext *dc, TCGv dst)
2869668bb9b7SRichard Henderson {
28702da789deSRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(htba));
28712da789deSRichard Henderson     return dst;
2872668bb9b7SRichard Henderson }
2873668bb9b7SRichard Henderson 
2874668bb9b7SRichard Henderson TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba)
2875668bb9b7SRichard Henderson 
2876668bb9b7SRichard Henderson static TCGv do_rdhver(DisasContext *dc, TCGv dst)
2877668bb9b7SRichard Henderson {
28782da789deSRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hver));
28792da789deSRichard Henderson     return dst;
2880668bb9b7SRichard Henderson }
2881668bb9b7SRichard Henderson 
2882668bb9b7SRichard Henderson TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver)
2883668bb9b7SRichard Henderson 
2884668bb9b7SRichard Henderson static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst)
2885668bb9b7SRichard Henderson {
2886577efa45SRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hstick_cmpr));
2887577efa45SRichard Henderson     return dst;
2888668bb9b7SRichard Henderson }
2889668bb9b7SRichard Henderson 
2890668bb9b7SRichard Henderson TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
2891668bb9b7SRichard Henderson       do_rdhstick_cmpr)
2892668bb9b7SRichard Henderson 
28935d617bfbSRichard Henderson static TCGv do_rdwim(DisasContext *dc, TCGv dst)
28945d617bfbSRichard Henderson {
2895cd6269f7SRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim));
2896cd6269f7SRichard Henderson     return dst;
28975d617bfbSRichard Henderson }
28985d617bfbSRichard Henderson 
28995d617bfbSRichard Henderson TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim)
29005d617bfbSRichard Henderson 
29015d617bfbSRichard Henderson static TCGv do_rdtpc(DisasContext *dc, TCGv dst)
29025d617bfbSRichard Henderson {
29035d617bfbSRichard Henderson #ifdef TARGET_SPARC64
29045d617bfbSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
29055d617bfbSRichard Henderson 
29065d617bfbSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
29075d617bfbSRichard Henderson     tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tpc));
29085d617bfbSRichard Henderson     return dst;
29095d617bfbSRichard Henderson #else
29105d617bfbSRichard Henderson     qemu_build_not_reached();
29115d617bfbSRichard Henderson #endif
29125d617bfbSRichard Henderson }
29135d617bfbSRichard Henderson 
29145d617bfbSRichard Henderson TRANS(RDPR_tpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtpc)
29155d617bfbSRichard Henderson 
29165d617bfbSRichard Henderson static TCGv do_rdtnpc(DisasContext *dc, TCGv dst)
29175d617bfbSRichard Henderson {
29185d617bfbSRichard Henderson #ifdef TARGET_SPARC64
29195d617bfbSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
29205d617bfbSRichard Henderson 
29215d617bfbSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
29225d617bfbSRichard Henderson     tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tnpc));
29235d617bfbSRichard Henderson     return dst;
29245d617bfbSRichard Henderson #else
29255d617bfbSRichard Henderson     qemu_build_not_reached();
29265d617bfbSRichard Henderson #endif
29275d617bfbSRichard Henderson }
29285d617bfbSRichard Henderson 
29295d617bfbSRichard Henderson TRANS(RDPR_tnpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtnpc)
29305d617bfbSRichard Henderson 
29315d617bfbSRichard Henderson static TCGv do_rdtstate(DisasContext *dc, TCGv dst)
29325d617bfbSRichard Henderson {
29335d617bfbSRichard Henderson #ifdef TARGET_SPARC64
29345d617bfbSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
29355d617bfbSRichard Henderson 
29365d617bfbSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
29375d617bfbSRichard Henderson     tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tstate));
29385d617bfbSRichard Henderson     return dst;
29395d617bfbSRichard Henderson #else
29405d617bfbSRichard Henderson     qemu_build_not_reached();
29415d617bfbSRichard Henderson #endif
29425d617bfbSRichard Henderson }
29435d617bfbSRichard Henderson 
29445d617bfbSRichard Henderson TRANS(RDPR_tstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdtstate)
29455d617bfbSRichard Henderson 
29465d617bfbSRichard Henderson static TCGv do_rdtt(DisasContext *dc, TCGv dst)
29475d617bfbSRichard Henderson {
29485d617bfbSRichard Henderson #ifdef TARGET_SPARC64
29495d617bfbSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
29505d617bfbSRichard Henderson 
29515d617bfbSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
29525d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, r_tsptr, offsetof(trap_state, tt));
29535d617bfbSRichard Henderson     return dst;
29545d617bfbSRichard Henderson #else
29555d617bfbSRichard Henderson     qemu_build_not_reached();
29565d617bfbSRichard Henderson #endif
29575d617bfbSRichard Henderson }
29585d617bfbSRichard Henderson 
29595d617bfbSRichard Henderson TRANS(RDPR_tt, 64, do_rd_special, supervisor(dc), a->rd, do_rdtt)
29605d617bfbSRichard Henderson TRANS(RDPR_tick, 64, do_rd_special, supervisor(dc), a->rd, do_rdtick)
29615d617bfbSRichard Henderson 
29625d617bfbSRichard Henderson static TCGv do_rdtba(DisasContext *dc, TCGv dst)
29635d617bfbSRichard Henderson {
29645d617bfbSRichard Henderson     return cpu_tbr;
29655d617bfbSRichard Henderson }
29665d617bfbSRichard Henderson 
2967e8325dc0SRichard Henderson TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba)
29685d617bfbSRichard Henderson TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba)
29695d617bfbSRichard Henderson 
29705d617bfbSRichard Henderson static TCGv do_rdpstate(DisasContext *dc, TCGv dst)
29715d617bfbSRichard Henderson {
29725d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(pstate));
29735d617bfbSRichard Henderson     return dst;
29745d617bfbSRichard Henderson }
29755d617bfbSRichard Henderson 
29765d617bfbSRichard Henderson TRANS(RDPR_pstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdpstate)
29775d617bfbSRichard Henderson 
29785d617bfbSRichard Henderson static TCGv do_rdtl(DisasContext *dc, TCGv dst)
29795d617bfbSRichard Henderson {
29805d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(tl));
29815d617bfbSRichard Henderson     return dst;
29825d617bfbSRichard Henderson }
29835d617bfbSRichard Henderson 
29845d617bfbSRichard Henderson TRANS(RDPR_tl, 64, do_rd_special, supervisor(dc), a->rd, do_rdtl)
29855d617bfbSRichard Henderson 
29865d617bfbSRichard Henderson static TCGv do_rdpil(DisasContext *dc, TCGv dst)
29875d617bfbSRichard Henderson {
29885d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env_field_offsetof(psrpil));
29895d617bfbSRichard Henderson     return dst;
29905d617bfbSRichard Henderson }
29915d617bfbSRichard Henderson 
29925d617bfbSRichard Henderson TRANS(RDPR_pil, 64, do_rd_special, supervisor(dc), a->rd, do_rdpil)
29935d617bfbSRichard Henderson 
29945d617bfbSRichard Henderson static TCGv do_rdcwp(DisasContext *dc, TCGv dst)
29955d617bfbSRichard Henderson {
29965d617bfbSRichard Henderson     gen_helper_rdcwp(dst, tcg_env);
29975d617bfbSRichard Henderson     return dst;
29985d617bfbSRichard Henderson }
29995d617bfbSRichard Henderson 
30005d617bfbSRichard Henderson TRANS(RDPR_cwp, 64, do_rd_special, supervisor(dc), a->rd, do_rdcwp)
30015d617bfbSRichard Henderson 
30025d617bfbSRichard Henderson static TCGv do_rdcansave(DisasContext *dc, TCGv dst)
30035d617bfbSRichard Henderson {
30045d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cansave));
30055d617bfbSRichard Henderson     return dst;
30065d617bfbSRichard Henderson }
30075d617bfbSRichard Henderson 
30085d617bfbSRichard Henderson TRANS(RDPR_cansave, 64, do_rd_special, supervisor(dc), a->rd, do_rdcansave)
30095d617bfbSRichard Henderson 
30105d617bfbSRichard Henderson static TCGv do_rdcanrestore(DisasContext *dc, TCGv dst)
30115d617bfbSRichard Henderson {
30125d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(canrestore));
30135d617bfbSRichard Henderson     return dst;
30145d617bfbSRichard Henderson }
30155d617bfbSRichard Henderson 
30165d617bfbSRichard Henderson TRANS(RDPR_canrestore, 64, do_rd_special, supervisor(dc), a->rd,
30175d617bfbSRichard Henderson       do_rdcanrestore)
30185d617bfbSRichard Henderson 
30195d617bfbSRichard Henderson static TCGv do_rdcleanwin(DisasContext *dc, TCGv dst)
30205d617bfbSRichard Henderson {
30215d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cleanwin));
30225d617bfbSRichard Henderson     return dst;
30235d617bfbSRichard Henderson }
30245d617bfbSRichard Henderson 
30255d617bfbSRichard Henderson TRANS(RDPR_cleanwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdcleanwin)
30265d617bfbSRichard Henderson 
30275d617bfbSRichard Henderson static TCGv do_rdotherwin(DisasContext *dc, TCGv dst)
30285d617bfbSRichard Henderson {
30295d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(otherwin));
30305d617bfbSRichard Henderson     return dst;
30315d617bfbSRichard Henderson }
30325d617bfbSRichard Henderson 
30335d617bfbSRichard Henderson TRANS(RDPR_otherwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdotherwin)
30345d617bfbSRichard Henderson 
30355d617bfbSRichard Henderson static TCGv do_rdwstate(DisasContext *dc, TCGv dst)
30365d617bfbSRichard Henderson {
30375d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(wstate));
30385d617bfbSRichard Henderson     return dst;
30395d617bfbSRichard Henderson }
30405d617bfbSRichard Henderson 
30415d617bfbSRichard Henderson TRANS(RDPR_wstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdwstate)
30425d617bfbSRichard Henderson 
30435d617bfbSRichard Henderson static TCGv do_rdgl(DisasContext *dc, TCGv dst)
30445d617bfbSRichard Henderson {
30455d617bfbSRichard Henderson     tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(gl));
30465d617bfbSRichard Henderson     return dst;
30475d617bfbSRichard Henderson }
30485d617bfbSRichard Henderson 
30495d617bfbSRichard Henderson TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a->rd, do_rdgl)
30505d617bfbSRichard Henderson 
30515d617bfbSRichard Henderson /* UA2005 strand status */
30525d617bfbSRichard Henderson static TCGv do_rdssr(DisasContext *dc, TCGv dst)
30535d617bfbSRichard Henderson {
30542da789deSRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(ssr));
30552da789deSRichard Henderson     return dst;
30565d617bfbSRichard Henderson }
30575d617bfbSRichard Henderson 
30585d617bfbSRichard Henderson TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdssr)
30595d617bfbSRichard Henderson 
30605d617bfbSRichard Henderson static TCGv do_rdver(DisasContext *dc, TCGv dst)
30615d617bfbSRichard Henderson {
30622da789deSRichard Henderson     tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(version));
30632da789deSRichard Henderson     return dst;
30645d617bfbSRichard Henderson }
30655d617bfbSRichard Henderson 
30665d617bfbSRichard Henderson TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver)
30675d617bfbSRichard Henderson 
3068e8325dc0SRichard Henderson static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a)
3069e8325dc0SRichard Henderson {
3070e8325dc0SRichard Henderson     if (avail_64(dc)) {
3071e8325dc0SRichard Henderson         gen_helper_flushw(tcg_env);
3072e8325dc0SRichard Henderson         return advance_pc(dc);
3073e8325dc0SRichard Henderson     }
3074e8325dc0SRichard Henderson     return false;
3075e8325dc0SRichard Henderson }
3076e8325dc0SRichard Henderson 
30770faef01bSRichard Henderson static bool do_wr_special(DisasContext *dc, arg_r_r_ri *a, bool priv,
30780faef01bSRichard Henderson                           void (*func)(DisasContext *, TCGv))
30790faef01bSRichard Henderson {
30800faef01bSRichard Henderson     TCGv src;
30810faef01bSRichard Henderson 
30820faef01bSRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
30830faef01bSRichard Henderson     if (!a->imm && (a->rs2_or_imm & ~0x1f)) {
30840faef01bSRichard Henderson         return false;
30850faef01bSRichard Henderson     }
30860faef01bSRichard Henderson     if (!priv) {
30870faef01bSRichard Henderson         return raise_priv(dc);
30880faef01bSRichard Henderson     }
30890faef01bSRichard Henderson 
30900faef01bSRichard Henderson     if (a->rs1 == 0 && (a->imm || a->rs2_or_imm == 0)) {
30910faef01bSRichard Henderson         src = tcg_constant_tl(a->rs2_or_imm);
30920faef01bSRichard Henderson     } else {
30930faef01bSRichard Henderson         TCGv src1 = gen_load_gpr(dc, a->rs1);
30940faef01bSRichard Henderson         if (a->rs2_or_imm == 0) {
30950faef01bSRichard Henderson             src = src1;
30960faef01bSRichard Henderson         } else {
30970faef01bSRichard Henderson             src = tcg_temp_new();
30980faef01bSRichard Henderson             if (a->imm) {
30990faef01bSRichard Henderson                 tcg_gen_xori_tl(src, src1, a->rs2_or_imm);
31000faef01bSRichard Henderson             } else {
31010faef01bSRichard Henderson                 tcg_gen_xor_tl(src, src1, gen_load_gpr(dc, a->rs2_or_imm));
31020faef01bSRichard Henderson             }
31030faef01bSRichard Henderson         }
31040faef01bSRichard Henderson     }
31050faef01bSRichard Henderson     func(dc, src);
31060faef01bSRichard Henderson     return advance_pc(dc);
31070faef01bSRichard Henderson }
31080faef01bSRichard Henderson 
31090faef01bSRichard Henderson static void do_wry(DisasContext *dc, TCGv src)
31100faef01bSRichard Henderson {
31110faef01bSRichard Henderson     tcg_gen_ext32u_tl(cpu_y, src);
31120faef01bSRichard Henderson }
31130faef01bSRichard Henderson 
31140faef01bSRichard Henderson TRANS(WRY, ALL, do_wr_special, a, true, do_wry)
31150faef01bSRichard Henderson 
31160faef01bSRichard Henderson static void do_wrccr(DisasContext *dc, TCGv src)
31170faef01bSRichard Henderson {
31180faef01bSRichard Henderson     gen_helper_wrccr(tcg_env, src);
31190faef01bSRichard Henderson }
31200faef01bSRichard Henderson 
31210faef01bSRichard Henderson TRANS(WRCCR, 64, do_wr_special, a, true, do_wrccr)
31220faef01bSRichard Henderson 
31230faef01bSRichard Henderson static void do_wrasi(DisasContext *dc, TCGv src)
31240faef01bSRichard Henderson {
31250faef01bSRichard Henderson     TCGv tmp = tcg_temp_new();
31260faef01bSRichard Henderson 
31270faef01bSRichard Henderson     tcg_gen_ext8u_tl(tmp, src);
31280faef01bSRichard Henderson     tcg_gen_st32_tl(tmp, tcg_env, env64_field_offsetof(asi));
31290faef01bSRichard Henderson     /* End TB to notice changed ASI. */
31300faef01bSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
31310faef01bSRichard Henderson }
31320faef01bSRichard Henderson 
31330faef01bSRichard Henderson TRANS(WRASI, 64, do_wr_special, a, true, do_wrasi)
31340faef01bSRichard Henderson 
31350faef01bSRichard Henderson static void do_wrfprs(DisasContext *dc, TCGv src)
31360faef01bSRichard Henderson {
31370faef01bSRichard Henderson #ifdef TARGET_SPARC64
31380faef01bSRichard Henderson     tcg_gen_trunc_tl_i32(cpu_fprs, src);
31390faef01bSRichard Henderson     dc->fprs_dirty = 0;
31400faef01bSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
31410faef01bSRichard Henderson #else
31420faef01bSRichard Henderson     qemu_build_not_reached();
31430faef01bSRichard Henderson #endif
31440faef01bSRichard Henderson }
31450faef01bSRichard Henderson 
31460faef01bSRichard Henderson TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
31470faef01bSRichard Henderson 
31480faef01bSRichard Henderson static void do_wrgsr(DisasContext *dc, TCGv src)
31490faef01bSRichard Henderson {
31500faef01bSRichard Henderson     gen_trap_ifnofpu(dc);
31510faef01bSRichard Henderson     tcg_gen_mov_tl(cpu_gsr, src);
31520faef01bSRichard Henderson }
31530faef01bSRichard Henderson 
31540faef01bSRichard Henderson TRANS(WRGSR, 64, do_wr_special, a, true, do_wrgsr)
31550faef01bSRichard Henderson 
31560faef01bSRichard Henderson static void do_wrsoftint_set(DisasContext *dc, TCGv src)
31570faef01bSRichard Henderson {
31580faef01bSRichard Henderson     gen_helper_set_softint(tcg_env, src);
31590faef01bSRichard Henderson }
31600faef01bSRichard Henderson 
31610faef01bSRichard Henderson TRANS(WRSOFTINT_SET, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_set)
31620faef01bSRichard Henderson 
31630faef01bSRichard Henderson static void do_wrsoftint_clr(DisasContext *dc, TCGv src)
31640faef01bSRichard Henderson {
31650faef01bSRichard Henderson     gen_helper_clear_softint(tcg_env, src);
31660faef01bSRichard Henderson }
31670faef01bSRichard Henderson 
31680faef01bSRichard Henderson TRANS(WRSOFTINT_CLR, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_clr)
31690faef01bSRichard Henderson 
31700faef01bSRichard Henderson static void do_wrsoftint(DisasContext *dc, TCGv src)
31710faef01bSRichard Henderson {
31720faef01bSRichard Henderson     gen_helper_write_softint(tcg_env, src);
31730faef01bSRichard Henderson }
31740faef01bSRichard Henderson 
31750faef01bSRichard Henderson TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(dc), do_wrsoftint)
31760faef01bSRichard Henderson 
31770faef01bSRichard Henderson static void do_wrtick_cmpr(DisasContext *dc, TCGv src)
31780faef01bSRichard Henderson {
31790faef01bSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
31800faef01bSRichard Henderson 
3181577efa45SRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(tick_cmpr));
3182577efa45SRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
31830faef01bSRichard Henderson     translator_io_start(&dc->base);
3184577efa45SRichard Henderson     gen_helper_tick_set_limit(r_tickptr, src);
31850faef01bSRichard Henderson     /* End TB to handle timer interrupt */
31860faef01bSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
31870faef01bSRichard Henderson }
31880faef01bSRichard Henderson 
31890faef01bSRichard Henderson TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr)
31900faef01bSRichard Henderson 
31910faef01bSRichard Henderson static void do_wrstick(DisasContext *dc, TCGv src)
31920faef01bSRichard Henderson {
31930faef01bSRichard Henderson #ifdef TARGET_SPARC64
31940faef01bSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
31950faef01bSRichard Henderson 
31960faef01bSRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick));
31970faef01bSRichard Henderson     translator_io_start(&dc->base);
31980faef01bSRichard Henderson     gen_helper_tick_set_count(r_tickptr, src);
31990faef01bSRichard Henderson     /* End TB to handle timer interrupt */
32000faef01bSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
32010faef01bSRichard Henderson #else
32020faef01bSRichard Henderson     qemu_build_not_reached();
32030faef01bSRichard Henderson #endif
32040faef01bSRichard Henderson }
32050faef01bSRichard Henderson 
32060faef01bSRichard Henderson TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc), do_wrstick)
32070faef01bSRichard Henderson 
32080faef01bSRichard Henderson static void do_wrstick_cmpr(DisasContext *dc, TCGv src)
32090faef01bSRichard Henderson {
32100faef01bSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
32110faef01bSRichard Henderson 
3212577efa45SRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(stick_cmpr));
3213577efa45SRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
32140faef01bSRichard Henderson     translator_io_start(&dc->base);
3215577efa45SRichard Henderson     gen_helper_tick_set_limit(r_tickptr, src);
32160faef01bSRichard Henderson     /* End TB to handle timer interrupt */
32170faef01bSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
32180faef01bSRichard Henderson }
32190faef01bSRichard Henderson 
32200faef01bSRichard Henderson TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr)
32210faef01bSRichard Henderson 
32220faef01bSRichard Henderson static void do_wrpowerdown(DisasContext *dc, TCGv src)
32230faef01bSRichard Henderson {
322489527e3aSRichard Henderson     finishing_insn(dc);
32250faef01bSRichard Henderson     save_state(dc);
32260faef01bSRichard Henderson     gen_helper_power_down(tcg_env);
32270faef01bSRichard Henderson }
32280faef01bSRichard Henderson 
32290faef01bSRichard Henderson TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
32300faef01bSRichard Henderson 
323125524734SRichard Henderson static void do_wrpsr(DisasContext *dc, TCGv src)
323225524734SRichard Henderson {
323325524734SRichard Henderson     gen_helper_wrpsr(tcg_env, src);
323425524734SRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
323525524734SRichard Henderson }
323625524734SRichard Henderson 
323725524734SRichard Henderson TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
323825524734SRichard Henderson 
32399422278eSRichard Henderson static void do_wrwim(DisasContext *dc, TCGv src)
32409422278eSRichard Henderson {
32419422278eSRichard Henderson     target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);
3242cd6269f7SRichard Henderson     TCGv tmp = tcg_temp_new();
3243cd6269f7SRichard Henderson 
3244cd6269f7SRichard Henderson     tcg_gen_andi_tl(tmp, src, mask);
3245cd6269f7SRichard Henderson     tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim));
32469422278eSRichard Henderson }
32479422278eSRichard Henderson 
32489422278eSRichard Henderson TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim)
32499422278eSRichard Henderson 
32509422278eSRichard Henderson static void do_wrtpc(DisasContext *dc, TCGv src)
32519422278eSRichard Henderson {
32529422278eSRichard Henderson #ifdef TARGET_SPARC64
32539422278eSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
32549422278eSRichard Henderson 
32559422278eSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
32569422278eSRichard Henderson     tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tpc));
32579422278eSRichard Henderson #else
32589422278eSRichard Henderson     qemu_build_not_reached();
32599422278eSRichard Henderson #endif
32609422278eSRichard Henderson }
32619422278eSRichard Henderson 
32629422278eSRichard Henderson TRANS(WRPR_tpc, 64, do_wr_special, a, supervisor(dc), do_wrtpc)
32639422278eSRichard Henderson 
32649422278eSRichard Henderson static void do_wrtnpc(DisasContext *dc, TCGv src)
32659422278eSRichard Henderson {
32669422278eSRichard Henderson #ifdef TARGET_SPARC64
32679422278eSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
32689422278eSRichard Henderson 
32699422278eSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
32709422278eSRichard Henderson     tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tnpc));
32719422278eSRichard Henderson #else
32729422278eSRichard Henderson     qemu_build_not_reached();
32739422278eSRichard Henderson #endif
32749422278eSRichard Henderson }
32759422278eSRichard Henderson 
32769422278eSRichard Henderson TRANS(WRPR_tnpc, 64, do_wr_special, a, supervisor(dc), do_wrtnpc)
32779422278eSRichard Henderson 
32789422278eSRichard Henderson static void do_wrtstate(DisasContext *dc, TCGv src)
32799422278eSRichard Henderson {
32809422278eSRichard Henderson #ifdef TARGET_SPARC64
32819422278eSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
32829422278eSRichard Henderson 
32839422278eSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
32849422278eSRichard Henderson     tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tstate));
32859422278eSRichard Henderson #else
32869422278eSRichard Henderson     qemu_build_not_reached();
32879422278eSRichard Henderson #endif
32889422278eSRichard Henderson }
32899422278eSRichard Henderson 
32909422278eSRichard Henderson TRANS(WRPR_tstate, 64, do_wr_special, a, supervisor(dc), do_wrtstate)
32919422278eSRichard Henderson 
32929422278eSRichard Henderson static void do_wrtt(DisasContext *dc, TCGv src)
32939422278eSRichard Henderson {
32949422278eSRichard Henderson #ifdef TARGET_SPARC64
32959422278eSRichard Henderson     TCGv_ptr r_tsptr = tcg_temp_new_ptr();
32969422278eSRichard Henderson 
32979422278eSRichard Henderson     gen_load_trap_state_at_tl(r_tsptr);
32989422278eSRichard Henderson     tcg_gen_st32_tl(src, r_tsptr, offsetof(trap_state, tt));
32999422278eSRichard Henderson #else
33009422278eSRichard Henderson     qemu_build_not_reached();
33019422278eSRichard Henderson #endif
33029422278eSRichard Henderson }
33039422278eSRichard Henderson 
33049422278eSRichard Henderson TRANS(WRPR_tt, 64, do_wr_special, a, supervisor(dc), do_wrtt)
33059422278eSRichard Henderson 
33069422278eSRichard Henderson static void do_wrtick(DisasContext *dc, TCGv src)
33079422278eSRichard Henderson {
33089422278eSRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
33099422278eSRichard Henderson 
33109422278eSRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
33119422278eSRichard Henderson     translator_io_start(&dc->base);
33129422278eSRichard Henderson     gen_helper_tick_set_count(r_tickptr, src);
33139422278eSRichard Henderson     /* End TB to handle timer interrupt */
33149422278eSRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
33159422278eSRichard Henderson }
33169422278eSRichard Henderson 
33179422278eSRichard Henderson TRANS(WRPR_tick, 64, do_wr_special, a, supervisor(dc), do_wrtick)
33189422278eSRichard Henderson 
33199422278eSRichard Henderson static void do_wrtba(DisasContext *dc, TCGv src)
33209422278eSRichard Henderson {
33219422278eSRichard Henderson     tcg_gen_mov_tl(cpu_tbr, src);
33229422278eSRichard Henderson }
33239422278eSRichard Henderson 
33249422278eSRichard Henderson TRANS(WRPR_tba, 64, do_wr_special, a, supervisor(dc), do_wrtba)
33259422278eSRichard Henderson 
33269422278eSRichard Henderson static void do_wrpstate(DisasContext *dc, TCGv src)
33279422278eSRichard Henderson {
33289422278eSRichard Henderson     save_state(dc);
33299422278eSRichard Henderson     if (translator_io_start(&dc->base)) {
33309422278eSRichard Henderson         dc->base.is_jmp = DISAS_EXIT;
33319422278eSRichard Henderson     }
33329422278eSRichard Henderson     gen_helper_wrpstate(tcg_env, src);
33339422278eSRichard Henderson     dc->npc = DYNAMIC_PC;
33349422278eSRichard Henderson }
33359422278eSRichard Henderson 
33369422278eSRichard Henderson TRANS(WRPR_pstate, 64, do_wr_special, a, supervisor(dc), do_wrpstate)
33379422278eSRichard Henderson 
33389422278eSRichard Henderson static void do_wrtl(DisasContext *dc, TCGv src)
33399422278eSRichard Henderson {
33409422278eSRichard Henderson     save_state(dc);
33419422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(tl));
33429422278eSRichard Henderson     dc->npc = DYNAMIC_PC;
33439422278eSRichard Henderson }
33449422278eSRichard Henderson 
33459422278eSRichard Henderson TRANS(WRPR_tl, 64, do_wr_special, a, supervisor(dc), do_wrtl)
33469422278eSRichard Henderson 
33479422278eSRichard Henderson static void do_wrpil(DisasContext *dc, TCGv src)
33489422278eSRichard Henderson {
33499422278eSRichard Henderson     if (translator_io_start(&dc->base)) {
33509422278eSRichard Henderson         dc->base.is_jmp = DISAS_EXIT;
33519422278eSRichard Henderson     }
33529422278eSRichard Henderson     gen_helper_wrpil(tcg_env, src);
33539422278eSRichard Henderson }
33549422278eSRichard Henderson 
33559422278eSRichard Henderson TRANS(WRPR_pil, 64, do_wr_special, a, supervisor(dc), do_wrpil)
33569422278eSRichard Henderson 
33579422278eSRichard Henderson static void do_wrcwp(DisasContext *dc, TCGv src)
33589422278eSRichard Henderson {
33599422278eSRichard Henderson     gen_helper_wrcwp(tcg_env, src);
33609422278eSRichard Henderson }
33619422278eSRichard Henderson 
33629422278eSRichard Henderson TRANS(WRPR_cwp, 64, do_wr_special, a, supervisor(dc), do_wrcwp)
33639422278eSRichard Henderson 
33649422278eSRichard Henderson static void do_wrcansave(DisasContext *dc, TCGv src)
33659422278eSRichard Henderson {
33669422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cansave));
33679422278eSRichard Henderson }
33689422278eSRichard Henderson 
33699422278eSRichard Henderson TRANS(WRPR_cansave, 64, do_wr_special, a, supervisor(dc), do_wrcansave)
33709422278eSRichard Henderson 
33719422278eSRichard Henderson static void do_wrcanrestore(DisasContext *dc, TCGv src)
33729422278eSRichard Henderson {
33739422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(canrestore));
33749422278eSRichard Henderson }
33759422278eSRichard Henderson 
33769422278eSRichard Henderson TRANS(WRPR_canrestore, 64, do_wr_special, a, supervisor(dc), do_wrcanrestore)
33779422278eSRichard Henderson 
33789422278eSRichard Henderson static void do_wrcleanwin(DisasContext *dc, TCGv src)
33799422278eSRichard Henderson {
33809422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cleanwin));
33819422278eSRichard Henderson }
33829422278eSRichard Henderson 
33839422278eSRichard Henderson TRANS(WRPR_cleanwin, 64, do_wr_special, a, supervisor(dc), do_wrcleanwin)
33849422278eSRichard Henderson 
33859422278eSRichard Henderson static void do_wrotherwin(DisasContext *dc, TCGv src)
33869422278eSRichard Henderson {
33879422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(otherwin));
33889422278eSRichard Henderson }
33899422278eSRichard Henderson 
33909422278eSRichard Henderson TRANS(WRPR_otherwin, 64, do_wr_special, a, supervisor(dc), do_wrotherwin)
33919422278eSRichard Henderson 
33929422278eSRichard Henderson static void do_wrwstate(DisasContext *dc, TCGv src)
33939422278eSRichard Henderson {
33949422278eSRichard Henderson     tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(wstate));
33959422278eSRichard Henderson }
33969422278eSRichard Henderson 
33979422278eSRichard Henderson TRANS(WRPR_wstate, 64, do_wr_special, a, supervisor(dc), do_wrwstate)
33989422278eSRichard Henderson 
33999422278eSRichard Henderson static void do_wrgl(DisasContext *dc, TCGv src)
34009422278eSRichard Henderson {
34019422278eSRichard Henderson     gen_helper_wrgl(tcg_env, src);
34029422278eSRichard Henderson }
34039422278eSRichard Henderson 
34049422278eSRichard Henderson TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), do_wrgl)
34059422278eSRichard Henderson 
34069422278eSRichard Henderson /* UA2005 strand status */
34079422278eSRichard Henderson static void do_wrssr(DisasContext *dc, TCGv src)
34089422278eSRichard Henderson {
34092da789deSRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(ssr));
34109422278eSRichard Henderson }
34119422278eSRichard Henderson 
34129422278eSRichard Henderson TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr)
34139422278eSRichard Henderson 
3414bb97f2f5SRichard Henderson TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba)
3415bb97f2f5SRichard Henderson 
3416bb97f2f5SRichard Henderson static void do_wrhpstate(DisasContext *dc, TCGv src)
3417bb97f2f5SRichard Henderson {
3418bb97f2f5SRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hpstate));
3419bb97f2f5SRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
3420bb97f2f5SRichard Henderson }
3421bb97f2f5SRichard Henderson 
3422bb97f2f5SRichard Henderson TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate)
3423bb97f2f5SRichard Henderson 
3424bb97f2f5SRichard Henderson static void do_wrhtstate(DisasContext *dc, TCGv src)
3425bb97f2f5SRichard Henderson {
3426bb97f2f5SRichard Henderson     TCGv_i32 tl = tcg_temp_new_i32();
3427bb97f2f5SRichard Henderson     TCGv_ptr tp = tcg_temp_new_ptr();
3428bb97f2f5SRichard Henderson 
3429bb97f2f5SRichard Henderson     tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
3430bb97f2f5SRichard Henderson     tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
3431bb97f2f5SRichard Henderson     tcg_gen_shli_i32(tl, tl, 3);
3432bb97f2f5SRichard Henderson     tcg_gen_ext_i32_ptr(tp, tl);
3433bb97f2f5SRichard Henderson     tcg_gen_add_ptr(tp, tp, tcg_env);
3434bb97f2f5SRichard Henderson 
3435bb97f2f5SRichard Henderson     tcg_gen_st_tl(src, tp, env64_field_offsetof(htstate));
3436bb97f2f5SRichard Henderson }
3437bb97f2f5SRichard Henderson 
3438bb97f2f5SRichard Henderson TRANS(WRHPR_htstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtstate)
3439bb97f2f5SRichard Henderson 
3440bb97f2f5SRichard Henderson static void do_wrhintp(DisasContext *dc, TCGv src)
3441bb97f2f5SRichard Henderson {
34422da789deSRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hintp));
3443bb97f2f5SRichard Henderson }
3444bb97f2f5SRichard Henderson 
3445bb97f2f5SRichard Henderson TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp)
3446bb97f2f5SRichard Henderson 
3447bb97f2f5SRichard Henderson static void do_wrhtba(DisasContext *dc, TCGv src)
3448bb97f2f5SRichard Henderson {
34492da789deSRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(htba));
3450bb97f2f5SRichard Henderson }
3451bb97f2f5SRichard Henderson 
3452bb97f2f5SRichard Henderson TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba)
3453bb97f2f5SRichard Henderson 
3454bb97f2f5SRichard Henderson static void do_wrhstick_cmpr(DisasContext *dc, TCGv src)
3455bb97f2f5SRichard Henderson {
3456bb97f2f5SRichard Henderson     TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3457bb97f2f5SRichard Henderson 
3458577efa45SRichard Henderson     tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hstick_cmpr));
3459bb97f2f5SRichard Henderson     tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick));
3460bb97f2f5SRichard Henderson     translator_io_start(&dc->base);
3461577efa45SRichard Henderson     gen_helper_tick_set_limit(r_tickptr, src);
3462bb97f2f5SRichard Henderson     /* End TB to handle timer interrupt */
3463bb97f2f5SRichard Henderson     dc->base.is_jmp = DISAS_EXIT;
3464bb97f2f5SRichard Henderson }
3465bb97f2f5SRichard Henderson 
3466bb97f2f5SRichard Henderson TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc),
3467bb97f2f5SRichard Henderson       do_wrhstick_cmpr)
3468bb97f2f5SRichard Henderson 
346925524734SRichard Henderson static bool do_saved_restored(DisasContext *dc, bool saved)
347025524734SRichard Henderson {
347125524734SRichard Henderson     if (!supervisor(dc)) {
347225524734SRichard Henderson         return raise_priv(dc);
347325524734SRichard Henderson     }
347425524734SRichard Henderson     if (saved) {
347525524734SRichard Henderson         gen_helper_saved(tcg_env);
347625524734SRichard Henderson     } else {
347725524734SRichard Henderson         gen_helper_restored(tcg_env);
347825524734SRichard Henderson     }
347925524734SRichard Henderson     return advance_pc(dc);
348025524734SRichard Henderson }
348125524734SRichard Henderson 
348225524734SRichard Henderson TRANS(SAVED, 64, do_saved_restored, true)
348325524734SRichard Henderson TRANS(RESTORED, 64, do_saved_restored, false)
348425524734SRichard Henderson 
3485d3825800SRichard Henderson static bool trans_NOP(DisasContext *dc, arg_NOP *a)
3486d3825800SRichard Henderson {
3487d3825800SRichard Henderson     return advance_pc(dc);
3488d3825800SRichard Henderson }
3489d3825800SRichard Henderson 
34900faef01bSRichard Henderson /*
34910faef01bSRichard Henderson  * TODO: Need a feature bit for sparcv8.
34920faef01bSRichard Henderson  * In the meantime, treat all 32-bit cpus like sparcv7.
34930faef01bSRichard Henderson  */
34945458fd31SRichard Henderson TRANS(NOP_v7, 32, trans_NOP, a)
34955458fd31SRichard Henderson TRANS(NOP_v9, 64, trans_NOP, a)
34960faef01bSRichard Henderson 
3497b597eedcSRichard Henderson static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a,
3498428881deSRichard Henderson                          void (*func)(TCGv, TCGv, TCGv),
34992a45b736SRichard Henderson                          void (*funci)(TCGv, TCGv, target_long),
35002a45b736SRichard Henderson                          bool logic_cc)
3501428881deSRichard Henderson {
3502428881deSRichard Henderson     TCGv dst, src1;
3503428881deSRichard Henderson 
3504428881deSRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
3505428881deSRichard Henderson     if (!a->imm && a->rs2_or_imm & ~0x1f) {
3506428881deSRichard Henderson         return false;
3507428881deSRichard Henderson     }
3508428881deSRichard Henderson 
35092a45b736SRichard Henderson     if (logic_cc) {
35102a45b736SRichard Henderson         dst = cpu_cc_N;
3511428881deSRichard Henderson     } else {
3512428881deSRichard Henderson         dst = gen_dest_gpr(dc, a->rd);
3513428881deSRichard Henderson     }
3514428881deSRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
3515428881deSRichard Henderson 
3516428881deSRichard Henderson     if (a->imm || a->rs2_or_imm == 0) {
3517428881deSRichard Henderson         if (funci) {
3518428881deSRichard Henderson             funci(dst, src1, a->rs2_or_imm);
3519428881deSRichard Henderson         } else {
3520428881deSRichard Henderson             func(dst, src1, tcg_constant_tl(a->rs2_or_imm));
3521428881deSRichard Henderson         }
3522428881deSRichard Henderson     } else {
3523428881deSRichard Henderson         func(dst, src1, cpu_regs[a->rs2_or_imm]);
3524428881deSRichard Henderson     }
35252a45b736SRichard Henderson 
35262a45b736SRichard Henderson     if (logic_cc) {
35272a45b736SRichard Henderson         if (TARGET_LONG_BITS == 64) {
35282a45b736SRichard Henderson             tcg_gen_mov_tl(cpu_icc_Z, cpu_cc_N);
35292a45b736SRichard Henderson             tcg_gen_movi_tl(cpu_icc_C, 0);
35302a45b736SRichard Henderson         }
35312a45b736SRichard Henderson         tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
35322a45b736SRichard Henderson         tcg_gen_movi_tl(cpu_cc_C, 0);
35332a45b736SRichard Henderson         tcg_gen_movi_tl(cpu_cc_V, 0);
35342a45b736SRichard Henderson     }
35352a45b736SRichard Henderson 
3536428881deSRichard Henderson     gen_store_gpr(dc, a->rd, dst);
3537428881deSRichard Henderson     return advance_pc(dc);
3538428881deSRichard Henderson }
3539428881deSRichard Henderson 
3540b597eedcSRichard Henderson static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a,
3541428881deSRichard Henderson                      void (*func)(TCGv, TCGv, TCGv),
3542428881deSRichard Henderson                      void (*funci)(TCGv, TCGv, target_long),
3543428881deSRichard Henderson                      void (*func_cc)(TCGv, TCGv, TCGv))
3544428881deSRichard Henderson {
3545428881deSRichard Henderson     if (a->cc) {
3546b597eedcSRichard Henderson         return do_arith_int(dc, a, func_cc, NULL, false);
3547428881deSRichard Henderson     }
3548b597eedcSRichard Henderson     return do_arith_int(dc, a, func, funci, false);
3549428881deSRichard Henderson }
3550428881deSRichard Henderson 
3551428881deSRichard Henderson static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
3552428881deSRichard Henderson                      void (*func)(TCGv, TCGv, TCGv),
3553428881deSRichard Henderson                      void (*funci)(TCGv, TCGv, target_long))
3554428881deSRichard Henderson {
3555b597eedcSRichard Henderson     return do_arith_int(dc, a, func, funci, a->cc);
3556428881deSRichard Henderson }
3557428881deSRichard Henderson 
3558b597eedcSRichard Henderson TRANS(ADD, ALL, do_arith, a, tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc)
3559b597eedcSRichard Henderson TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc)
3560b597eedcSRichard Henderson TRANS(ADDC, ALL, do_arith, a, gen_op_addc, NULL, gen_op_addccc)
3561b597eedcSRichard Henderson TRANS(SUBC, ALL, do_arith, a, gen_op_subc, NULL, gen_op_subccc)
3562428881deSRichard Henderson 
3563b597eedcSRichard Henderson TRANS(TADDcc, ALL, do_arith, a, NULL, NULL, gen_op_taddcc)
3564b597eedcSRichard Henderson TRANS(TSUBcc, ALL, do_arith, a, NULL, NULL, gen_op_tsubcc)
3565b597eedcSRichard Henderson TRANS(TADDccTV, ALL, do_arith, a, NULL, NULL, gen_op_taddcctv)
3566b597eedcSRichard Henderson TRANS(TSUBccTV, ALL, do_arith, a, NULL, NULL, gen_op_tsubcctv)
3567a9aba13dSRichard Henderson 
3568428881deSRichard Henderson TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
3569428881deSRichard Henderson TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
3570428881deSRichard Henderson TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
3571428881deSRichard Henderson TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
3572428881deSRichard Henderson TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
3573428881deSRichard Henderson 
3574b597eedcSRichard Henderson TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
3575b5372650SRichard Henderson TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
3576b5372650SRichard Henderson TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
3577b597eedcSRichard Henderson TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc)
357822188d7dSRichard Henderson 
35793a6b8de3SRichard Henderson TRANS(UDIVcc, DIV, do_arith, a, NULL, NULL, gen_op_udivcc)
3580b597eedcSRichard Henderson TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc)
35814ee85ea9SRichard Henderson 
35829c6ec5bcSRichard Henderson /* TODO: Should have feature bit -- comes in with UltraSparc T2. */
3583b597eedcSRichard Henderson TRANS(POPC, 64, do_arith, a, gen_op_popc, NULL, NULL)
35849c6ec5bcSRichard Henderson 
3585428881deSRichard Henderson static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
3586428881deSRichard Henderson {
3587428881deSRichard Henderson     /* OR with %g0 is the canonical alias for MOV. */
3588428881deSRichard Henderson     if (!a->cc && a->rs1 == 0) {
3589428881deSRichard Henderson         if (a->imm || a->rs2_or_imm == 0) {
3590428881deSRichard Henderson             gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
3591428881deSRichard Henderson         } else if (a->rs2_or_imm & ~0x1f) {
3592428881deSRichard Henderson             /* For simplicity, we under-decoded the rs2 form. */
3593428881deSRichard Henderson             return false;
3594428881deSRichard Henderson         } else {
3595428881deSRichard Henderson             gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
3596428881deSRichard Henderson         }
3597428881deSRichard Henderson         return advance_pc(dc);
3598428881deSRichard Henderson     }
3599428881deSRichard Henderson     return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
3600428881deSRichard Henderson }
3601428881deSRichard Henderson 
36023a6b8de3SRichard Henderson static bool trans_UDIV(DisasContext *dc, arg_r_r_ri *a)
36033a6b8de3SRichard Henderson {
36043a6b8de3SRichard Henderson     TCGv_i64 t1, t2;
36053a6b8de3SRichard Henderson     TCGv dst;
36063a6b8de3SRichard Henderson 
36073a6b8de3SRichard Henderson     if (!avail_DIV(dc)) {
36083a6b8de3SRichard Henderson         return false;
36093a6b8de3SRichard Henderson     }
36103a6b8de3SRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
36113a6b8de3SRichard Henderson     if (!a->imm && a->rs2_or_imm & ~0x1f) {
36123a6b8de3SRichard Henderson         return false;
36133a6b8de3SRichard Henderson     }
36143a6b8de3SRichard Henderson 
36153a6b8de3SRichard Henderson     if (unlikely(a->rs2_or_imm == 0)) {
36163a6b8de3SRichard Henderson         gen_exception(dc, TT_DIV_ZERO);
36173a6b8de3SRichard Henderson         return true;
36183a6b8de3SRichard Henderson     }
36193a6b8de3SRichard Henderson 
36203a6b8de3SRichard Henderson     if (a->imm) {
36213a6b8de3SRichard Henderson         t2 = tcg_constant_i64((uint32_t)a->rs2_or_imm);
36223a6b8de3SRichard Henderson     } else {
36233a6b8de3SRichard Henderson         TCGLabel *lab;
36243a6b8de3SRichard Henderson         TCGv_i32 n2;
36253a6b8de3SRichard Henderson 
36263a6b8de3SRichard Henderson         finishing_insn(dc);
36273a6b8de3SRichard Henderson         flush_cond(dc);
36283a6b8de3SRichard Henderson 
36293a6b8de3SRichard Henderson         n2 = tcg_temp_new_i32();
36303a6b8de3SRichard Henderson         tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]);
36313a6b8de3SRichard Henderson 
36323a6b8de3SRichard Henderson         lab = delay_exception(dc, TT_DIV_ZERO);
36333a6b8de3SRichard Henderson         tcg_gen_brcondi_i32(TCG_COND_EQ, n2, 0, lab);
36343a6b8de3SRichard Henderson 
36353a6b8de3SRichard Henderson         t2 = tcg_temp_new_i64();
36363a6b8de3SRichard Henderson #ifdef TARGET_SPARC64
36373a6b8de3SRichard Henderson         tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]);
36383a6b8de3SRichard Henderson #else
36393a6b8de3SRichard Henderson         tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]);
36403a6b8de3SRichard Henderson #endif
36413a6b8de3SRichard Henderson     }
36423a6b8de3SRichard Henderson 
36433a6b8de3SRichard Henderson     t1 = tcg_temp_new_i64();
36443a6b8de3SRichard Henderson     tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y);
36453a6b8de3SRichard Henderson 
36463a6b8de3SRichard Henderson     tcg_gen_divu_i64(t1, t1, t2);
36473a6b8de3SRichard Henderson     tcg_gen_umin_i64(t1, t1, tcg_constant_i64(UINT32_MAX));
36483a6b8de3SRichard Henderson 
36493a6b8de3SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
36503a6b8de3SRichard Henderson     tcg_gen_trunc_i64_tl(dst, t1);
36513a6b8de3SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
36523a6b8de3SRichard Henderson     return advance_pc(dc);
36533a6b8de3SRichard Henderson }
36543a6b8de3SRichard Henderson 
3655f3141174SRichard Henderson static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a)
3656f3141174SRichard Henderson {
3657f3141174SRichard Henderson     TCGv dst, src1, src2;
3658f3141174SRichard Henderson 
3659f3141174SRichard Henderson     if (!avail_64(dc)) {
3660f3141174SRichard Henderson         return false;
3661f3141174SRichard Henderson     }
3662f3141174SRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
3663f3141174SRichard Henderson     if (!a->imm && a->rs2_or_imm & ~0x1f) {
3664f3141174SRichard Henderson         return false;
3665f3141174SRichard Henderson     }
3666f3141174SRichard Henderson 
3667f3141174SRichard Henderson     if (unlikely(a->rs2_or_imm == 0)) {
3668f3141174SRichard Henderson         gen_exception(dc, TT_DIV_ZERO);
3669f3141174SRichard Henderson         return true;
3670f3141174SRichard Henderson     }
3671f3141174SRichard Henderson 
3672f3141174SRichard Henderson     if (a->imm) {
3673f3141174SRichard Henderson         src2 = tcg_constant_tl(a->rs2_or_imm);
3674f3141174SRichard Henderson     } else {
3675f3141174SRichard Henderson         TCGLabel *lab;
3676f3141174SRichard Henderson 
3677f3141174SRichard Henderson         finishing_insn(dc);
3678f3141174SRichard Henderson         flush_cond(dc);
3679f3141174SRichard Henderson 
3680f3141174SRichard Henderson         lab = delay_exception(dc, TT_DIV_ZERO);
3681f3141174SRichard Henderson         src2 = cpu_regs[a->rs2_or_imm];
3682f3141174SRichard Henderson         tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
3683f3141174SRichard Henderson     }
3684f3141174SRichard Henderson 
3685f3141174SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
3686f3141174SRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
3687f3141174SRichard Henderson 
3688f3141174SRichard Henderson     tcg_gen_divu_tl(dst, src1, src2);
3689f3141174SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
3690f3141174SRichard Henderson     return advance_pc(dc);
3691f3141174SRichard Henderson }
3692f3141174SRichard Henderson 
3693f3141174SRichard Henderson static bool trans_SDIVX(DisasContext *dc, arg_r_r_ri *a)
3694f3141174SRichard Henderson {
3695f3141174SRichard Henderson     TCGv dst, src1, src2;
3696f3141174SRichard Henderson 
3697f3141174SRichard Henderson     if (!avail_64(dc)) {
3698f3141174SRichard Henderson         return false;
3699f3141174SRichard Henderson     }
3700f3141174SRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
3701f3141174SRichard Henderson     if (!a->imm && a->rs2_or_imm & ~0x1f) {
3702f3141174SRichard Henderson         return false;
3703f3141174SRichard Henderson     }
3704f3141174SRichard Henderson 
3705f3141174SRichard Henderson     if (unlikely(a->rs2_or_imm == 0)) {
3706f3141174SRichard Henderson         gen_exception(dc, TT_DIV_ZERO);
3707f3141174SRichard Henderson         return true;
3708f3141174SRichard Henderson     }
3709f3141174SRichard Henderson 
3710f3141174SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
3711f3141174SRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
3712f3141174SRichard Henderson 
3713f3141174SRichard Henderson     if (a->imm) {
3714f3141174SRichard Henderson         if (unlikely(a->rs2_or_imm == -1)) {
3715f3141174SRichard Henderson             tcg_gen_neg_tl(dst, src1);
3716f3141174SRichard Henderson             gen_store_gpr(dc, a->rd, dst);
3717f3141174SRichard Henderson             return advance_pc(dc);
3718f3141174SRichard Henderson         }
3719f3141174SRichard Henderson         src2 = tcg_constant_tl(a->rs2_or_imm);
3720f3141174SRichard Henderson     } else {
3721f3141174SRichard Henderson         TCGLabel *lab;
3722f3141174SRichard Henderson         TCGv t1, t2;
3723f3141174SRichard Henderson 
3724f3141174SRichard Henderson         finishing_insn(dc);
3725f3141174SRichard Henderson         flush_cond(dc);
3726f3141174SRichard Henderson 
3727f3141174SRichard Henderson         lab = delay_exception(dc, TT_DIV_ZERO);
3728f3141174SRichard Henderson         src2 = cpu_regs[a->rs2_or_imm];
3729f3141174SRichard Henderson         tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
3730f3141174SRichard Henderson 
3731f3141174SRichard Henderson         /*
3732f3141174SRichard Henderson          * Need to avoid INT64_MIN / -1, which will trap on x86 host.
3733f3141174SRichard Henderson          * Set SRC2 to 1 as a new divisor, to produce the correct result.
3734f3141174SRichard Henderson          */
3735f3141174SRichard Henderson         t1 = tcg_temp_new();
3736f3141174SRichard Henderson         t2 = tcg_temp_new();
3737f3141174SRichard Henderson         tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src1, (target_long)INT64_MIN);
3738f3141174SRichard Henderson         tcg_gen_setcondi_tl(TCG_COND_EQ, t2, src2, -1);
3739f3141174SRichard Henderson         tcg_gen_and_tl(t1, t1, t2);
3740f3141174SRichard Henderson         tcg_gen_movcond_tl(TCG_COND_NE, t1, t1, tcg_constant_tl(0),
3741f3141174SRichard Henderson                            tcg_constant_tl(1), src2);
3742f3141174SRichard Henderson         src2 = t1;
3743f3141174SRichard Henderson     }
3744f3141174SRichard Henderson 
3745f3141174SRichard Henderson     tcg_gen_div_tl(dst, src1, src2);
3746f3141174SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
3747f3141174SRichard Henderson     return advance_pc(dc);
3748f3141174SRichard Henderson }
3749f3141174SRichard Henderson 
3750b88ce6f2SRichard Henderson static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
3751b88ce6f2SRichard Henderson                      int width, bool cc, bool left)
3752b88ce6f2SRichard Henderson {
3753b88ce6f2SRichard Henderson     TCGv dst, s1, s2, lo1, lo2;
3754b88ce6f2SRichard Henderson     uint64_t amask, tabl, tabr;
3755b88ce6f2SRichard Henderson     int shift, imask, omask;
3756b88ce6f2SRichard Henderson 
3757b88ce6f2SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
3758b88ce6f2SRichard Henderson     s1 = gen_load_gpr(dc, a->rs1);
3759b88ce6f2SRichard Henderson     s2 = gen_load_gpr(dc, a->rs2);
3760b88ce6f2SRichard Henderson 
3761b88ce6f2SRichard Henderson     if (cc) {
3762f828df74SRichard Henderson         gen_op_subcc(cpu_cc_N, s1, s2);
3763b88ce6f2SRichard Henderson     }
3764b88ce6f2SRichard Henderson 
3765b88ce6f2SRichard Henderson     /*
3766b88ce6f2SRichard Henderson      * Theory of operation: there are two tables, left and right (not to
3767b88ce6f2SRichard Henderson      * be confused with the left and right versions of the opcode).  These
3768b88ce6f2SRichard Henderson      * are indexed by the low 3 bits of the inputs.  To make things "easy",
3769b88ce6f2SRichard Henderson      * these tables are loaded into two constants, TABL and TABR below.
3770b88ce6f2SRichard Henderson      * The operation index = (input & imask) << shift calculates the index
3771b88ce6f2SRichard Henderson      * into the constant, while val = (table >> index) & omask calculates
3772b88ce6f2SRichard Henderson      * the value we're looking for.
3773b88ce6f2SRichard Henderson      */
3774b88ce6f2SRichard Henderson     switch (width) {
3775b88ce6f2SRichard Henderson     case 8:
3776b88ce6f2SRichard Henderson         imask = 0x7;
3777b88ce6f2SRichard Henderson         shift = 3;
3778b88ce6f2SRichard Henderson         omask = 0xff;
3779b88ce6f2SRichard Henderson         if (left) {
3780b88ce6f2SRichard Henderson             tabl = 0x80c0e0f0f8fcfeffULL;
3781b88ce6f2SRichard Henderson             tabr = 0xff7f3f1f0f070301ULL;
3782b88ce6f2SRichard Henderson         } else {
3783b88ce6f2SRichard Henderson             tabl = 0x0103070f1f3f7fffULL;
3784b88ce6f2SRichard Henderson             tabr = 0xfffefcf8f0e0c080ULL;
3785b88ce6f2SRichard Henderson         }
3786b88ce6f2SRichard Henderson         break;
3787b88ce6f2SRichard Henderson     case 16:
3788b88ce6f2SRichard Henderson         imask = 0x6;
3789b88ce6f2SRichard Henderson         shift = 1;
3790b88ce6f2SRichard Henderson         omask = 0xf;
3791b88ce6f2SRichard Henderson         if (left) {
3792b88ce6f2SRichard Henderson             tabl = 0x8cef;
3793b88ce6f2SRichard Henderson             tabr = 0xf731;
3794b88ce6f2SRichard Henderson         } else {
3795b88ce6f2SRichard Henderson             tabl = 0x137f;
3796b88ce6f2SRichard Henderson             tabr = 0xfec8;
3797b88ce6f2SRichard Henderson         }
3798b88ce6f2SRichard Henderson         break;
3799b88ce6f2SRichard Henderson     case 32:
3800b88ce6f2SRichard Henderson         imask = 0x4;
3801b88ce6f2SRichard Henderson         shift = 0;
3802b88ce6f2SRichard Henderson         omask = 0x3;
3803b88ce6f2SRichard Henderson         if (left) {
3804b88ce6f2SRichard Henderson             tabl = (2 << 2) | 3;
3805b88ce6f2SRichard Henderson             tabr = (3 << 2) | 1;
3806b88ce6f2SRichard Henderson         } else {
3807b88ce6f2SRichard Henderson             tabl = (1 << 2) | 3;
3808b88ce6f2SRichard Henderson             tabr = (3 << 2) | 2;
3809b88ce6f2SRichard Henderson         }
3810b88ce6f2SRichard Henderson         break;
3811b88ce6f2SRichard Henderson     default:
3812b88ce6f2SRichard Henderson         abort();
3813b88ce6f2SRichard Henderson     }
3814b88ce6f2SRichard Henderson 
3815b88ce6f2SRichard Henderson     lo1 = tcg_temp_new();
3816b88ce6f2SRichard Henderson     lo2 = tcg_temp_new();
3817b88ce6f2SRichard Henderson     tcg_gen_andi_tl(lo1, s1, imask);
3818b88ce6f2SRichard Henderson     tcg_gen_andi_tl(lo2, s2, imask);
3819b88ce6f2SRichard Henderson     tcg_gen_shli_tl(lo1, lo1, shift);
3820b88ce6f2SRichard Henderson     tcg_gen_shli_tl(lo2, lo2, shift);
3821b88ce6f2SRichard Henderson 
3822b88ce6f2SRichard Henderson     tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
3823b88ce6f2SRichard Henderson     tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
3824b88ce6f2SRichard Henderson     tcg_gen_andi_tl(lo1, lo1, omask);
3825b88ce6f2SRichard Henderson     tcg_gen_andi_tl(lo2, lo2, omask);
3826b88ce6f2SRichard Henderson 
3827b88ce6f2SRichard Henderson     amask = address_mask_i(dc, -8);
3828b88ce6f2SRichard Henderson     tcg_gen_andi_tl(s1, s1, amask);
3829b88ce6f2SRichard Henderson     tcg_gen_andi_tl(s2, s2, amask);
3830b88ce6f2SRichard Henderson 
3831b88ce6f2SRichard Henderson     /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
3832b88ce6f2SRichard Henderson     tcg_gen_and_tl(lo2, lo2, lo1);
3833b88ce6f2SRichard Henderson     tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
3834b88ce6f2SRichard Henderson 
3835b88ce6f2SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
3836b88ce6f2SRichard Henderson     return advance_pc(dc);
3837b88ce6f2SRichard Henderson }
3838b88ce6f2SRichard Henderson 
3839b88ce6f2SRichard Henderson TRANS(EDGE8cc, VIS1, gen_edge, a, 8, 1, 0)
3840b88ce6f2SRichard Henderson TRANS(EDGE8Lcc, VIS1, gen_edge, a, 8, 1, 1)
3841b88ce6f2SRichard Henderson TRANS(EDGE16cc, VIS1, gen_edge, a, 16, 1, 0)
3842b88ce6f2SRichard Henderson TRANS(EDGE16Lcc, VIS1, gen_edge, a, 16, 1, 1)
3843b88ce6f2SRichard Henderson TRANS(EDGE32cc, VIS1, gen_edge, a, 32, 1, 0)
3844b88ce6f2SRichard Henderson TRANS(EDGE32Lcc, VIS1, gen_edge, a, 32, 1, 1)
3845b88ce6f2SRichard Henderson 
3846b88ce6f2SRichard Henderson TRANS(EDGE8N, VIS2, gen_edge, a, 8, 0, 0)
3847b88ce6f2SRichard Henderson TRANS(EDGE8LN, VIS2, gen_edge, a, 8, 0, 1)
3848b88ce6f2SRichard Henderson TRANS(EDGE16N, VIS2, gen_edge, a, 16, 0, 0)
3849b88ce6f2SRichard Henderson TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1)
3850b88ce6f2SRichard Henderson TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0)
3851b88ce6f2SRichard Henderson TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1)
3852b88ce6f2SRichard Henderson 
385345bfed3bSRichard Henderson static bool do_rrr(DisasContext *dc, arg_r_r_r *a,
385445bfed3bSRichard Henderson                    void (*func)(TCGv, TCGv, TCGv))
385545bfed3bSRichard Henderson {
385645bfed3bSRichard Henderson     TCGv dst = gen_dest_gpr(dc, a->rd);
385745bfed3bSRichard Henderson     TCGv src1 = gen_load_gpr(dc, a->rs1);
385845bfed3bSRichard Henderson     TCGv src2 = gen_load_gpr(dc, a->rs2);
385945bfed3bSRichard Henderson 
386045bfed3bSRichard Henderson     func(dst, src1, src2);
386145bfed3bSRichard Henderson     gen_store_gpr(dc, a->rd, dst);
386245bfed3bSRichard Henderson     return advance_pc(dc);
386345bfed3bSRichard Henderson }
386445bfed3bSRichard Henderson 
386545bfed3bSRichard Henderson TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8)
386645bfed3bSRichard Henderson TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16)
386745bfed3bSRichard Henderson TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32)
386845bfed3bSRichard Henderson 
38699e20ca94SRichard Henderson static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2)
38709e20ca94SRichard Henderson {
38719e20ca94SRichard Henderson #ifdef TARGET_SPARC64
38729e20ca94SRichard Henderson     TCGv tmp = tcg_temp_new();
38739e20ca94SRichard Henderson 
38749e20ca94SRichard Henderson     tcg_gen_add_tl(tmp, s1, s2);
38759e20ca94SRichard Henderson     tcg_gen_andi_tl(dst, tmp, -8);
38769e20ca94SRichard Henderson     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
38779e20ca94SRichard Henderson #else
38789e20ca94SRichard Henderson     g_assert_not_reached();
38799e20ca94SRichard Henderson #endif
38809e20ca94SRichard Henderson }
38819e20ca94SRichard Henderson 
38829e20ca94SRichard Henderson static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2)
38839e20ca94SRichard Henderson {
38849e20ca94SRichard Henderson #ifdef TARGET_SPARC64
38859e20ca94SRichard Henderson     TCGv tmp = tcg_temp_new();
38869e20ca94SRichard Henderson 
38879e20ca94SRichard Henderson     tcg_gen_add_tl(tmp, s1, s2);
38889e20ca94SRichard Henderson     tcg_gen_andi_tl(dst, tmp, -8);
38899e20ca94SRichard Henderson     tcg_gen_neg_tl(tmp, tmp);
38909e20ca94SRichard Henderson     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
38919e20ca94SRichard Henderson #else
38929e20ca94SRichard Henderson     g_assert_not_reached();
38939e20ca94SRichard Henderson #endif
38949e20ca94SRichard Henderson }
38959e20ca94SRichard Henderson 
38969e20ca94SRichard Henderson TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr)
38979e20ca94SRichard Henderson TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl)
38989e20ca94SRichard Henderson 
389939ca3490SRichard Henderson static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2)
390039ca3490SRichard Henderson {
390139ca3490SRichard Henderson #ifdef TARGET_SPARC64
390239ca3490SRichard Henderson     tcg_gen_add_tl(dst, s1, s2);
390339ca3490SRichard Henderson     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, dst, 32, 32);
390439ca3490SRichard Henderson #else
390539ca3490SRichard Henderson     g_assert_not_reached();
390639ca3490SRichard Henderson #endif
390739ca3490SRichard Henderson }
390839ca3490SRichard Henderson 
390939ca3490SRichard Henderson TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask)
391039ca3490SRichard Henderson 
39115fc546eeSRichard Henderson static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
39125fc546eeSRichard Henderson {
39135fc546eeSRichard Henderson     TCGv dst, src1, src2;
39145fc546eeSRichard Henderson 
39155fc546eeSRichard Henderson     /* Reject 64-bit shifts for sparc32. */
39165fc546eeSRichard Henderson     if (avail_32(dc) && a->x) {
39175fc546eeSRichard Henderson         return false;
39185fc546eeSRichard Henderson     }
39195fc546eeSRichard Henderson 
39205fc546eeSRichard Henderson     src2 = tcg_temp_new();
39215fc546eeSRichard Henderson     tcg_gen_andi_tl(src2, gen_load_gpr(dc, a->rs2), a->x ? 63 : 31);
39225fc546eeSRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
39235fc546eeSRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
39245fc546eeSRichard Henderson 
39255fc546eeSRichard Henderson     if (l) {
39265fc546eeSRichard Henderson         tcg_gen_shl_tl(dst, src1, src2);
39275fc546eeSRichard Henderson         if (!a->x) {
39285fc546eeSRichard Henderson             tcg_gen_ext32u_tl(dst, dst);
39295fc546eeSRichard Henderson         }
39305fc546eeSRichard Henderson     } else if (u) {
39315fc546eeSRichard Henderson         if (!a->x) {
39325fc546eeSRichard Henderson             tcg_gen_ext32u_tl(dst, src1);
39335fc546eeSRichard Henderson             src1 = dst;
39345fc546eeSRichard Henderson         }
39355fc546eeSRichard Henderson         tcg_gen_shr_tl(dst, src1, src2);
39365fc546eeSRichard Henderson     } else {
39375fc546eeSRichard Henderson         if (!a->x) {
39385fc546eeSRichard Henderson             tcg_gen_ext32s_tl(dst, src1);
39395fc546eeSRichard Henderson             src1 = dst;
39405fc546eeSRichard Henderson         }
39415fc546eeSRichard Henderson         tcg_gen_sar_tl(dst, src1, src2);
39425fc546eeSRichard Henderson     }
39435fc546eeSRichard Henderson     gen_store_gpr(dc, a->rd, dst);
39445fc546eeSRichard Henderson     return advance_pc(dc);
39455fc546eeSRichard Henderson }
39465fc546eeSRichard Henderson 
39475fc546eeSRichard Henderson TRANS(SLL_r, ALL, do_shift_r, a, true, true)
39485fc546eeSRichard Henderson TRANS(SRL_r, ALL, do_shift_r, a, false, true)
39495fc546eeSRichard Henderson TRANS(SRA_r, ALL, do_shift_r, a, false, false)
39505fc546eeSRichard Henderson 
39515fc546eeSRichard Henderson static bool do_shift_i(DisasContext *dc, arg_shifti *a, bool l, bool u)
39525fc546eeSRichard Henderson {
39535fc546eeSRichard Henderson     TCGv dst, src1;
39545fc546eeSRichard Henderson 
39555fc546eeSRichard Henderson     /* Reject 64-bit shifts for sparc32. */
39565fc546eeSRichard Henderson     if (avail_32(dc) && (a->x || a->i >= 32)) {
39575fc546eeSRichard Henderson         return false;
39585fc546eeSRichard Henderson     }
39595fc546eeSRichard Henderson 
39605fc546eeSRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
39615fc546eeSRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
39625fc546eeSRichard Henderson 
39635fc546eeSRichard Henderson     if (avail_32(dc) || a->x) {
39645fc546eeSRichard Henderson         if (l) {
39655fc546eeSRichard Henderson             tcg_gen_shli_tl(dst, src1, a->i);
39665fc546eeSRichard Henderson         } else if (u) {
39675fc546eeSRichard Henderson             tcg_gen_shri_tl(dst, src1, a->i);
39685fc546eeSRichard Henderson         } else {
39695fc546eeSRichard Henderson             tcg_gen_sari_tl(dst, src1, a->i);
39705fc546eeSRichard Henderson         }
39715fc546eeSRichard Henderson     } else {
39725fc546eeSRichard Henderson         if (l) {
39735fc546eeSRichard Henderson             tcg_gen_deposit_z_tl(dst, src1, a->i, 32 - a->i);
39745fc546eeSRichard Henderson         } else if (u) {
39755fc546eeSRichard Henderson             tcg_gen_extract_tl(dst, src1, a->i, 32 - a->i);
39765fc546eeSRichard Henderson         } else {
39775fc546eeSRichard Henderson             tcg_gen_sextract_tl(dst, src1, a->i, 32 - a->i);
39785fc546eeSRichard Henderson         }
39795fc546eeSRichard Henderson     }
39805fc546eeSRichard Henderson     gen_store_gpr(dc, a->rd, dst);
39815fc546eeSRichard Henderson     return advance_pc(dc);
39825fc546eeSRichard Henderson }
39835fc546eeSRichard Henderson 
39845fc546eeSRichard Henderson TRANS(SLL_i, ALL, do_shift_i, a, true, true)
39855fc546eeSRichard Henderson TRANS(SRL_i, ALL, do_shift_i, a, false, true)
39865fc546eeSRichard Henderson TRANS(SRA_i, ALL, do_shift_i, a, false, false)
39875fc546eeSRichard Henderson 
3988fb4ed7aaSRichard Henderson static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
3989fb4ed7aaSRichard Henderson {
3990fb4ed7aaSRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
3991fb4ed7aaSRichard Henderson     if (!imm && rs2_or_imm & ~0x1f) {
3992fb4ed7aaSRichard Henderson         return NULL;
3993fb4ed7aaSRichard Henderson     }
3994fb4ed7aaSRichard Henderson     if (imm || rs2_or_imm == 0) {
3995fb4ed7aaSRichard Henderson         return tcg_constant_tl(rs2_or_imm);
3996fb4ed7aaSRichard Henderson     } else {
3997fb4ed7aaSRichard Henderson         return cpu_regs[rs2_or_imm];
3998fb4ed7aaSRichard Henderson     }
3999fb4ed7aaSRichard Henderson }
4000fb4ed7aaSRichard Henderson 
4001fb4ed7aaSRichard Henderson static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
4002fb4ed7aaSRichard Henderson {
4003fb4ed7aaSRichard Henderson     TCGv dst = gen_load_gpr(dc, rd);
4004c8507ebfSRichard Henderson     TCGv c2 = tcg_constant_tl(cmp->c2);
4005fb4ed7aaSRichard Henderson 
4006c8507ebfSRichard Henderson     tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, c2, src2, dst);
4007fb4ed7aaSRichard Henderson     gen_store_gpr(dc, rd, dst);
4008fb4ed7aaSRichard Henderson     return advance_pc(dc);
4009fb4ed7aaSRichard Henderson }
4010fb4ed7aaSRichard Henderson 
4011fb4ed7aaSRichard Henderson static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a)
4012fb4ed7aaSRichard Henderson {
4013fb4ed7aaSRichard Henderson     TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4014fb4ed7aaSRichard Henderson     DisasCompare cmp;
4015fb4ed7aaSRichard Henderson 
4016fb4ed7aaSRichard Henderson     if (src2 == NULL) {
4017fb4ed7aaSRichard Henderson         return false;
4018fb4ed7aaSRichard Henderson     }
4019fb4ed7aaSRichard Henderson     gen_compare(&cmp, a->cc, a->cond, dc);
4020fb4ed7aaSRichard Henderson     return do_mov_cond(dc, &cmp, a->rd, src2);
4021fb4ed7aaSRichard Henderson }
4022fb4ed7aaSRichard Henderson 
4023fb4ed7aaSRichard Henderson static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a)
4024fb4ed7aaSRichard Henderson {
4025fb4ed7aaSRichard Henderson     TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4026fb4ed7aaSRichard Henderson     DisasCompare cmp;
4027fb4ed7aaSRichard Henderson 
4028fb4ed7aaSRichard Henderson     if (src2 == NULL) {
4029fb4ed7aaSRichard Henderson         return false;
4030fb4ed7aaSRichard Henderson     }
4031fb4ed7aaSRichard Henderson     gen_fcompare(&cmp, a->cc, a->cond);
4032fb4ed7aaSRichard Henderson     return do_mov_cond(dc, &cmp, a->rd, src2);
4033fb4ed7aaSRichard Henderson }
4034fb4ed7aaSRichard Henderson 
4035fb4ed7aaSRichard Henderson static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
4036fb4ed7aaSRichard Henderson {
4037fb4ed7aaSRichard Henderson     TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4038fb4ed7aaSRichard Henderson     DisasCompare cmp;
4039fb4ed7aaSRichard Henderson 
4040fb4ed7aaSRichard Henderson     if (src2 == NULL) {
4041fb4ed7aaSRichard Henderson         return false;
4042fb4ed7aaSRichard Henderson     }
40432c4f56c9SRichard Henderson     if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
40442c4f56c9SRichard Henderson         return false;
40452c4f56c9SRichard Henderson     }
4046fb4ed7aaSRichard Henderson     return do_mov_cond(dc, &cmp, a->rd, src2);
4047fb4ed7aaSRichard Henderson }
4048fb4ed7aaSRichard Henderson 
404986b82fe0SRichard Henderson static bool do_add_special(DisasContext *dc, arg_r_r_ri *a,
405086b82fe0SRichard Henderson                            bool (*func)(DisasContext *dc, int rd, TCGv src))
405186b82fe0SRichard Henderson {
405286b82fe0SRichard Henderson     TCGv src1, sum;
405386b82fe0SRichard Henderson 
405486b82fe0SRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
405586b82fe0SRichard Henderson     if (!a->imm && a->rs2_or_imm & ~0x1f) {
405686b82fe0SRichard Henderson         return false;
405786b82fe0SRichard Henderson     }
405886b82fe0SRichard Henderson 
405986b82fe0SRichard Henderson     /*
406086b82fe0SRichard Henderson      * Always load the sum into a new temporary.
406186b82fe0SRichard Henderson      * This is required to capture the value across a window change,
406286b82fe0SRichard Henderson      * e.g. SAVE and RESTORE, and may be optimized away otherwise.
406386b82fe0SRichard Henderson      */
406486b82fe0SRichard Henderson     sum = tcg_temp_new();
406586b82fe0SRichard Henderson     src1 = gen_load_gpr(dc, a->rs1);
406686b82fe0SRichard Henderson     if (a->imm || a->rs2_or_imm == 0) {
406786b82fe0SRichard Henderson         tcg_gen_addi_tl(sum, src1, a->rs2_or_imm);
406886b82fe0SRichard Henderson     } else {
406986b82fe0SRichard Henderson         tcg_gen_add_tl(sum, src1, cpu_regs[a->rs2_or_imm]);
407086b82fe0SRichard Henderson     }
407186b82fe0SRichard Henderson     return func(dc, a->rd, sum);
407286b82fe0SRichard Henderson }
407386b82fe0SRichard Henderson 
407486b82fe0SRichard Henderson static bool do_jmpl(DisasContext *dc, int rd, TCGv src)
407586b82fe0SRichard Henderson {
407686b82fe0SRichard Henderson     /*
407786b82fe0SRichard Henderson      * Preserve pc across advance, so that we can delay
407886b82fe0SRichard Henderson      * the writeback to rd until after src is consumed.
407986b82fe0SRichard Henderson      */
408086b82fe0SRichard Henderson     target_ulong cur_pc = dc->pc;
408186b82fe0SRichard Henderson 
408286b82fe0SRichard Henderson     gen_check_align(dc, src, 3);
408386b82fe0SRichard Henderson 
408486b82fe0SRichard Henderson     gen_mov_pc_npc(dc);
408586b82fe0SRichard Henderson     tcg_gen_mov_tl(cpu_npc, src);
408686b82fe0SRichard Henderson     gen_address_mask(dc, cpu_npc);
408786b82fe0SRichard Henderson     gen_store_gpr(dc, rd, tcg_constant_tl(cur_pc));
408886b82fe0SRichard Henderson 
408986b82fe0SRichard Henderson     dc->npc = DYNAMIC_PC_LOOKUP;
409086b82fe0SRichard Henderson     return true;
409186b82fe0SRichard Henderson }
409286b82fe0SRichard Henderson 
409386b82fe0SRichard Henderson TRANS(JMPL, ALL, do_add_special, a, do_jmpl)
409486b82fe0SRichard Henderson 
409586b82fe0SRichard Henderson static bool do_rett(DisasContext *dc, int rd, TCGv src)
409686b82fe0SRichard Henderson {
409786b82fe0SRichard Henderson     if (!supervisor(dc)) {
409886b82fe0SRichard Henderson         return raise_priv(dc);
409986b82fe0SRichard Henderson     }
410086b82fe0SRichard Henderson 
410186b82fe0SRichard Henderson     gen_check_align(dc, src, 3);
410286b82fe0SRichard Henderson 
410386b82fe0SRichard Henderson     gen_mov_pc_npc(dc);
410486b82fe0SRichard Henderson     tcg_gen_mov_tl(cpu_npc, src);
410586b82fe0SRichard Henderson     gen_helper_rett(tcg_env);
410686b82fe0SRichard Henderson 
410786b82fe0SRichard Henderson     dc->npc = DYNAMIC_PC;
410886b82fe0SRichard Henderson     return true;
410986b82fe0SRichard Henderson }
411086b82fe0SRichard Henderson 
411186b82fe0SRichard Henderson TRANS(RETT, 32, do_add_special, a, do_rett)
411286b82fe0SRichard Henderson 
411386b82fe0SRichard Henderson static bool do_return(DisasContext *dc, int rd, TCGv src)
411486b82fe0SRichard Henderson {
411586b82fe0SRichard Henderson     gen_check_align(dc, src, 3);
41160dfae4f9SRichard Henderson     gen_helper_restore(tcg_env);
411786b82fe0SRichard Henderson 
411886b82fe0SRichard Henderson     gen_mov_pc_npc(dc);
411986b82fe0SRichard Henderson     tcg_gen_mov_tl(cpu_npc, src);
412086b82fe0SRichard Henderson     gen_address_mask(dc, cpu_npc);
412186b82fe0SRichard Henderson 
412286b82fe0SRichard Henderson     dc->npc = DYNAMIC_PC_LOOKUP;
412386b82fe0SRichard Henderson     return true;
412486b82fe0SRichard Henderson }
412586b82fe0SRichard Henderson 
412686b82fe0SRichard Henderson TRANS(RETURN, 64, do_add_special, a, do_return)
412786b82fe0SRichard Henderson 
4128d3825800SRichard Henderson static bool do_save(DisasContext *dc, int rd, TCGv src)
4129d3825800SRichard Henderson {
4130d3825800SRichard Henderson     gen_helper_save(tcg_env);
4131d3825800SRichard Henderson     gen_store_gpr(dc, rd, src);
4132d3825800SRichard Henderson     return advance_pc(dc);
4133d3825800SRichard Henderson }
4134d3825800SRichard Henderson 
4135d3825800SRichard Henderson TRANS(SAVE, ALL, do_add_special, a, do_save)
4136d3825800SRichard Henderson 
4137d3825800SRichard Henderson static bool do_restore(DisasContext *dc, int rd, TCGv src)
4138d3825800SRichard Henderson {
4139d3825800SRichard Henderson     gen_helper_restore(tcg_env);
4140d3825800SRichard Henderson     gen_store_gpr(dc, rd, src);
4141d3825800SRichard Henderson     return advance_pc(dc);
4142d3825800SRichard Henderson }
4143d3825800SRichard Henderson 
4144d3825800SRichard Henderson TRANS(RESTORE, ALL, do_add_special, a, do_restore)
4145d3825800SRichard Henderson 
41468f75b8a4SRichard Henderson static bool do_done_retry(DisasContext *dc, bool done)
41478f75b8a4SRichard Henderson {
41488f75b8a4SRichard Henderson     if (!supervisor(dc)) {
41498f75b8a4SRichard Henderson         return raise_priv(dc);
41508f75b8a4SRichard Henderson     }
41518f75b8a4SRichard Henderson     dc->npc = DYNAMIC_PC;
41528f75b8a4SRichard Henderson     dc->pc = DYNAMIC_PC;
41538f75b8a4SRichard Henderson     translator_io_start(&dc->base);
41548f75b8a4SRichard Henderson     if (done) {
41558f75b8a4SRichard Henderson         gen_helper_done(tcg_env);
41568f75b8a4SRichard Henderson     } else {
41578f75b8a4SRichard Henderson         gen_helper_retry(tcg_env);
41588f75b8a4SRichard Henderson     }
41598f75b8a4SRichard Henderson     return true;
41608f75b8a4SRichard Henderson }
41618f75b8a4SRichard Henderson 
41628f75b8a4SRichard Henderson TRANS(DONE, 64, do_done_retry, true)
41638f75b8a4SRichard Henderson TRANS(RETRY, 64, do_done_retry, false)
41648f75b8a4SRichard Henderson 
41650880d20bSRichard Henderson /*
41660880d20bSRichard Henderson  * Major opcode 11 -- load and store instructions
41670880d20bSRichard Henderson  */
41680880d20bSRichard Henderson 
41690880d20bSRichard Henderson static TCGv gen_ldst_addr(DisasContext *dc, int rs1, bool imm, int rs2_or_imm)
41700880d20bSRichard Henderson {
41710880d20bSRichard Henderson     TCGv addr, tmp = NULL;
41720880d20bSRichard Henderson 
41730880d20bSRichard Henderson     /* For simplicity, we under-decoded the rs2 form. */
41740880d20bSRichard Henderson     if (!imm && rs2_or_imm & ~0x1f) {
41750880d20bSRichard Henderson         return NULL;
41760880d20bSRichard Henderson     }
41770880d20bSRichard Henderson 
41780880d20bSRichard Henderson     addr = gen_load_gpr(dc, rs1);
41790880d20bSRichard Henderson     if (rs2_or_imm) {
41800880d20bSRichard Henderson         tmp = tcg_temp_new();
41810880d20bSRichard Henderson         if (imm) {
41820880d20bSRichard Henderson             tcg_gen_addi_tl(tmp, addr, rs2_or_imm);
41830880d20bSRichard Henderson         } else {
41840880d20bSRichard Henderson             tcg_gen_add_tl(tmp, addr, cpu_regs[rs2_or_imm]);
41850880d20bSRichard Henderson         }
41860880d20bSRichard Henderson         addr = tmp;
41870880d20bSRichard Henderson     }
41880880d20bSRichard Henderson     if (AM_CHECK(dc)) {
41890880d20bSRichard Henderson         if (!tmp) {
41900880d20bSRichard Henderson             tmp = tcg_temp_new();
41910880d20bSRichard Henderson         }
41920880d20bSRichard Henderson         tcg_gen_ext32u_tl(tmp, addr);
41930880d20bSRichard Henderson         addr = tmp;
41940880d20bSRichard Henderson     }
41950880d20bSRichard Henderson     return addr;
41960880d20bSRichard Henderson }
41970880d20bSRichard Henderson 
41980880d20bSRichard Henderson static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
41990880d20bSRichard Henderson {
42000880d20bSRichard Henderson     TCGv reg, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
42010880d20bSRichard Henderson     DisasASI da;
42020880d20bSRichard Henderson 
42030880d20bSRichard Henderson     if (addr == NULL) {
42040880d20bSRichard Henderson         return false;
42050880d20bSRichard Henderson     }
42060880d20bSRichard Henderson     da = resolve_asi(dc, a->asi, mop);
42070880d20bSRichard Henderson 
42080880d20bSRichard Henderson     reg = gen_dest_gpr(dc, a->rd);
420942071fc1SRichard Henderson     gen_ld_asi(dc, &da, reg, addr);
42100880d20bSRichard Henderson     gen_store_gpr(dc, a->rd, reg);
42110880d20bSRichard Henderson     return advance_pc(dc);
42120880d20bSRichard Henderson }
42130880d20bSRichard Henderson 
42140880d20bSRichard Henderson TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL)
42150880d20bSRichard Henderson TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB)
42160880d20bSRichard Henderson TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW)
42170880d20bSRichard Henderson TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB)
42180880d20bSRichard Henderson TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW)
42190880d20bSRichard Henderson TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL)
42200880d20bSRichard Henderson TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ)
42210880d20bSRichard Henderson 
42220880d20bSRichard Henderson static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
42230880d20bSRichard Henderson {
42240880d20bSRichard Henderson     TCGv reg, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
42250880d20bSRichard Henderson     DisasASI da;
42260880d20bSRichard Henderson 
42270880d20bSRichard Henderson     if (addr == NULL) {
42280880d20bSRichard Henderson         return false;
42290880d20bSRichard Henderson     }
42300880d20bSRichard Henderson     da = resolve_asi(dc, a->asi, mop);
42310880d20bSRichard Henderson 
42320880d20bSRichard Henderson     reg = gen_load_gpr(dc, a->rd);
423342071fc1SRichard Henderson     gen_st_asi(dc, &da, reg, addr);
42340880d20bSRichard Henderson     return advance_pc(dc);
42350880d20bSRichard Henderson }
42360880d20bSRichard Henderson 
42370880d20bSRichard Henderson TRANS(STW, ALL, do_st_gpr, a, MO_TEUL)
42380880d20bSRichard Henderson TRANS(STB, ALL, do_st_gpr, a, MO_UB)
42390880d20bSRichard Henderson TRANS(STH, ALL, do_st_gpr, a, MO_TEUW)
42400880d20bSRichard Henderson TRANS(STX, 64, do_st_gpr, a, MO_TEUQ)
42410880d20bSRichard Henderson 
42420880d20bSRichard Henderson static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)
42430880d20bSRichard Henderson {
42440880d20bSRichard Henderson     TCGv addr;
42450880d20bSRichard Henderson     DisasASI da;
42460880d20bSRichard Henderson 
42470880d20bSRichard Henderson     if (a->rd & 1) {
42480880d20bSRichard Henderson         return false;
42490880d20bSRichard Henderson     }
42500880d20bSRichard Henderson     addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
42510880d20bSRichard Henderson     if (addr == NULL) {
42520880d20bSRichard Henderson         return false;
42530880d20bSRichard Henderson     }
42540880d20bSRichard Henderson     da = resolve_asi(dc, a->asi, MO_TEUQ);
425542071fc1SRichard Henderson     gen_ldda_asi(dc, &da, addr, a->rd);
42560880d20bSRichard Henderson     return advance_pc(dc);
42570880d20bSRichard Henderson }
42580880d20bSRichard Henderson 
42590880d20bSRichard Henderson static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a)
42600880d20bSRichard Henderson {
42610880d20bSRichard Henderson     TCGv addr;
42620880d20bSRichard Henderson     DisasASI da;
42630880d20bSRichard Henderson 
42640880d20bSRichard Henderson     if (a->rd & 1) {
42650880d20bSRichard Henderson         return false;
42660880d20bSRichard Henderson     }
42670880d20bSRichard Henderson     addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
42680880d20bSRichard Henderson     if (addr == NULL) {
42690880d20bSRichard Henderson         return false;
42700880d20bSRichard Henderson     }
42710880d20bSRichard Henderson     da = resolve_asi(dc, a->asi, MO_TEUQ);
427242071fc1SRichard Henderson     gen_stda_asi(dc, &da, addr, a->rd);
42730880d20bSRichard Henderson     return advance_pc(dc);
42740880d20bSRichard Henderson }
42750880d20bSRichard Henderson 
4276cf07cd1eSRichard Henderson static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a)
4277cf07cd1eSRichard Henderson {
4278cf07cd1eSRichard Henderson     TCGv addr, reg;
4279cf07cd1eSRichard Henderson     DisasASI da;
4280cf07cd1eSRichard Henderson 
4281cf07cd1eSRichard Henderson     addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
4282cf07cd1eSRichard Henderson     if (addr == NULL) {
4283cf07cd1eSRichard Henderson         return false;
4284cf07cd1eSRichard Henderson     }
4285cf07cd1eSRichard Henderson     da = resolve_asi(dc, a->asi, MO_UB);
4286cf07cd1eSRichard Henderson 
4287cf07cd1eSRichard Henderson     reg = gen_dest_gpr(dc, a->rd);
4288cf07cd1eSRichard Henderson     gen_ldstub_asi(dc, &da, reg, addr);
4289cf07cd1eSRichard Henderson     gen_store_gpr(dc, a->rd, reg);
4290cf07cd1eSRichard Henderson     return advance_pc(dc);
4291cf07cd1eSRichard Henderson }
4292cf07cd1eSRichard Henderson 
4293dca544b9SRichard Henderson static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a)
4294dca544b9SRichard Henderson {
4295dca544b9SRichard Henderson     TCGv addr, dst, src;
4296dca544b9SRichard Henderson     DisasASI da;
4297dca544b9SRichard Henderson 
4298dca544b9SRichard Henderson     addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
4299dca544b9SRichard Henderson     if (addr == NULL) {
4300dca544b9SRichard Henderson         return false;
4301dca544b9SRichard Henderson     }
4302dca544b9SRichard Henderson     da = resolve_asi(dc, a->asi, MO_TEUL);
4303dca544b9SRichard Henderson 
4304dca544b9SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
4305dca544b9SRichard Henderson     src = gen_load_gpr(dc, a->rd);
4306dca544b9SRichard Henderson     gen_swap_asi(dc, &da, dst, src, addr);
4307dca544b9SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
4308dca544b9SRichard Henderson     return advance_pc(dc);
4309dca544b9SRichard Henderson }
4310dca544b9SRichard Henderson 
4311d0a11d25SRichard Henderson static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
4312d0a11d25SRichard Henderson {
4313d0a11d25SRichard Henderson     TCGv addr, o, n, c;
4314d0a11d25SRichard Henderson     DisasASI da;
4315d0a11d25SRichard Henderson 
4316d0a11d25SRichard Henderson     addr = gen_ldst_addr(dc, a->rs1, true, 0);
4317d0a11d25SRichard Henderson     if (addr == NULL) {
4318d0a11d25SRichard Henderson         return false;
4319d0a11d25SRichard Henderson     }
4320d0a11d25SRichard Henderson     da = resolve_asi(dc, a->asi, mop);
4321d0a11d25SRichard Henderson 
4322d0a11d25SRichard Henderson     o = gen_dest_gpr(dc, a->rd);
4323d0a11d25SRichard Henderson     n = gen_load_gpr(dc, a->rd);
4324d0a11d25SRichard Henderson     c = gen_load_gpr(dc, a->rs2_or_imm);
4325d0a11d25SRichard Henderson     gen_cas_asi(dc, &da, o, n, c, addr);
4326d0a11d25SRichard Henderson     gen_store_gpr(dc, a->rd, o);
4327d0a11d25SRichard Henderson     return advance_pc(dc);
4328d0a11d25SRichard Henderson }
4329d0a11d25SRichard Henderson 
4330d0a11d25SRichard Henderson TRANS(CASA, CASA, do_casa, a, MO_TEUL)
4331d0a11d25SRichard Henderson TRANS(CASXA, 64, do_casa, a, MO_TEUQ)
4332d0a11d25SRichard Henderson 
433306c060d9SRichard Henderson static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
433406c060d9SRichard Henderson {
433506c060d9SRichard Henderson     TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
433606c060d9SRichard Henderson     DisasASI da;
433706c060d9SRichard Henderson 
433806c060d9SRichard Henderson     if (addr == NULL) {
433906c060d9SRichard Henderson         return false;
434006c060d9SRichard Henderson     }
434106c060d9SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
434206c060d9SRichard Henderson         return true;
434306c060d9SRichard Henderson     }
434406c060d9SRichard Henderson     if (sz == MO_128 && gen_trap_float128(dc)) {
434506c060d9SRichard Henderson         return true;
434606c060d9SRichard Henderson     }
434706c060d9SRichard Henderson     da = resolve_asi(dc, a->asi, MO_TE | sz);
4348287b1152SRichard Henderson     gen_ldf_asi(dc, &da, sz, addr, a->rd);
434906c060d9SRichard Henderson     gen_update_fprs_dirty(dc, a->rd);
435006c060d9SRichard Henderson     return advance_pc(dc);
435106c060d9SRichard Henderson }
435206c060d9SRichard Henderson 
435306c060d9SRichard Henderson TRANS(LDF, ALL, do_ld_fpr, a, MO_32)
435406c060d9SRichard Henderson TRANS(LDDF, ALL, do_ld_fpr, a, MO_64)
435506c060d9SRichard Henderson TRANS(LDQF, ALL, do_ld_fpr, a, MO_128)
435606c060d9SRichard Henderson 
4357287b1152SRichard Henderson TRANS(LDFA, 64, do_ld_fpr, a, MO_32)
4358287b1152SRichard Henderson TRANS(LDDFA, 64, do_ld_fpr, a, MO_64)
4359287b1152SRichard Henderson TRANS(LDQFA, 64, do_ld_fpr, a, MO_128)
4360287b1152SRichard Henderson 
436106c060d9SRichard Henderson static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
436206c060d9SRichard Henderson {
436306c060d9SRichard Henderson     TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
436406c060d9SRichard Henderson     DisasASI da;
436506c060d9SRichard Henderson 
436606c060d9SRichard Henderson     if (addr == NULL) {
436706c060d9SRichard Henderson         return false;
436806c060d9SRichard Henderson     }
436906c060d9SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
437006c060d9SRichard Henderson         return true;
437106c060d9SRichard Henderson     }
437206c060d9SRichard Henderson     if (sz == MO_128 && gen_trap_float128(dc)) {
437306c060d9SRichard Henderson         return true;
437406c060d9SRichard Henderson     }
437506c060d9SRichard Henderson     da = resolve_asi(dc, a->asi, MO_TE | sz);
4376287b1152SRichard Henderson     gen_stf_asi(dc, &da, sz, addr, a->rd);
437706c060d9SRichard Henderson     return advance_pc(dc);
437806c060d9SRichard Henderson }
437906c060d9SRichard Henderson 
438006c060d9SRichard Henderson TRANS(STF, ALL, do_st_fpr, a, MO_32)
438106c060d9SRichard Henderson TRANS(STDF, ALL, do_st_fpr, a, MO_64)
438206c060d9SRichard Henderson TRANS(STQF, ALL, do_st_fpr, a, MO_128)
438306c060d9SRichard Henderson 
4384287b1152SRichard Henderson TRANS(STFA, 64, do_st_fpr, a, MO_32)
4385287b1152SRichard Henderson TRANS(STDFA, 64, do_st_fpr, a, MO_64)
4386287b1152SRichard Henderson TRANS(STQFA, 64, do_st_fpr, a, MO_128)
4387287b1152SRichard Henderson 
438806c060d9SRichard Henderson static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
438906c060d9SRichard Henderson {
439006c060d9SRichard Henderson     if (!avail_32(dc)) {
439106c060d9SRichard Henderson         return false;
439206c060d9SRichard Henderson     }
439306c060d9SRichard Henderson     if (!supervisor(dc)) {
439406c060d9SRichard Henderson         return raise_priv(dc);
439506c060d9SRichard Henderson     }
439606c060d9SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
439706c060d9SRichard Henderson         return true;
439806c060d9SRichard Henderson     }
439906c060d9SRichard Henderson     gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
440006c060d9SRichard Henderson     return true;
440106c060d9SRichard Henderson }
440206c060d9SRichard Henderson 
4403da681406SRichard Henderson static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop,
4404da681406SRichard Henderson                      target_ulong new_mask, target_ulong old_mask)
44053d3c0673SRichard Henderson {
4406da681406SRichard Henderson     TCGv tmp, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
44073d3c0673SRichard Henderson     if (addr == NULL) {
44083d3c0673SRichard Henderson         return false;
44093d3c0673SRichard Henderson     }
44103d3c0673SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
44113d3c0673SRichard Henderson         return true;
44123d3c0673SRichard Henderson     }
4413da681406SRichard Henderson     tmp = tcg_temp_new();
4414da681406SRichard Henderson     tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN);
4415da681406SRichard Henderson     tcg_gen_andi_tl(tmp, tmp, new_mask);
4416da681406SRichard Henderson     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask);
4417da681406SRichard Henderson     tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp);
4418da681406SRichard Henderson     gen_helper_set_fsr(tcg_env, cpu_fsr);
44193d3c0673SRichard Henderson     return advance_pc(dc);
44203d3c0673SRichard Henderson }
44213d3c0673SRichard Henderson 
4422da681406SRichard Henderson TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK)
4423da681406SRichard Henderson TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMASK)
44243d3c0673SRichard Henderson 
44253d3c0673SRichard Henderson static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
44263d3c0673SRichard Henderson {
44273d3c0673SRichard Henderson     TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
44283d3c0673SRichard Henderson     if (addr == NULL) {
44293d3c0673SRichard Henderson         return false;
44303d3c0673SRichard Henderson     }
44313d3c0673SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
44323d3c0673SRichard Henderson         return true;
44333d3c0673SRichard Henderson     }
44343d3c0673SRichard Henderson     tcg_gen_qemu_st_tl(cpu_fsr, addr, dc->mem_idx, mop | MO_ALIGN);
44353d3c0673SRichard Henderson     return advance_pc(dc);
44363d3c0673SRichard Henderson }
44373d3c0673SRichard Henderson 
44383d3c0673SRichard Henderson TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL)
44393d3c0673SRichard Henderson TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ)
44403d3c0673SRichard Henderson 
44413a38260eSRichard Henderson static bool do_fc(DisasContext *dc, int rd, bool c)
44423a38260eSRichard Henderson {
44433a38260eSRichard Henderson     uint64_t mask;
44443a38260eSRichard Henderson 
44453a38260eSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
44463a38260eSRichard Henderson         return true;
44473a38260eSRichard Henderson     }
44483a38260eSRichard Henderson 
44493a38260eSRichard Henderson     if (rd & 1) {
44503a38260eSRichard Henderson         mask = MAKE_64BIT_MASK(0, 32);
44513a38260eSRichard Henderson     } else {
44523a38260eSRichard Henderson         mask = MAKE_64BIT_MASK(32, 32);
44533a38260eSRichard Henderson     }
44543a38260eSRichard Henderson     if (c) {
44553a38260eSRichard Henderson         tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask);
44563a38260eSRichard Henderson     } else {
44573a38260eSRichard Henderson         tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask);
44583a38260eSRichard Henderson     }
44593a38260eSRichard Henderson     gen_update_fprs_dirty(dc, rd);
44603a38260eSRichard Henderson     return advance_pc(dc);
44613a38260eSRichard Henderson }
44623a38260eSRichard Henderson 
44633a38260eSRichard Henderson TRANS(FZEROs, VIS1, do_fc, a->rd, 0)
44643a38260eSRichard Henderson TRANS(FONEs, VIS1, do_fc, a->rd, 1)
44653a38260eSRichard Henderson 
44663a38260eSRichard Henderson static bool do_dc(DisasContext *dc, int rd, int64_t c)
44673a38260eSRichard Henderson {
44683a38260eSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
44693a38260eSRichard Henderson         return true;
44703a38260eSRichard Henderson     }
44713a38260eSRichard Henderson 
44723a38260eSRichard Henderson     tcg_gen_movi_i64(cpu_fpr[rd / 2], c);
44733a38260eSRichard Henderson     gen_update_fprs_dirty(dc, rd);
44743a38260eSRichard Henderson     return advance_pc(dc);
44753a38260eSRichard Henderson }
44763a38260eSRichard Henderson 
44773a38260eSRichard Henderson TRANS(FZEROd, VIS1, do_dc, a->rd, 0)
44783a38260eSRichard Henderson TRANS(FONEd, VIS1, do_dc, a->rd, -1)
44793a38260eSRichard Henderson 
4480baf3dbf2SRichard Henderson static bool do_ff(DisasContext *dc, arg_r_r *a,
4481baf3dbf2SRichard Henderson                   void (*func)(TCGv_i32, TCGv_i32))
4482baf3dbf2SRichard Henderson {
4483baf3dbf2SRichard Henderson     TCGv_i32 tmp;
4484baf3dbf2SRichard Henderson 
4485baf3dbf2SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4486baf3dbf2SRichard Henderson         return true;
4487baf3dbf2SRichard Henderson     }
4488baf3dbf2SRichard Henderson 
4489baf3dbf2SRichard Henderson     tmp = gen_load_fpr_F(dc, a->rs);
4490baf3dbf2SRichard Henderson     func(tmp, tmp);
4491baf3dbf2SRichard Henderson     gen_store_fpr_F(dc, a->rd, tmp);
4492baf3dbf2SRichard Henderson     return advance_pc(dc);
4493baf3dbf2SRichard Henderson }
4494baf3dbf2SRichard Henderson 
4495baf3dbf2SRichard Henderson TRANS(FMOVs, ALL, do_ff, a, gen_op_fmovs)
4496baf3dbf2SRichard Henderson TRANS(FNEGs, ALL, do_ff, a, gen_op_fnegs)
4497baf3dbf2SRichard Henderson TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
4498baf3dbf2SRichard Henderson TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
4499baf3dbf2SRichard Henderson TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
4500baf3dbf2SRichard Henderson 
45012f722641SRichard Henderson static bool do_fd(DisasContext *dc, arg_r_r *a,
45022f722641SRichard Henderson                   void (*func)(TCGv_i32, TCGv_i64))
45032f722641SRichard Henderson {
45042f722641SRichard Henderson     TCGv_i32 dst;
45052f722641SRichard Henderson     TCGv_i64 src;
45062f722641SRichard Henderson 
45072f722641SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
45082f722641SRichard Henderson         return true;
45092f722641SRichard Henderson     }
45102f722641SRichard Henderson 
4511388a6465SRichard Henderson     dst = tcg_temp_new_i32();
45122f722641SRichard Henderson     src = gen_load_fpr_D(dc, a->rs);
45132f722641SRichard Henderson     func(dst, src);
45142f722641SRichard Henderson     gen_store_fpr_F(dc, a->rd, dst);
45152f722641SRichard Henderson     return advance_pc(dc);
45162f722641SRichard Henderson }
45172f722641SRichard Henderson 
45182f722641SRichard Henderson TRANS(FPACK16, VIS1, do_fd, a, gen_op_fpack16)
45192f722641SRichard Henderson TRANS(FPACKFIX, VIS1, do_fd, a, gen_op_fpackfix)
45202f722641SRichard Henderson 
4521119cb94fSRichard Henderson static bool do_env_ff(DisasContext *dc, arg_r_r *a,
4522119cb94fSRichard Henderson                       void (*func)(TCGv_i32, TCGv_env, TCGv_i32))
4523119cb94fSRichard Henderson {
4524119cb94fSRichard Henderson     TCGv_i32 tmp;
4525119cb94fSRichard Henderson 
4526119cb94fSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4527119cb94fSRichard Henderson         return true;
4528119cb94fSRichard Henderson     }
4529119cb94fSRichard Henderson 
4530119cb94fSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4531119cb94fSRichard Henderson     tmp = gen_load_fpr_F(dc, a->rs);
4532119cb94fSRichard Henderson     func(tmp, tcg_env, tmp);
4533119cb94fSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4534119cb94fSRichard Henderson     gen_store_fpr_F(dc, a->rd, tmp);
4535119cb94fSRichard Henderson     return advance_pc(dc);
4536119cb94fSRichard Henderson }
4537119cb94fSRichard Henderson 
4538119cb94fSRichard Henderson TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts)
4539119cb94fSRichard Henderson TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos)
4540119cb94fSRichard Henderson TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi)
4541119cb94fSRichard Henderson 
45428c94bcd8SRichard Henderson static bool do_env_fd(DisasContext *dc, arg_r_r *a,
45438c94bcd8SRichard Henderson                       void (*func)(TCGv_i32, TCGv_env, TCGv_i64))
45448c94bcd8SRichard Henderson {
45458c94bcd8SRichard Henderson     TCGv_i32 dst;
45468c94bcd8SRichard Henderson     TCGv_i64 src;
45478c94bcd8SRichard Henderson 
45488c94bcd8SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
45498c94bcd8SRichard Henderson         return true;
45508c94bcd8SRichard Henderson     }
45518c94bcd8SRichard Henderson 
45528c94bcd8SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4553388a6465SRichard Henderson     dst = tcg_temp_new_i32();
45548c94bcd8SRichard Henderson     src = gen_load_fpr_D(dc, a->rs);
45558c94bcd8SRichard Henderson     func(dst, tcg_env, src);
45568c94bcd8SRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
45578c94bcd8SRichard Henderson     gen_store_fpr_F(dc, a->rd, dst);
45588c94bcd8SRichard Henderson     return advance_pc(dc);
45598c94bcd8SRichard Henderson }
45608c94bcd8SRichard Henderson 
45618c94bcd8SRichard Henderson TRANS(FdTOs, ALL, do_env_fd, a, gen_helper_fdtos)
45628c94bcd8SRichard Henderson TRANS(FdTOi, ALL, do_env_fd, a, gen_helper_fdtoi)
45638c94bcd8SRichard Henderson TRANS(FxTOs, 64, do_env_fd, a, gen_helper_fxtos)
45648c94bcd8SRichard Henderson 
4565c6d83e4fSRichard Henderson static bool do_dd(DisasContext *dc, arg_r_r *a,
4566c6d83e4fSRichard Henderson                   void (*func)(TCGv_i64, TCGv_i64))
4567c6d83e4fSRichard Henderson {
4568c6d83e4fSRichard Henderson     TCGv_i64 dst, src;
4569c6d83e4fSRichard Henderson 
4570c6d83e4fSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4571c6d83e4fSRichard Henderson         return true;
4572c6d83e4fSRichard Henderson     }
4573c6d83e4fSRichard Henderson 
4574c6d83e4fSRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
4575c6d83e4fSRichard Henderson     src = gen_load_fpr_D(dc, a->rs);
4576c6d83e4fSRichard Henderson     func(dst, src);
4577c6d83e4fSRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4578c6d83e4fSRichard Henderson     return advance_pc(dc);
4579c6d83e4fSRichard Henderson }
4580c6d83e4fSRichard Henderson 
4581c6d83e4fSRichard Henderson TRANS(FMOVd, 64, do_dd, a, gen_op_fmovd)
4582c6d83e4fSRichard Henderson TRANS(FNEGd, 64, do_dd, a, gen_op_fnegd)
4583c6d83e4fSRichard Henderson TRANS(FABSd, 64, do_dd, a, gen_op_fabsd)
4584c6d83e4fSRichard Henderson TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64)
4585c6d83e4fSRichard Henderson TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64)
4586c6d83e4fSRichard Henderson 
45878aa418b3SRichard Henderson static bool do_env_dd(DisasContext *dc, arg_r_r *a,
45888aa418b3SRichard Henderson                       void (*func)(TCGv_i64, TCGv_env, TCGv_i64))
45898aa418b3SRichard Henderson {
45908aa418b3SRichard Henderson     TCGv_i64 dst, src;
45918aa418b3SRichard Henderson 
45928aa418b3SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
45938aa418b3SRichard Henderson         return true;
45948aa418b3SRichard Henderson     }
45958aa418b3SRichard Henderson 
45968aa418b3SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
45978aa418b3SRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
45988aa418b3SRichard Henderson     src = gen_load_fpr_D(dc, a->rs);
45998aa418b3SRichard Henderson     func(dst, tcg_env, src);
46008aa418b3SRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
46018aa418b3SRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
46028aa418b3SRichard Henderson     return advance_pc(dc);
46038aa418b3SRichard Henderson }
46048aa418b3SRichard Henderson 
46058aa418b3SRichard Henderson TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd)
46068aa418b3SRichard Henderson TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod)
46078aa418b3SRichard Henderson TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox)
46088aa418b3SRichard Henderson 
4609199d43efSRichard Henderson static bool do_env_df(DisasContext *dc, arg_r_r *a,
4610199d43efSRichard Henderson                       void (*func)(TCGv_i64, TCGv_env, TCGv_i32))
4611199d43efSRichard Henderson {
4612199d43efSRichard Henderson     TCGv_i64 dst;
4613199d43efSRichard Henderson     TCGv_i32 src;
4614199d43efSRichard Henderson 
4615199d43efSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4616199d43efSRichard Henderson         return true;
4617199d43efSRichard Henderson     }
4618199d43efSRichard Henderson 
4619199d43efSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4620199d43efSRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
4621199d43efSRichard Henderson     src = gen_load_fpr_F(dc, a->rs);
4622199d43efSRichard Henderson     func(dst, tcg_env, src);
4623199d43efSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4624199d43efSRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4625199d43efSRichard Henderson     return advance_pc(dc);
4626199d43efSRichard Henderson }
4627199d43efSRichard Henderson 
4628199d43efSRichard Henderson TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod)
4629199d43efSRichard Henderson TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod)
4630199d43efSRichard Henderson TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox)
4631199d43efSRichard Henderson 
4632daf457d4SRichard Henderson static bool do_qq(DisasContext *dc, arg_r_r *a,
4633daf457d4SRichard Henderson                   void (*func)(TCGv_i128, TCGv_i128))
4634f4e18df5SRichard Henderson {
463533ec4245SRichard Henderson     TCGv_i128 t;
4636f4e18df5SRichard Henderson 
4637f4e18df5SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4638f4e18df5SRichard Henderson         return true;
4639f4e18df5SRichard Henderson     }
4640f4e18df5SRichard Henderson     if (gen_trap_float128(dc)) {
4641f4e18df5SRichard Henderson         return true;
4642f4e18df5SRichard Henderson     }
4643f4e18df5SRichard Henderson 
4644f4e18df5SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
464533ec4245SRichard Henderson     t = gen_load_fpr_Q(dc, a->rs);
4646daf457d4SRichard Henderson     func(t, t);
464733ec4245SRichard Henderson     gen_store_fpr_Q(dc, a->rd, t);
4648f4e18df5SRichard Henderson     return advance_pc(dc);
4649f4e18df5SRichard Henderson }
4650f4e18df5SRichard Henderson 
4651daf457d4SRichard Henderson TRANS(FMOVq, 64, do_qq, a, tcg_gen_mov_i128)
4652daf457d4SRichard Henderson TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq)
4653daf457d4SRichard Henderson TRANS(FABSq, 64, do_qq, a, gen_op_fabsq)
4654f4e18df5SRichard Henderson 
4655c995216bSRichard Henderson static bool do_env_qq(DisasContext *dc, arg_r_r *a,
4656e41716beSRichard Henderson                       void (*func)(TCGv_i128, TCGv_env, TCGv_i128))
4657c995216bSRichard Henderson {
4658e41716beSRichard Henderson     TCGv_i128 t;
4659e41716beSRichard Henderson 
4660c995216bSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4661c995216bSRichard Henderson         return true;
4662c995216bSRichard Henderson     }
4663c995216bSRichard Henderson     if (gen_trap_float128(dc)) {
4664c995216bSRichard Henderson         return true;
4665c995216bSRichard Henderson     }
4666c995216bSRichard Henderson 
4667c995216bSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4668e41716beSRichard Henderson 
4669e41716beSRichard Henderson     t = gen_load_fpr_Q(dc, a->rs);
4670e41716beSRichard Henderson     func(t, tcg_env, t);
4671c995216bSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4672e41716beSRichard Henderson     gen_store_fpr_Q(dc, a->rd, t);
4673c995216bSRichard Henderson     return advance_pc(dc);
4674c995216bSRichard Henderson }
4675c995216bSRichard Henderson 
4676c995216bSRichard Henderson TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq)
4677c995216bSRichard Henderson 
4678bd9c5c42SRichard Henderson static bool do_env_fq(DisasContext *dc, arg_r_r *a,
4679d81e3efeSRichard Henderson                       void (*func)(TCGv_i32, TCGv_env, TCGv_i128))
4680bd9c5c42SRichard Henderson {
4681d81e3efeSRichard Henderson     TCGv_i128 src;
4682bd9c5c42SRichard Henderson     TCGv_i32 dst;
4683bd9c5c42SRichard Henderson 
4684bd9c5c42SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4685bd9c5c42SRichard Henderson         return true;
4686bd9c5c42SRichard Henderson     }
4687bd9c5c42SRichard Henderson     if (gen_trap_float128(dc)) {
4688bd9c5c42SRichard Henderson         return true;
4689bd9c5c42SRichard Henderson     }
4690bd9c5c42SRichard Henderson 
4691bd9c5c42SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4692d81e3efeSRichard Henderson     src = gen_load_fpr_Q(dc, a->rs);
4693388a6465SRichard Henderson     dst = tcg_temp_new_i32();
4694d81e3efeSRichard Henderson     func(dst, tcg_env, src);
4695bd9c5c42SRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4696bd9c5c42SRichard Henderson     gen_store_fpr_F(dc, a->rd, dst);
4697bd9c5c42SRichard Henderson     return advance_pc(dc);
4698bd9c5c42SRichard Henderson }
4699bd9c5c42SRichard Henderson 
4700bd9c5c42SRichard Henderson TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos)
4701bd9c5c42SRichard Henderson TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi)
4702bd9c5c42SRichard Henderson 
47031617586fSRichard Henderson static bool do_env_dq(DisasContext *dc, arg_r_r *a,
470425a5769eSRichard Henderson                       void (*func)(TCGv_i64, TCGv_env, TCGv_i128))
47051617586fSRichard Henderson {
470625a5769eSRichard Henderson     TCGv_i128 src;
47071617586fSRichard Henderson     TCGv_i64 dst;
47081617586fSRichard Henderson 
47091617586fSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
47101617586fSRichard Henderson         return true;
47111617586fSRichard Henderson     }
47121617586fSRichard Henderson     if (gen_trap_float128(dc)) {
47131617586fSRichard Henderson         return true;
47141617586fSRichard Henderson     }
47151617586fSRichard Henderson 
47161617586fSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
471725a5769eSRichard Henderson     src = gen_load_fpr_Q(dc, a->rs);
47181617586fSRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
471925a5769eSRichard Henderson     func(dst, tcg_env, src);
47201617586fSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
47211617586fSRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
47221617586fSRichard Henderson     return advance_pc(dc);
47231617586fSRichard Henderson }
47241617586fSRichard Henderson 
47251617586fSRichard Henderson TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod)
47261617586fSRichard Henderson TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox)
47271617586fSRichard Henderson 
472813ebcc77SRichard Henderson static bool do_env_qf(DisasContext *dc, arg_r_r *a,
4729*0b2a61ccSRichard Henderson                       void (*func)(TCGv_i128, TCGv_env, TCGv_i32))
473013ebcc77SRichard Henderson {
473113ebcc77SRichard Henderson     TCGv_i32 src;
4732*0b2a61ccSRichard Henderson     TCGv_i128 dst;
473313ebcc77SRichard Henderson 
473413ebcc77SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
473513ebcc77SRichard Henderson         return true;
473613ebcc77SRichard Henderson     }
473713ebcc77SRichard Henderson     if (gen_trap_float128(dc)) {
473813ebcc77SRichard Henderson         return true;
473913ebcc77SRichard Henderson     }
474013ebcc77SRichard Henderson 
474113ebcc77SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
474213ebcc77SRichard Henderson     src = gen_load_fpr_F(dc, a->rs);
4743*0b2a61ccSRichard Henderson     dst = tcg_temp_new_i128();
4744*0b2a61ccSRichard Henderson     func(dst, tcg_env, src);
4745*0b2a61ccSRichard Henderson     gen_store_fpr_Q(dc, a->rd, dst);
474613ebcc77SRichard Henderson     return advance_pc(dc);
474713ebcc77SRichard Henderson }
474813ebcc77SRichard Henderson 
474913ebcc77SRichard Henderson TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq)
475013ebcc77SRichard Henderson TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq)
475113ebcc77SRichard Henderson 
47527b8e3e1aSRichard Henderson static bool do_env_qd(DisasContext *dc, arg_r_r *a,
47537b8e3e1aSRichard Henderson                       void (*func)(TCGv_env, TCGv_i64))
47547b8e3e1aSRichard Henderson {
47557b8e3e1aSRichard Henderson     TCGv_i64 src;
47567b8e3e1aSRichard Henderson 
47577b8e3e1aSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
47587b8e3e1aSRichard Henderson         return true;
47597b8e3e1aSRichard Henderson     }
47607b8e3e1aSRichard Henderson     if (gen_trap_float128(dc)) {
47617b8e3e1aSRichard Henderson         return true;
47627b8e3e1aSRichard Henderson     }
47637b8e3e1aSRichard Henderson 
47647b8e3e1aSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
47657b8e3e1aSRichard Henderson     src = gen_load_fpr_D(dc, a->rs);
47667b8e3e1aSRichard Henderson     func(tcg_env, src);
47677b8e3e1aSRichard Henderson     gen_op_store_QT0_fpr(QFPREG(a->rd));
47687b8e3e1aSRichard Henderson     gen_update_fprs_dirty(dc, QFPREG(a->rd));
47697b8e3e1aSRichard Henderson     return advance_pc(dc);
47707b8e3e1aSRichard Henderson }
47717b8e3e1aSRichard Henderson 
47727b8e3e1aSRichard Henderson TRANS(FdTOq, ALL, do_env_qd, a, gen_helper_fdtoq)
47737b8e3e1aSRichard Henderson TRANS(FxTOq, 64, do_env_qd, a, gen_helper_fxtoq)
47747b8e3e1aSRichard Henderson 
47757f10b52fSRichard Henderson static bool do_fff(DisasContext *dc, arg_r_r_r *a,
47767f10b52fSRichard Henderson                    void (*func)(TCGv_i32, TCGv_i32, TCGv_i32))
47777f10b52fSRichard Henderson {
47787f10b52fSRichard Henderson     TCGv_i32 src1, src2;
47797f10b52fSRichard Henderson 
47807f10b52fSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
47817f10b52fSRichard Henderson         return true;
47827f10b52fSRichard Henderson     }
47837f10b52fSRichard Henderson 
47847f10b52fSRichard Henderson     src1 = gen_load_fpr_F(dc, a->rs1);
47857f10b52fSRichard Henderson     src2 = gen_load_fpr_F(dc, a->rs2);
47867f10b52fSRichard Henderson     func(src1, src1, src2);
47877f10b52fSRichard Henderson     gen_store_fpr_F(dc, a->rd, src1);
47887f10b52fSRichard Henderson     return advance_pc(dc);
47897f10b52fSRichard Henderson }
47907f10b52fSRichard Henderson 
47917f10b52fSRichard Henderson TRANS(FPADD16s, VIS1, do_fff, a, tcg_gen_vec_add16_i32)
47927f10b52fSRichard Henderson TRANS(FPADD32s, VIS1, do_fff, a, tcg_gen_add_i32)
47937f10b52fSRichard Henderson TRANS(FPSUB16s, VIS1, do_fff, a, tcg_gen_vec_sub16_i32)
47947f10b52fSRichard Henderson TRANS(FPSUB32s, VIS1, do_fff, a, tcg_gen_sub_i32)
47957f10b52fSRichard Henderson TRANS(FNORs, VIS1, do_fff, a, tcg_gen_nor_i32)
47967f10b52fSRichard Henderson TRANS(FANDNOTs, VIS1, do_fff, a, tcg_gen_andc_i32)
47977f10b52fSRichard Henderson TRANS(FXORs, VIS1, do_fff, a, tcg_gen_xor_i32)
47987f10b52fSRichard Henderson TRANS(FNANDs, VIS1, do_fff, a, tcg_gen_nand_i32)
47997f10b52fSRichard Henderson TRANS(FANDs, VIS1, do_fff, a, tcg_gen_and_i32)
48007f10b52fSRichard Henderson TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32)
48017f10b52fSRichard Henderson TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32)
48027f10b52fSRichard Henderson TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32)
48037f10b52fSRichard Henderson 
4804c1514961SRichard Henderson static bool do_env_fff(DisasContext *dc, arg_r_r_r *a,
4805c1514961SRichard Henderson                        void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
4806c1514961SRichard Henderson {
4807c1514961SRichard Henderson     TCGv_i32 src1, src2;
4808c1514961SRichard Henderson 
4809c1514961SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4810c1514961SRichard Henderson         return true;
4811c1514961SRichard Henderson     }
4812c1514961SRichard Henderson 
4813c1514961SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4814c1514961SRichard Henderson     src1 = gen_load_fpr_F(dc, a->rs1);
4815c1514961SRichard Henderson     src2 = gen_load_fpr_F(dc, a->rs2);
4816c1514961SRichard Henderson     func(src1, tcg_env, src1, src2);
4817c1514961SRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4818c1514961SRichard Henderson     gen_store_fpr_F(dc, a->rd, src1);
4819c1514961SRichard Henderson     return advance_pc(dc);
4820c1514961SRichard Henderson }
4821c1514961SRichard Henderson 
4822c1514961SRichard Henderson TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds)
4823c1514961SRichard Henderson TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs)
4824c1514961SRichard Henderson TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls)
4825c1514961SRichard Henderson TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs)
4826c1514961SRichard Henderson 
4827e06c9f83SRichard Henderson static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
4828e06c9f83SRichard Henderson                    void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
4829e06c9f83SRichard Henderson {
4830e06c9f83SRichard Henderson     TCGv_i64 dst, src1, src2;
4831e06c9f83SRichard Henderson 
4832e06c9f83SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4833e06c9f83SRichard Henderson         return true;
4834e06c9f83SRichard Henderson     }
4835e06c9f83SRichard Henderson 
4836e06c9f83SRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
4837e06c9f83SRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
4838e06c9f83SRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
4839e06c9f83SRichard Henderson     func(dst, src1, src2);
4840e06c9f83SRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4841e06c9f83SRichard Henderson     return advance_pc(dc);
4842e06c9f83SRichard Henderson }
4843e06c9f83SRichard Henderson 
4844e06c9f83SRichard Henderson TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16)
4845e06c9f83SRichard Henderson TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au)
4846e06c9f83SRichard Henderson TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al)
4847e06c9f83SRichard Henderson TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16)
4848e06c9f83SRichard Henderson TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16)
4849e06c9f83SRichard Henderson TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16)
4850e06c9f83SRichard Henderson TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16)
4851e06c9f83SRichard Henderson TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge)
4852e06c9f83SRichard Henderson TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand)
4853e06c9f83SRichard Henderson 
4854e06c9f83SRichard Henderson TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64)
4855e06c9f83SRichard Henderson TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64)
4856e06c9f83SRichard Henderson TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64)
4857e06c9f83SRichard Henderson TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64)
4858e06c9f83SRichard Henderson TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64)
4859e06c9f83SRichard Henderson TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64)
4860e06c9f83SRichard Henderson TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64)
4861e06c9f83SRichard Henderson TRANS(FNANDd, VIS1, do_ddd, a, tcg_gen_nand_i64)
4862e06c9f83SRichard Henderson TRANS(FANDd, VIS1, do_ddd, a, tcg_gen_and_i64)
4863e06c9f83SRichard Henderson TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64)
4864e06c9f83SRichard Henderson TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64)
4865e06c9f83SRichard Henderson TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64)
4866e06c9f83SRichard Henderson 
48674b6edc0aSRichard Henderson TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32)
48684b6edc0aSRichard Henderson TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata)
48694b6edc0aSRichard Henderson TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle)
48704b6edc0aSRichard Henderson 
4871e2fa6bd1SRichard Henderson static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
4872e2fa6bd1SRichard Henderson                    void (*func)(TCGv, TCGv_i64, TCGv_i64))
4873e2fa6bd1SRichard Henderson {
4874e2fa6bd1SRichard Henderson     TCGv_i64 src1, src2;
4875e2fa6bd1SRichard Henderson     TCGv dst;
4876e2fa6bd1SRichard Henderson 
4877e2fa6bd1SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4878e2fa6bd1SRichard Henderson         return true;
4879e2fa6bd1SRichard Henderson     }
4880e2fa6bd1SRichard Henderson 
4881e2fa6bd1SRichard Henderson     dst = gen_dest_gpr(dc, a->rd);
4882e2fa6bd1SRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
4883e2fa6bd1SRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
4884e2fa6bd1SRichard Henderson     func(dst, src1, src2);
4885e2fa6bd1SRichard Henderson     gen_store_gpr(dc, a->rd, dst);
4886e2fa6bd1SRichard Henderson     return advance_pc(dc);
4887e2fa6bd1SRichard Henderson }
4888e2fa6bd1SRichard Henderson 
4889e2fa6bd1SRichard Henderson TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple16)
4890e2fa6bd1SRichard Henderson TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16)
4891e2fa6bd1SRichard Henderson TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16)
4892e2fa6bd1SRichard Henderson TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16)
4893e2fa6bd1SRichard Henderson 
4894e2fa6bd1SRichard Henderson TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32)
4895e2fa6bd1SRichard Henderson TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32)
4896e2fa6bd1SRichard Henderson TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32)
4897e2fa6bd1SRichard Henderson TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32)
4898e2fa6bd1SRichard Henderson 
4899f2a59b0aSRichard Henderson static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
4900f2a59b0aSRichard Henderson                        void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
4901f2a59b0aSRichard Henderson {
4902f2a59b0aSRichard Henderson     TCGv_i64 dst, src1, src2;
4903f2a59b0aSRichard Henderson 
4904f2a59b0aSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4905f2a59b0aSRichard Henderson         return true;
4906f2a59b0aSRichard Henderson     }
4907f2a59b0aSRichard Henderson 
4908f2a59b0aSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4909f2a59b0aSRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
4910f2a59b0aSRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
4911f2a59b0aSRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
4912f2a59b0aSRichard Henderson     func(dst, tcg_env, src1, src2);
4913f2a59b0aSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4914f2a59b0aSRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4915f2a59b0aSRichard Henderson     return advance_pc(dc);
4916f2a59b0aSRichard Henderson }
4917f2a59b0aSRichard Henderson 
4918f2a59b0aSRichard Henderson TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd)
4919f2a59b0aSRichard Henderson TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd)
4920f2a59b0aSRichard Henderson TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld)
4921f2a59b0aSRichard Henderson TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd)
4922f2a59b0aSRichard Henderson 
4923ff4c711bSRichard Henderson static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a)
4924ff4c711bSRichard Henderson {
4925ff4c711bSRichard Henderson     TCGv_i64 dst;
4926ff4c711bSRichard Henderson     TCGv_i32 src1, src2;
4927ff4c711bSRichard Henderson 
4928ff4c711bSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4929ff4c711bSRichard Henderson         return true;
4930ff4c711bSRichard Henderson     }
4931ff4c711bSRichard Henderson     if (!(dc->def->features & CPU_FEATURE_FSMULD)) {
4932ff4c711bSRichard Henderson         return raise_unimpfpop(dc);
4933ff4c711bSRichard Henderson     }
4934ff4c711bSRichard Henderson 
4935ff4c711bSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
4936ff4c711bSRichard Henderson     dst = gen_dest_fpr_D(dc, a->rd);
4937ff4c711bSRichard Henderson     src1 = gen_load_fpr_F(dc, a->rs1);
4938ff4c711bSRichard Henderson     src2 = gen_load_fpr_F(dc, a->rs2);
4939ff4c711bSRichard Henderson     gen_helper_fsmuld(dst, tcg_env, src1, src2);
4940ff4c711bSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4941ff4c711bSRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4942ff4c711bSRichard Henderson     return advance_pc(dc);
4943ff4c711bSRichard Henderson }
4944ff4c711bSRichard Henderson 
4945afb04344SRichard Henderson static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
4946afb04344SRichard Henderson                     void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
4947afb04344SRichard Henderson {
4948afb04344SRichard Henderson     TCGv_i64 dst, src0, src1, src2;
4949afb04344SRichard Henderson 
4950afb04344SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4951afb04344SRichard Henderson         return true;
4952afb04344SRichard Henderson     }
4953afb04344SRichard Henderson 
4954afb04344SRichard Henderson     dst  = gen_dest_fpr_D(dc, a->rd);
4955afb04344SRichard Henderson     src0 = gen_load_fpr_D(dc, a->rd);
4956afb04344SRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
4957afb04344SRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
4958afb04344SRichard Henderson     func(dst, src0, src1, src2);
4959afb04344SRichard Henderson     gen_store_fpr_D(dc, a->rd, dst);
4960afb04344SRichard Henderson     return advance_pc(dc);
4961afb04344SRichard Henderson }
4962afb04344SRichard Henderson 
4963afb04344SRichard Henderson TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist)
4964afb04344SRichard Henderson 
4965a4056239SRichard Henderson static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a,
496616bedf89SRichard Henderson                        void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i128))
4967a4056239SRichard Henderson {
496816bedf89SRichard Henderson     TCGv_i128 src1, src2;
496916bedf89SRichard Henderson 
4970a4056239SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
4971a4056239SRichard Henderson         return true;
4972a4056239SRichard Henderson     }
4973a4056239SRichard Henderson     if (gen_trap_float128(dc)) {
4974a4056239SRichard Henderson         return true;
4975a4056239SRichard Henderson     }
4976a4056239SRichard Henderson 
4977a4056239SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
497816bedf89SRichard Henderson     src1 = gen_load_fpr_Q(dc, a->rs1);
497916bedf89SRichard Henderson     src2 = gen_load_fpr_Q(dc, a->rs2);
498016bedf89SRichard Henderson     func(src1, tcg_env, src1, src2);
4981a4056239SRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
498216bedf89SRichard Henderson     gen_store_fpr_Q(dc, a->rd, src1);
4983a4056239SRichard Henderson     return advance_pc(dc);
4984a4056239SRichard Henderson }
4985a4056239SRichard Henderson 
4986a4056239SRichard Henderson TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq)
4987a4056239SRichard Henderson TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq)
4988a4056239SRichard Henderson TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq)
4989a4056239SRichard Henderson TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
4990a4056239SRichard Henderson 
49915e3b17bbSRichard Henderson static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
49925e3b17bbSRichard Henderson {
49935e3b17bbSRichard Henderson     TCGv_i64 src1, src2;
49945e3b17bbSRichard Henderson 
49955e3b17bbSRichard Henderson     if (gen_trap_ifnofpu(dc)) {
49965e3b17bbSRichard Henderson         return true;
49975e3b17bbSRichard Henderson     }
49985e3b17bbSRichard Henderson     if (gen_trap_float128(dc)) {
49995e3b17bbSRichard Henderson         return true;
50005e3b17bbSRichard Henderson     }
50015e3b17bbSRichard Henderson 
50025e3b17bbSRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
50035e3b17bbSRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
50045e3b17bbSRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
50055e3b17bbSRichard Henderson     gen_helper_fdmulq(tcg_env, src1, src2);
50065e3b17bbSRichard Henderson     gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
50075e3b17bbSRichard Henderson     gen_op_store_QT0_fpr(QFPREG(a->rd));
50085e3b17bbSRichard Henderson     gen_update_fprs_dirty(dc, QFPREG(a->rd));
50095e3b17bbSRichard Henderson     return advance_pc(dc);
50105e3b17bbSRichard Henderson }
50115e3b17bbSRichard Henderson 
5012f7ec8155SRichard Henderson static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a, bool is_128,
5013f7ec8155SRichard Henderson                      void (*func)(DisasContext *, DisasCompare *, int, int))
5014f7ec8155SRichard Henderson {
5015f7ec8155SRichard Henderson     DisasCompare cmp;
5016f7ec8155SRichard Henderson 
50172c4f56c9SRichard Henderson     if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
50182c4f56c9SRichard Henderson         return false;
50192c4f56c9SRichard Henderson     }
5020f7ec8155SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
5021f7ec8155SRichard Henderson         return true;
5022f7ec8155SRichard Henderson     }
5023f7ec8155SRichard Henderson     if (is_128 && gen_trap_float128(dc)) {
5024f7ec8155SRichard Henderson         return true;
5025f7ec8155SRichard Henderson     }
5026f7ec8155SRichard Henderson 
5027f7ec8155SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
5028f7ec8155SRichard Henderson     func(dc, &cmp, a->rd, a->rs2);
5029f7ec8155SRichard Henderson     return advance_pc(dc);
5030f7ec8155SRichard Henderson }
5031f7ec8155SRichard Henderson 
5032f7ec8155SRichard Henderson TRANS(FMOVRs, 64, do_fmovr, a, false, gen_fmovs)
5033f7ec8155SRichard Henderson TRANS(FMOVRd, 64, do_fmovr, a, false, gen_fmovd)
5034f7ec8155SRichard Henderson TRANS(FMOVRq, 64, do_fmovr, a, true, gen_fmovq)
5035f7ec8155SRichard Henderson 
5036f7ec8155SRichard Henderson static bool do_fmovcc(DisasContext *dc, arg_FMOVscc *a, bool is_128,
5037f7ec8155SRichard Henderson                       void (*func)(DisasContext *, DisasCompare *, int, int))
5038f7ec8155SRichard Henderson {
5039f7ec8155SRichard Henderson     DisasCompare cmp;
5040f7ec8155SRichard Henderson 
5041f7ec8155SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
5042f7ec8155SRichard Henderson         return true;
5043f7ec8155SRichard Henderson     }
5044f7ec8155SRichard Henderson     if (is_128 && gen_trap_float128(dc)) {
5045f7ec8155SRichard Henderson         return true;
5046f7ec8155SRichard Henderson     }
5047f7ec8155SRichard Henderson 
5048f7ec8155SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
5049f7ec8155SRichard Henderson     gen_compare(&cmp, a->cc, a->cond, dc);
5050f7ec8155SRichard Henderson     func(dc, &cmp, a->rd, a->rs2);
5051f7ec8155SRichard Henderson     return advance_pc(dc);
5052f7ec8155SRichard Henderson }
5053f7ec8155SRichard Henderson 
5054f7ec8155SRichard Henderson TRANS(FMOVscc, 64, do_fmovcc, a, false, gen_fmovs)
5055f7ec8155SRichard Henderson TRANS(FMOVdcc, 64, do_fmovcc, a, false, gen_fmovd)
5056f7ec8155SRichard Henderson TRANS(FMOVqcc, 64, do_fmovcc, a, true, gen_fmovq)
5057f7ec8155SRichard Henderson 
5058f7ec8155SRichard Henderson static bool do_fmovfcc(DisasContext *dc, arg_FMOVsfcc *a, bool is_128,
5059f7ec8155SRichard Henderson                        void (*func)(DisasContext *, DisasCompare *, int, int))
5060f7ec8155SRichard Henderson {
5061f7ec8155SRichard Henderson     DisasCompare cmp;
5062f7ec8155SRichard Henderson 
5063f7ec8155SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
5064f7ec8155SRichard Henderson         return true;
5065f7ec8155SRichard Henderson     }
5066f7ec8155SRichard Henderson     if (is_128 && gen_trap_float128(dc)) {
5067f7ec8155SRichard Henderson         return true;
5068f7ec8155SRichard Henderson     }
5069f7ec8155SRichard Henderson 
5070f7ec8155SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
5071f7ec8155SRichard Henderson     gen_fcompare(&cmp, a->cc, a->cond);
5072f7ec8155SRichard Henderson     func(dc, &cmp, a->rd, a->rs2);
5073f7ec8155SRichard Henderson     return advance_pc(dc);
5074f7ec8155SRichard Henderson }
5075f7ec8155SRichard Henderson 
5076f7ec8155SRichard Henderson TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
5077f7ec8155SRichard Henderson TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
5078f7ec8155SRichard Henderson TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
5079f7ec8155SRichard Henderson 
508040f9ad21SRichard Henderson static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e)
508140f9ad21SRichard Henderson {
508240f9ad21SRichard Henderson     TCGv_i32 src1, src2;
508340f9ad21SRichard Henderson 
508440f9ad21SRichard Henderson     if (avail_32(dc) && a->cc != 0) {
508540f9ad21SRichard Henderson         return false;
508640f9ad21SRichard Henderson     }
508740f9ad21SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
508840f9ad21SRichard Henderson         return true;
508940f9ad21SRichard Henderson     }
509040f9ad21SRichard Henderson 
509140f9ad21SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
509240f9ad21SRichard Henderson     src1 = gen_load_fpr_F(dc, a->rs1);
509340f9ad21SRichard Henderson     src2 = gen_load_fpr_F(dc, a->rs2);
509440f9ad21SRichard Henderson     if (e) {
509540f9ad21SRichard Henderson         gen_op_fcmpes(a->cc, src1, src2);
509640f9ad21SRichard Henderson     } else {
509740f9ad21SRichard Henderson         gen_op_fcmps(a->cc, src1, src2);
509840f9ad21SRichard Henderson     }
509940f9ad21SRichard Henderson     return advance_pc(dc);
510040f9ad21SRichard Henderson }
510140f9ad21SRichard Henderson 
510240f9ad21SRichard Henderson TRANS(FCMPs, ALL, do_fcmps, a, false)
510340f9ad21SRichard Henderson TRANS(FCMPEs, ALL, do_fcmps, a, true)
510440f9ad21SRichard Henderson 
510540f9ad21SRichard Henderson static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, bool e)
510640f9ad21SRichard Henderson {
510740f9ad21SRichard Henderson     TCGv_i64 src1, src2;
510840f9ad21SRichard Henderson 
510940f9ad21SRichard Henderson     if (avail_32(dc) && a->cc != 0) {
511040f9ad21SRichard Henderson         return false;
511140f9ad21SRichard Henderson     }
511240f9ad21SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
511340f9ad21SRichard Henderson         return true;
511440f9ad21SRichard Henderson     }
511540f9ad21SRichard Henderson 
511640f9ad21SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
511740f9ad21SRichard Henderson     src1 = gen_load_fpr_D(dc, a->rs1);
511840f9ad21SRichard Henderson     src2 = gen_load_fpr_D(dc, a->rs2);
511940f9ad21SRichard Henderson     if (e) {
512040f9ad21SRichard Henderson         gen_op_fcmped(a->cc, src1, src2);
512140f9ad21SRichard Henderson     } else {
512240f9ad21SRichard Henderson         gen_op_fcmpd(a->cc, src1, src2);
512340f9ad21SRichard Henderson     }
512440f9ad21SRichard Henderson     return advance_pc(dc);
512540f9ad21SRichard Henderson }
512640f9ad21SRichard Henderson 
512740f9ad21SRichard Henderson TRANS(FCMPd, ALL, do_fcmpd, a, false)
512840f9ad21SRichard Henderson TRANS(FCMPEd, ALL, do_fcmpd, a, true)
512940f9ad21SRichard Henderson 
513040f9ad21SRichard Henderson static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e)
513140f9ad21SRichard Henderson {
5132f3ceafadSRichard Henderson     TCGv_i128 src1, src2;
5133f3ceafadSRichard Henderson 
513440f9ad21SRichard Henderson     if (avail_32(dc) && a->cc != 0) {
513540f9ad21SRichard Henderson         return false;
513640f9ad21SRichard Henderson     }
513740f9ad21SRichard Henderson     if (gen_trap_ifnofpu(dc)) {
513840f9ad21SRichard Henderson         return true;
513940f9ad21SRichard Henderson     }
514040f9ad21SRichard Henderson     if (gen_trap_float128(dc)) {
514140f9ad21SRichard Henderson         return true;
514240f9ad21SRichard Henderson     }
514340f9ad21SRichard Henderson 
514440f9ad21SRichard Henderson     gen_op_clear_ieee_excp_and_FTT();
5145f3ceafadSRichard Henderson     src1 = gen_load_fpr_Q(dc, a->rs1);
5146f3ceafadSRichard Henderson     src2 = gen_load_fpr_Q(dc, a->rs2);
514740f9ad21SRichard Henderson     if (e) {
5148f3ceafadSRichard Henderson         gen_op_fcmpeq(a->cc, src1, src2);
514940f9ad21SRichard Henderson     } else {
5150f3ceafadSRichard Henderson         gen_op_fcmpq(a->cc, src1, src2);
515140f9ad21SRichard Henderson     }
515240f9ad21SRichard Henderson     return advance_pc(dc);
515340f9ad21SRichard Henderson }
515440f9ad21SRichard Henderson 
515540f9ad21SRichard Henderson TRANS(FCMPq, ALL, do_fcmpq, a, false)
515640f9ad21SRichard Henderson TRANS(FCMPEq, ALL, do_fcmpq, a, true)
515740f9ad21SRichard Henderson 
51586e61bc94SEmilio G. Cota static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5159fcf5ef2aSThomas Huth {
51606e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
5161b77af26eSRichard Henderson     CPUSPARCState *env = cpu_env(cs);
51626e61bc94SEmilio G. Cota     int bound;
5163af00be49SEmilio G. Cota 
5164af00be49SEmilio G. Cota     dc->pc = dc->base.pc_first;
51656e61bc94SEmilio G. Cota     dc->npc = (target_ulong)dc->base.tb->cs_base;
51666e61bc94SEmilio G. Cota     dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
5167576e1c4cSIgor Mammedov     dc->def = &env->def;
51686e61bc94SEmilio G. Cota     dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
51696e61bc94SEmilio G. Cota     dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
5170c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
51716e61bc94SEmilio G. Cota     dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
5172c9b459aaSArtyom Tarasenko #endif
5173fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5174fcf5ef2aSThomas Huth     dc->fprs_dirty = 0;
51756e61bc94SEmilio G. Cota     dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
5176c9b459aaSArtyom Tarasenko #ifndef CONFIG_USER_ONLY
51776e61bc94SEmilio G. Cota     dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
5178c9b459aaSArtyom Tarasenko #endif
5179fcf5ef2aSThomas Huth #endif
51806e61bc94SEmilio G. Cota     /*
51816e61bc94SEmilio G. Cota      * if we reach a page boundary, we stop generation so that the
51826e61bc94SEmilio G. Cota      * PC of a TT_TFAULT exception is always in the right page
51836e61bc94SEmilio G. Cota      */
51846e61bc94SEmilio G. Cota     bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
51856e61bc94SEmilio G. Cota     dc->base.max_insns = MIN(dc->base.max_insns, bound);
5186af00be49SEmilio G. Cota }
5187fcf5ef2aSThomas Huth 
51886e61bc94SEmilio G. Cota static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
51896e61bc94SEmilio G. Cota {
51906e61bc94SEmilio G. Cota }
51916e61bc94SEmilio G. Cota 
51926e61bc94SEmilio G. Cota static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
51936e61bc94SEmilio G. Cota {
51946e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
5195633c4283SRichard Henderson     target_ulong npc = dc->npc;
51966e61bc94SEmilio G. Cota 
5197633c4283SRichard Henderson     if (npc & 3) {
5198633c4283SRichard Henderson         switch (npc) {
5199633c4283SRichard Henderson         case JUMP_PC:
5200fcf5ef2aSThomas Huth             assert(dc->jump_pc[1] == dc->pc + 4);
5201633c4283SRichard Henderson             npc = dc->jump_pc[0] | JUMP_PC;
5202633c4283SRichard Henderson             break;
5203633c4283SRichard Henderson         case DYNAMIC_PC:
5204633c4283SRichard Henderson         case DYNAMIC_PC_LOOKUP:
5205633c4283SRichard Henderson             npc = DYNAMIC_PC;
5206633c4283SRichard Henderson             break;
5207633c4283SRichard Henderson         default:
5208633c4283SRichard Henderson             g_assert_not_reached();
5209fcf5ef2aSThomas Huth         }
52106e61bc94SEmilio G. Cota     }
5211633c4283SRichard Henderson     tcg_gen_insn_start(dc->pc, npc);
5212633c4283SRichard Henderson }
5213fcf5ef2aSThomas Huth 
52146e61bc94SEmilio G. Cota static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
52156e61bc94SEmilio G. Cota {
52166e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
5217b77af26eSRichard Henderson     CPUSPARCState *env = cpu_env(cs);
52186e61bc94SEmilio G. Cota     unsigned int insn;
5219fcf5ef2aSThomas Huth 
52204e116893SIlya Leoshkevich     insn = translator_ldl(env, &dc->base, dc->pc);
5221af00be49SEmilio G. Cota     dc->base.pc_next += 4;
5222878cc677SRichard Henderson 
5223878cc677SRichard Henderson     if (!decode(dc, insn)) {
5224ba9c09b4SRichard Henderson         gen_exception(dc, TT_ILL_INSN);
5225878cc677SRichard Henderson     }
5226fcf5ef2aSThomas Huth 
5227af00be49SEmilio G. Cota     if (dc->base.is_jmp == DISAS_NORETURN) {
52286e61bc94SEmilio G. Cota         return;
5229c5e6ccdfSEmilio G. Cota     }
5230af00be49SEmilio G. Cota     if (dc->pc != dc->base.pc_next) {
52316e61bc94SEmilio G. Cota         dc->base.is_jmp = DISAS_TOO_MANY;
5232af00be49SEmilio G. Cota     }
52336e61bc94SEmilio G. Cota }
5234fcf5ef2aSThomas Huth 
52356e61bc94SEmilio G. Cota static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
52366e61bc94SEmilio G. Cota {
52376e61bc94SEmilio G. Cota     DisasContext *dc = container_of(dcbase, DisasContext, base);
5238186e7890SRichard Henderson     DisasDelayException *e, *e_next;
5239633c4283SRichard Henderson     bool may_lookup;
52406e61bc94SEmilio G. Cota 
524189527e3aSRichard Henderson     finishing_insn(dc);
524289527e3aSRichard Henderson 
524346bb0137SMark Cave-Ayland     switch (dc->base.is_jmp) {
524446bb0137SMark Cave-Ayland     case DISAS_NEXT:
524546bb0137SMark Cave-Ayland     case DISAS_TOO_MANY:
5246633c4283SRichard Henderson         if (((dc->pc | dc->npc) & 3) == 0) {
5247fcf5ef2aSThomas Huth             /* static PC and NPC: we can use direct chaining */
5248fcf5ef2aSThomas Huth             gen_goto_tb(dc, 0, dc->pc, dc->npc);
5249633c4283SRichard Henderson             break;
5250fcf5ef2aSThomas Huth         }
5251633c4283SRichard Henderson 
5252930f1865SRichard Henderson         may_lookup = true;
5253633c4283SRichard Henderson         if (dc->pc & 3) {
5254633c4283SRichard Henderson             switch (dc->pc) {
5255633c4283SRichard Henderson             case DYNAMIC_PC_LOOKUP:
5256633c4283SRichard Henderson                 break;
5257633c4283SRichard Henderson             case DYNAMIC_PC:
5258633c4283SRichard Henderson                 may_lookup = false;
5259633c4283SRichard Henderson                 break;
5260633c4283SRichard Henderson             default:
5261633c4283SRichard Henderson                 g_assert_not_reached();
5262633c4283SRichard Henderson             }
5263633c4283SRichard Henderson         } else {
5264633c4283SRichard Henderson             tcg_gen_movi_tl(cpu_pc, dc->pc);
5265633c4283SRichard Henderson         }
5266633c4283SRichard Henderson 
5267930f1865SRichard Henderson         if (dc->npc & 3) {
5268930f1865SRichard Henderson             switch (dc->npc) {
5269930f1865SRichard Henderson             case JUMP_PC:
5270930f1865SRichard Henderson                 gen_generic_branch(dc);
5271930f1865SRichard Henderson                 break;
5272930f1865SRichard Henderson             case DYNAMIC_PC:
5273930f1865SRichard Henderson                 may_lookup = false;
5274930f1865SRichard Henderson                 break;
5275930f1865SRichard Henderson             case DYNAMIC_PC_LOOKUP:
5276930f1865SRichard Henderson                 break;
5277930f1865SRichard Henderson             default:
5278930f1865SRichard Henderson                 g_assert_not_reached();
5279930f1865SRichard Henderson             }
5280930f1865SRichard Henderson         } else {
5281930f1865SRichard Henderson             tcg_gen_movi_tl(cpu_npc, dc->npc);
5282930f1865SRichard Henderson         }
5283633c4283SRichard Henderson         if (may_lookup) {
5284633c4283SRichard Henderson             tcg_gen_lookup_and_goto_ptr();
5285633c4283SRichard Henderson         } else {
528607ea28b4SRichard Henderson             tcg_gen_exit_tb(NULL, 0);
5287fcf5ef2aSThomas Huth         }
528846bb0137SMark Cave-Ayland         break;
528946bb0137SMark Cave-Ayland 
529046bb0137SMark Cave-Ayland     case DISAS_NORETURN:
529146bb0137SMark Cave-Ayland        break;
529246bb0137SMark Cave-Ayland 
529346bb0137SMark Cave-Ayland     case DISAS_EXIT:
529446bb0137SMark Cave-Ayland         /* Exit TB */
529546bb0137SMark Cave-Ayland         save_state(dc);
529646bb0137SMark Cave-Ayland         tcg_gen_exit_tb(NULL, 0);
529746bb0137SMark Cave-Ayland         break;
529846bb0137SMark Cave-Ayland 
529946bb0137SMark Cave-Ayland     default:
530046bb0137SMark Cave-Ayland         g_assert_not_reached();
5301fcf5ef2aSThomas Huth     }
5302186e7890SRichard Henderson 
5303186e7890SRichard Henderson     for (e = dc->delay_excp_list; e ; e = e_next) {
5304186e7890SRichard Henderson         gen_set_label(e->lab);
5305186e7890SRichard Henderson 
5306186e7890SRichard Henderson         tcg_gen_movi_tl(cpu_pc, e->pc);
5307186e7890SRichard Henderson         if (e->npc % 4 == 0) {
5308186e7890SRichard Henderson             tcg_gen_movi_tl(cpu_npc, e->npc);
5309186e7890SRichard Henderson         }
5310186e7890SRichard Henderson         gen_helper_raise_exception(tcg_env, e->excp);
5311186e7890SRichard Henderson 
5312186e7890SRichard Henderson         e_next = e->next;
5313186e7890SRichard Henderson         g_free(e);
5314186e7890SRichard Henderson     }
5315fcf5ef2aSThomas Huth }
53166e61bc94SEmilio G. Cota 
53178eb806a7SRichard Henderson static void sparc_tr_disas_log(const DisasContextBase *dcbase,
53188eb806a7SRichard Henderson                                CPUState *cpu, FILE *logfile)
53196e61bc94SEmilio G. Cota {
53208eb806a7SRichard Henderson     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
53218eb806a7SRichard Henderson     target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
53226e61bc94SEmilio G. Cota }
53236e61bc94SEmilio G. Cota 
53246e61bc94SEmilio G. Cota static const TranslatorOps sparc_tr_ops = {
53256e61bc94SEmilio G. Cota     .init_disas_context = sparc_tr_init_disas_context,
53266e61bc94SEmilio G. Cota     .tb_start           = sparc_tr_tb_start,
53276e61bc94SEmilio G. Cota     .insn_start         = sparc_tr_insn_start,
53286e61bc94SEmilio G. Cota     .translate_insn     = sparc_tr_translate_insn,
53296e61bc94SEmilio G. Cota     .tb_stop            = sparc_tr_tb_stop,
53306e61bc94SEmilio G. Cota     .disas_log          = sparc_tr_disas_log,
53316e61bc94SEmilio G. Cota };
53326e61bc94SEmilio G. Cota 
5333597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
533432f0c394SAnton Johansson                            vaddr pc, void *host_pc)
53356e61bc94SEmilio G. Cota {
53366e61bc94SEmilio G. Cota     DisasContext dc = {};
53376e61bc94SEmilio G. Cota 
5338306c8721SRichard Henderson     translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
5339fcf5ef2aSThomas Huth }
5340fcf5ef2aSThomas Huth 
534155c3ceefSRichard Henderson void sparc_tcg_init(void)
5342fcf5ef2aSThomas Huth {
5343fcf5ef2aSThomas Huth     static const char gregnames[32][4] = {
5344fcf5ef2aSThomas Huth         "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
5345fcf5ef2aSThomas Huth         "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5346fcf5ef2aSThomas Huth         "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5347fcf5ef2aSThomas Huth         "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
5348fcf5ef2aSThomas Huth     };
5349fcf5ef2aSThomas Huth     static const char fregnames[32][4] = {
5350fcf5ef2aSThomas Huth         "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5351fcf5ef2aSThomas Huth         "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5352fcf5ef2aSThomas Huth         "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5353fcf5ef2aSThomas Huth         "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5354fcf5ef2aSThomas Huth     };
5355fcf5ef2aSThomas Huth 
5356fcf5ef2aSThomas Huth     static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5357fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64
5358fcf5ef2aSThomas Huth         { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
53592a1905c7SRichard Henderson         { &cpu_xcc_Z, offsetof(CPUSPARCState, xcc_Z), "xcc_Z" },
53602a1905c7SRichard Henderson         { &cpu_xcc_C, offsetof(CPUSPARCState, xcc_C), "xcc_C" },
5361fcf5ef2aSThomas Huth #endif
53622a1905c7SRichard Henderson         { &cpu_cc_N, offsetof(CPUSPARCState, cc_N), "cc_N" },
53632a1905c7SRichard Henderson         { &cpu_cc_V, offsetof(CPUSPARCState, cc_V), "cc_V" },
53642a1905c7SRichard Henderson         { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" },
53652a1905c7SRichard Henderson         { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" },
5366fcf5ef2aSThomas Huth         { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5367fcf5ef2aSThomas Huth         { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5368fcf5ef2aSThomas Huth         { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5369fcf5ef2aSThomas Huth         { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5370fcf5ef2aSThomas Huth         { &cpu_y, offsetof(CPUSPARCState, y), "y" },
5371fcf5ef2aSThomas Huth         { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
5372fcf5ef2aSThomas Huth     };
5373fcf5ef2aSThomas Huth 
5374fcf5ef2aSThomas Huth     unsigned int i;
5375fcf5ef2aSThomas Huth 
5376ad75a51eSRichard Henderson     cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
5377fcf5ef2aSThomas Huth                                          offsetof(CPUSPARCState, regwptr),
5378fcf5ef2aSThomas Huth                                          "regwptr");
5379fcf5ef2aSThomas Huth 
5380fcf5ef2aSThomas Huth     for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5381ad75a51eSRichard Henderson         *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
5382fcf5ef2aSThomas Huth     }
5383fcf5ef2aSThomas Huth 
5384f764718dSRichard Henderson     cpu_regs[0] = NULL;
5385fcf5ef2aSThomas Huth     for (i = 1; i < 8; ++i) {
5386ad75a51eSRichard Henderson         cpu_regs[i] = tcg_global_mem_new(tcg_env,
5387fcf5ef2aSThomas Huth                                          offsetof(CPUSPARCState, gregs[i]),
5388fcf5ef2aSThomas Huth                                          gregnames[i]);
5389fcf5ef2aSThomas Huth     }
5390fcf5ef2aSThomas Huth 
5391fcf5ef2aSThomas Huth     for (i = 8; i < 32; ++i) {
5392fcf5ef2aSThomas Huth         cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5393fcf5ef2aSThomas Huth                                          (i - 8) * sizeof(target_ulong),
5394fcf5ef2aSThomas Huth                                          gregnames[i]);
5395fcf5ef2aSThomas Huth     }
5396fcf5ef2aSThomas Huth 
5397fcf5ef2aSThomas Huth     for (i = 0; i < TARGET_DPREGS; i++) {
5398ad75a51eSRichard Henderson         cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
5399fcf5ef2aSThomas Huth                                             offsetof(CPUSPARCState, fpr[i]),
5400fcf5ef2aSThomas Huth                                             fregnames[i]);
5401fcf5ef2aSThomas Huth     }
5402b597eedcSRichard Henderson 
5403b597eedcSRichard Henderson #ifdef TARGET_SPARC64
5404b597eedcSRichard Henderson     cpu_fprs = tcg_global_mem_new_i32(tcg_env,
5405b597eedcSRichard Henderson                                       offsetof(CPUSPARCState, fprs), "fprs");
5406b597eedcSRichard Henderson #endif
5407fcf5ef2aSThomas Huth }
5408fcf5ef2aSThomas Huth 
5409f36aaa53SRichard Henderson void sparc_restore_state_to_opc(CPUState *cs,
5410f36aaa53SRichard Henderson                                 const TranslationBlock *tb,
5411f36aaa53SRichard Henderson                                 const uint64_t *data)
5412fcf5ef2aSThomas Huth {
5413f36aaa53SRichard Henderson     SPARCCPU *cpu = SPARC_CPU(cs);
5414f36aaa53SRichard Henderson     CPUSPARCState *env = &cpu->env;
5415fcf5ef2aSThomas Huth     target_ulong pc = data[0];
5416fcf5ef2aSThomas Huth     target_ulong npc = data[1];
5417fcf5ef2aSThomas Huth 
5418fcf5ef2aSThomas Huth     env->pc = pc;
5419fcf5ef2aSThomas Huth     if (npc == DYNAMIC_PC) {
5420fcf5ef2aSThomas Huth         /* dynamic NPC: already stored */
5421fcf5ef2aSThomas Huth     } else if (npc & JUMP_PC) {
5422fcf5ef2aSThomas Huth         /* jump PC: use 'cond' and the jump targets of the translation */
5423fcf5ef2aSThomas Huth         if (env->cond) {
5424fcf5ef2aSThomas Huth             env->npc = npc & ~3;
5425fcf5ef2aSThomas Huth         } else {
5426fcf5ef2aSThomas Huth             env->npc = pc + 4;
5427fcf5ef2aSThomas Huth         }
5428fcf5ef2aSThomas Huth     } else {
5429fcf5ef2aSThomas Huth         env->npc = npc;
5430fcf5ef2aSThomas Huth     }
5431fcf5ef2aSThomas Huth }
5432