1 /* 2 * Sparc32 interrupt helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "trace.h" 23 #include "exec/log.h" 24 #include "sysemu/runstate.h" 25 26 27 static const char * const excp_names[0x80] = { 28 [TT_TFAULT] = "Instruction Access Fault", 29 [TT_ILL_INSN] = "Illegal Instruction", 30 [TT_PRIV_INSN] = "Privileged Instruction", 31 [TT_NFPU_INSN] = "FPU Disabled", 32 [TT_WIN_OVF] = "Window Overflow", 33 [TT_WIN_UNF] = "Window Underflow", 34 [TT_UNALIGNED] = "Unaligned Memory Access", 35 [TT_FP_EXCP] = "FPU Exception", 36 [TT_DFAULT] = "Data Access Fault", 37 [TT_TOVF] = "Tag Overflow", 38 [TT_EXTINT | 0x1] = "External Interrupt 1", 39 [TT_EXTINT | 0x2] = "External Interrupt 2", 40 [TT_EXTINT | 0x3] = "External Interrupt 3", 41 [TT_EXTINT | 0x4] = "External Interrupt 4", 42 [TT_EXTINT | 0x5] = "External Interrupt 5", 43 [TT_EXTINT | 0x6] = "External Interrupt 6", 44 [TT_EXTINT | 0x7] = "External Interrupt 7", 45 [TT_EXTINT | 0x8] = "External Interrupt 8", 46 [TT_EXTINT | 0x9] = "External Interrupt 9", 47 [TT_EXTINT | 0xa] = "External Interrupt 10", 48 [TT_EXTINT | 0xb] = "External Interrupt 11", 49 [TT_EXTINT | 0xc] = "External Interrupt 12", 50 [TT_EXTINT | 0xd] = "External Interrupt 13", 51 [TT_EXTINT | 0xe] = "External Interrupt 14", 52 [TT_EXTINT | 0xf] = "External Interrupt 15", 53 [TT_TOVF] = "Tag Overflow", 54 [TT_CODE_ACCESS] = "Instruction Access Error", 55 [TT_DATA_ACCESS] = "Data Access Error", 56 [TT_DIV_ZERO] = "Division By Zero", 57 [TT_NCP_INSN] = "Coprocessor Disabled", 58 }; 59 60 void sparc_cpu_do_interrupt(CPUState *cs) 61 { 62 SPARCCPU *cpu = SPARC_CPU(cs); 63 CPUSPARCState *env = &cpu->env; 64 int cwp, intno = cs->exception_index; 65 66 /* Compute PSR before exposing state. */ 67 if (env->cc_op != CC_OP_FLAGS) { 68 cpu_get_psr(env); 69 } 70 71 if (qemu_loglevel_mask(CPU_LOG_INT)) { 72 static int count; 73 const char *name; 74 75 if (intno < 0 || intno >= 0x100) { 76 name = "Unknown"; 77 } else if (intno >= 0x80) { 78 name = "Trap Instruction"; 79 } else { 80 name = excp_names[intno]; 81 if (!name) { 82 name = "Unknown"; 83 } 84 } 85 86 qemu_log("%6d: %s (v=%02x)\n", count, name, intno); 87 log_cpu_state(cs, 0); 88 #if 0 89 { 90 int i; 91 uint8_t *ptr; 92 93 qemu_log(" code="); 94 ptr = (uint8_t *)env->pc; 95 for (i = 0; i < 16; i++) { 96 qemu_log(" %02x", ldub(ptr + i)); 97 } 98 qemu_log("\n"); 99 } 100 #endif 101 count++; 102 } 103 #if !defined(CONFIG_USER_ONLY) 104 if (env->psret == 0) { 105 if (cs->exception_index == 0x80 && 106 env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { 107 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 108 } else { 109 cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", 110 cs->exception_index); 111 } 112 return; 113 } 114 #endif 115 env->psret = 0; 116 cwp = cpu_cwp_dec(env, env->cwp - 1); 117 cpu_set_cwp(env, cwp); 118 env->regwptr[9] = env->pc; 119 env->regwptr[10] = env->npc; 120 env->psrps = env->psrs; 121 env->psrs = 1; 122 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); 123 env->pc = env->tbr; 124 env->npc = env->pc + 4; 125 cs->exception_index = -1; 126 127 #if !defined(CONFIG_USER_ONLY) 128 /* IRQ acknowledgment */ 129 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { 130 env->qemu_irq_ack(env, env->irq_manager, intno); 131 } 132 #endif 133 } 134 135 #if !defined(CONFIG_USER_ONLY) 136 static void leon3_cache_control_int(CPUSPARCState *env) 137 { 138 uint32_t state = 0; 139 140 if (env->cache_control & CACHE_CTRL_IF) { 141 /* Instruction cache state */ 142 state = env->cache_control & CACHE_STATE_MASK; 143 if (state == CACHE_ENABLED) { 144 state = CACHE_FROZEN; 145 trace_int_helper_icache_freeze(); 146 } 147 148 env->cache_control &= ~CACHE_STATE_MASK; 149 env->cache_control |= state; 150 } 151 152 if (env->cache_control & CACHE_CTRL_DF) { 153 /* Data cache state */ 154 state = (env->cache_control >> 2) & CACHE_STATE_MASK; 155 if (state == CACHE_ENABLED) { 156 state = CACHE_FROZEN; 157 trace_int_helper_dcache_freeze(); 158 } 159 160 env->cache_control &= ~(CACHE_STATE_MASK << 2); 161 env->cache_control |= (state << 2); 162 } 163 } 164 165 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) 166 { 167 leon3_irq_ack(irq_manager, intno); 168 leon3_cache_control_int(env); 169 } 170 #endif 171