1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * Sparc32 interrupt helpers 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2005 Fabrice Bellard 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 95650b549SChetan Pant * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18fcf5ef2aSThomas Huth */ 19fcf5ef2aSThomas Huth 20fcf5ef2aSThomas Huth #include "qemu/osdep.h" 2110fb1340SPhilippe Mathieu-Daudé #include "qemu/main-loop.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "trace.h" 24*c35c8d4dSCarl Hauser #include "exec/cpu_ldst.h" 25fcf5ef2aSThomas Huth #include "exec/log.h" 2654d31236SMarkus Armbruster #include "sysemu/runstate.h" 27fcf5ef2aSThomas Huth 28fcf5ef2aSThomas Huth static const char * const excp_names[0x80] = { 29fcf5ef2aSThomas Huth [TT_TFAULT] = "Instruction Access Fault", 30fcf5ef2aSThomas Huth [TT_ILL_INSN] = "Illegal Instruction", 31fcf5ef2aSThomas Huth [TT_PRIV_INSN] = "Privileged Instruction", 32fcf5ef2aSThomas Huth [TT_NFPU_INSN] = "FPU Disabled", 33fcf5ef2aSThomas Huth [TT_WIN_OVF] = "Window Overflow", 34fcf5ef2aSThomas Huth [TT_WIN_UNF] = "Window Underflow", 35fcf5ef2aSThomas Huth [TT_UNALIGNED] = "Unaligned Memory Access", 36fcf5ef2aSThomas Huth [TT_FP_EXCP] = "FPU Exception", 37fcf5ef2aSThomas Huth [TT_DFAULT] = "Data Access Fault", 38fcf5ef2aSThomas Huth [TT_TOVF] = "Tag Overflow", 39fcf5ef2aSThomas Huth [TT_EXTINT | 0x1] = "External Interrupt 1", 40fcf5ef2aSThomas Huth [TT_EXTINT | 0x2] = "External Interrupt 2", 41fcf5ef2aSThomas Huth [TT_EXTINT | 0x3] = "External Interrupt 3", 42fcf5ef2aSThomas Huth [TT_EXTINT | 0x4] = "External Interrupt 4", 43fcf5ef2aSThomas Huth [TT_EXTINT | 0x5] = "External Interrupt 5", 44fcf5ef2aSThomas Huth [TT_EXTINT | 0x6] = "External Interrupt 6", 45fcf5ef2aSThomas Huth [TT_EXTINT | 0x7] = "External Interrupt 7", 46fcf5ef2aSThomas Huth [TT_EXTINT | 0x8] = "External Interrupt 8", 47fcf5ef2aSThomas Huth [TT_EXTINT | 0x9] = "External Interrupt 9", 48fcf5ef2aSThomas Huth [TT_EXTINT | 0xa] = "External Interrupt 10", 49fcf5ef2aSThomas Huth [TT_EXTINT | 0xb] = "External Interrupt 11", 50fcf5ef2aSThomas Huth [TT_EXTINT | 0xc] = "External Interrupt 12", 51fcf5ef2aSThomas Huth [TT_EXTINT | 0xd] = "External Interrupt 13", 52fcf5ef2aSThomas Huth [TT_EXTINT | 0xe] = "External Interrupt 14", 53fcf5ef2aSThomas Huth [TT_EXTINT | 0xf] = "External Interrupt 15", 54fcf5ef2aSThomas Huth [TT_CODE_ACCESS] = "Instruction Access Error", 55fcf5ef2aSThomas Huth [TT_DATA_ACCESS] = "Data Access Error", 56fcf5ef2aSThomas Huth [TT_DIV_ZERO] = "Division By Zero", 57fcf5ef2aSThomas Huth [TT_NCP_INSN] = "Coprocessor Disabled", 58fcf5ef2aSThomas Huth }; 59fcf5ef2aSThomas Huth 6086e8c353SPhilippe Mathieu-Daudé static const char *excp_name_str(int32_t exception_index) 6186e8c353SPhilippe Mathieu-Daudé { 6286e8c353SPhilippe Mathieu-Daudé if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) { 6386e8c353SPhilippe Mathieu-Daudé return "Unknown"; 6486e8c353SPhilippe Mathieu-Daudé } 6586e8c353SPhilippe Mathieu-Daudé return excp_names[exception_index]; 6686e8c353SPhilippe Mathieu-Daudé } 6786e8c353SPhilippe Mathieu-Daudé 6810fb1340SPhilippe Mathieu-Daudé void cpu_check_irqs(CPUSPARCState *env) 6910fb1340SPhilippe Mathieu-Daudé { 7010fb1340SPhilippe Mathieu-Daudé CPUState *cs; 7110fb1340SPhilippe Mathieu-Daudé 7210fb1340SPhilippe Mathieu-Daudé /* We should be holding the BQL before we mess with IRQs */ 73195801d7SStefan Hajnoczi g_assert(bql_locked()); 7410fb1340SPhilippe Mathieu-Daudé 7510fb1340SPhilippe Mathieu-Daudé if (env->pil_in && (env->interrupt_index == 0 || 7610fb1340SPhilippe Mathieu-Daudé (env->interrupt_index & ~15) == TT_EXTINT)) { 7710fb1340SPhilippe Mathieu-Daudé unsigned int i; 7810fb1340SPhilippe Mathieu-Daudé 7910fb1340SPhilippe Mathieu-Daudé for (i = 15; i > 0; i--) { 8010fb1340SPhilippe Mathieu-Daudé if (env->pil_in & (1 << i)) { 8110fb1340SPhilippe Mathieu-Daudé int old_interrupt = env->interrupt_index; 8210fb1340SPhilippe Mathieu-Daudé 8310fb1340SPhilippe Mathieu-Daudé env->interrupt_index = TT_EXTINT | i; 8410fb1340SPhilippe Mathieu-Daudé if (old_interrupt != env->interrupt_index) { 8510fb1340SPhilippe Mathieu-Daudé cs = env_cpu(env); 8610fb1340SPhilippe Mathieu-Daudé trace_sun4m_cpu_interrupt(i); 8710fb1340SPhilippe Mathieu-Daudé cpu_interrupt(cs, CPU_INTERRUPT_HARD); 8810fb1340SPhilippe Mathieu-Daudé } 8910fb1340SPhilippe Mathieu-Daudé break; 9010fb1340SPhilippe Mathieu-Daudé } 9110fb1340SPhilippe Mathieu-Daudé } 9210fb1340SPhilippe Mathieu-Daudé } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 9310fb1340SPhilippe Mathieu-Daudé cs = env_cpu(env); 9410fb1340SPhilippe Mathieu-Daudé trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 9510fb1340SPhilippe Mathieu-Daudé env->interrupt_index = 0; 9610fb1340SPhilippe Mathieu-Daudé cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 9710fb1340SPhilippe Mathieu-Daudé } 9810fb1340SPhilippe Mathieu-Daudé } 9910fb1340SPhilippe Mathieu-Daudé 100fcf5ef2aSThomas Huth void sparc_cpu_do_interrupt(CPUState *cs) 101fcf5ef2aSThomas Huth { 10277976769SPhilippe Mathieu-Daudé CPUSPARCState *env = cpu_env(cs); 103fcf5ef2aSThomas Huth int cwp, intno = cs->exception_index; 104fcf5ef2aSThomas Huth 105fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_INT)) { 106fcf5ef2aSThomas Huth static int count; 107fcf5ef2aSThomas Huth const char *name; 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth if (intno < 0 || intno >= 0x100) { 110fcf5ef2aSThomas Huth name = "Unknown"; 111fcf5ef2aSThomas Huth } else if (intno >= 0x80) { 112fcf5ef2aSThomas Huth name = "Trap Instruction"; 113fcf5ef2aSThomas Huth } else { 11486e8c353SPhilippe Mathieu-Daudé name = excp_name_str(intno); 115fcf5ef2aSThomas Huth } 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth qemu_log("%6d: %s (v=%02x)\n", count, name, intno); 118fcf5ef2aSThomas Huth log_cpu_state(cs, 0); 119fcf5ef2aSThomas Huth count++; 120fcf5ef2aSThomas Huth } 121*c35c8d4dSCarl Hauser #ifndef CONFIG_USER_ONLY 122fcf5ef2aSThomas Huth if (env->psret == 0) { 123fcf5ef2aSThomas Huth if (cs->exception_index == 0x80 && 124576e1c4cSIgor Mammedov env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { 125cf83f140SEric Blake qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 126fcf5ef2aSThomas Huth } else { 12786e8c353SPhilippe Mathieu-Daudé cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, " 12886e8c353SPhilippe Mathieu-Daudé "Error state", 12986e8c353SPhilippe Mathieu-Daudé cs->exception_index, excp_name_str(cs->exception_index)); 130fcf5ef2aSThomas Huth } 131fcf5ef2aSThomas Huth return; 132fcf5ef2aSThomas Huth } 133*c35c8d4dSCarl Hauser if (intno == TT_FP_EXCP) { 134*c35c8d4dSCarl Hauser /* 135*c35c8d4dSCarl Hauser * The sparc32 fpu has three states related to exception handling. 136*c35c8d4dSCarl Hauser * The FPop that signals an exception transitions from fp_execute 137*c35c8d4dSCarl Hauser * to fp_exception_pending. A subsequent FPop transitions from 138*c35c8d4dSCarl Hauser * fp_exception_pending to fp_exception, which forces the trap. 139*c35c8d4dSCarl Hauser * 140*c35c8d4dSCarl Hauser * If the queue is not empty, this trap is due to execution of an 141*c35c8d4dSCarl Hauser * illegal FPop while in fp_exception state. Here we are to 142*c35c8d4dSCarl Hauser * re-enter fp_exception_pending state without queuing the insn. 143*c35c8d4dSCarl Hauser * 144*c35c8d4dSCarl Hauser * We do not model the fp_exception_pending state, but instead 145*c35c8d4dSCarl Hauser * skip directly to fp_exception state. We advance pc/npc to 146*c35c8d4dSCarl Hauser * mimic delayed trap delivery as if by the subsequent insn. 147*c35c8d4dSCarl Hauser */ 148*c35c8d4dSCarl Hauser if (!env->fsr_qne) { 149*c35c8d4dSCarl Hauser env->fsr_qne = FSR_QNE; 150*c35c8d4dSCarl Hauser env->fq.s.addr = env->pc; 151*c35c8d4dSCarl Hauser env->fq.s.insn = cpu_ldl_code(env, env->pc); 152*c35c8d4dSCarl Hauser } 153*c35c8d4dSCarl Hauser env->pc = env->npc; 154*c35c8d4dSCarl Hauser env->npc = env->npc + 4; 155*c35c8d4dSCarl Hauser } 156fcf5ef2aSThomas Huth #endif 157fcf5ef2aSThomas Huth env->psret = 0; 158fcf5ef2aSThomas Huth cwp = cpu_cwp_dec(env, env->cwp - 1); 159fcf5ef2aSThomas Huth cpu_set_cwp(env, cwp); 160fcf5ef2aSThomas Huth env->regwptr[9] = env->pc; 161fcf5ef2aSThomas Huth env->regwptr[10] = env->npc; 162fcf5ef2aSThomas Huth env->psrps = env->psrs; 163fcf5ef2aSThomas Huth env->psrs = 1; 164fcf5ef2aSThomas Huth env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); 165fcf5ef2aSThomas Huth env->pc = env->tbr; 166fcf5ef2aSThomas Huth env->npc = env->pc + 4; 167fcf5ef2aSThomas Huth cs->exception_index = -1; 168fcf5ef2aSThomas Huth 169fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 170fcf5ef2aSThomas Huth /* IRQ acknowledgment */ 171fcf5ef2aSThomas Huth if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { 172a318da6bSClément Chigot env->qemu_irq_ack(env, intno); 173fcf5ef2aSThomas Huth } 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth } 176