1# SPDX-License-Identifier: LGPL-2.0+ 2# 3# Sparc instruction decode definitions. 4# Copyright (c) 2023 Richard Henderson <rth@twiddle.net> 5 6## 7## Major Opcodes 00 and 01 -- branches, call, and sethi. 8## 9 10&bcc i a cond cc 11BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc 12Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 13FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc 14FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0 15 16%d16 20:s2 0:14 17BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 18 19NCP 00 - ---- 111 ---------------------- # CBcc 20 21SETHI 00 rd:5 100 i:22 22 23CALL 01 i:s30 24 25## 26## Major Opcode 10 -- integer, floating-point, vis, and system insns. 27## 28 29&r_r_ri rd rs1 rs2_or_imm imm:bool 30@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 31@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri 32 33&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool 34@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc 35@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 36@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1 37 38{ 39 [ 40 STBAR 10 00000 101000 01111 0 0000000000000 41 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 42 43 RDCCR 10 rd:5 101000 00010 0 0000000000000 44 RDASI 10 rd:5 101000 00011 0 0000000000000 45 RDTICK 10 rd:5 101000 00100 0 0000000000000 46 RDPC 10 rd:5 101000 00101 0 0000000000000 47 RDFPRS 10 rd:5 101000 00110 0 0000000000000 48 RDASR17 10 rd:5 101000 10001 0 0000000000000 49 RDGSR 10 rd:5 101000 10011 0 0000000000000 50 RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 51 RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 52 RDSTICK 10 rd:5 101000 11000 0 0000000000000 53 RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 54 RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 55 ] 56 # Before v8, all rs1 accepted; otherwise rs1==0. 57 RDY 10 rd:5 101000 rs1:5 0 0000000000000 58} 59 60{ 61 [ 62 WRY 10 00000 110000 ..... . ............. @n_r_ri 63 WRCCR 10 00010 110000 ..... . ............. @n_r_ri 64 WRASI 10 00011 110000 ..... . ............. @n_r_ri 65 WRFPRS 10 00110 110000 ..... . ............. @n_r_ri 66 { 67 WRGSR 10 10011 110000 ..... . ............. @n_r_ri 68 WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri 69 } 70 WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri 71 WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri 72 WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri 73 WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri 74 WRSTICK 10 11000 110000 ..... . ............. @n_r_ri 75 WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri 76 ] 77 # Before v8, rs1==0 was WRY, and the rest executed as nop. 78 [ 79 NOP_v7 10 ----- 110000 ----- 0 00000000 ----- 80 NOP_v7 10 ----- 110000 ----- 1 -------- ----- 81 ] 82} 83 84{ 85 RDPSR 10 rd:5 101001 00000 0 0000000000000 86 RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 87} 88RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 89RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 90RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 91RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 92RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 93 94{ 95 WRPSR 10 00000 110001 ..... . ............. @n_r_ri 96 SAVED 10 00000 110001 00000 0 0000000000000 97} 98RESTORED 10 00001 110001 00000 0 0000000000000 99# UA2005 ALLCLEAN 100# UA2005 OTHERW 101# UA2005 NORMALW 102# UA2005 INVALW 103 104{ 105 RDWIM 10 rd:5 101010 00000 0 0000000000000 106 RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 107} 108RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 109RDPR_tstate 10 rd:5 101010 00010 0 0000000000000 110RDPR_tt 10 rd:5 101010 00011 0 0000000000000 111RDPR_tick 10 rd:5 101010 00100 0 0000000000000 112RDPR_tba 10 rd:5 101010 00101 0 0000000000000 113RDPR_pstate 10 rd:5 101010 00110 0 0000000000000 114RDPR_tl 10 rd:5 101010 00111 0 0000000000000 115RDPR_pil 10 rd:5 101010 01000 0 0000000000000 116RDPR_cwp 10 rd:5 101010 01001 0 0000000000000 117RDPR_cansave 10 rd:5 101010 01010 0 0000000000000 118RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 119RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 120RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 121RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 122RDPR_gl 10 rd:5 101010 10000 0 0000000000000 123RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 124RDPR_ver 10 rd:5 101010 11111 0 0000000000000 125 126{ 127 WRWIM 10 00000 110010 ..... . ............. @n_r_ri 128 WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri 129} 130WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri 131WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri 132WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri 133WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri 134WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri 135WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri 136WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri 137WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri 138WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri 139WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri 140WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri 141WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri 142WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri 143WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri 144WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri 145WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri 146 147{ 148 FLUSHW 10 00000 101011 00000 0 0000000000000 149 RDTBR 10 rd:5 101011 00000 0 0000000000000 150} 151 152{ 153 WRTBR 10 00000 110011 ..... . ............. @n_r_ri 154 WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri 155} 156WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri 157WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri 158WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri 159WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri 160 161ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc 162AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc 163OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc 164XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc 165SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc 166ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc 167ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc 168XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc 169ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc 170SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc 171 172MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 173UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc 174SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc 175MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1 176 177UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 178SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 179UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc 180SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc 181 182TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1 183TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1 184TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 185TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 186 187POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \ 188 &r_r_ri_cc rs1=0 cc=0 189 190&shiftr rd rs1 rs2 x:bool 191@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr 192 193SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr 194SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr 195SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr 196 197&shifti rd rs1 i x:bool 198@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti 199 200SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti 201SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti 202SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti 203 204Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 205{ 206 # For v7, the entire simm13 field is present, but masked to 7 bits. 207 # For v8, [12:7] are reserved. However, a compatibility note for 208 # the Tcc insn in the v9 manual suggests that the v8 reserved field 209 # was ignored and did not produce traps. 210 Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7 211 212 # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0). 213 # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. 214 Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 215} 216 217MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 218MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 219MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 220 221JMPL 10 ..... 111000 ..... . ............. @r_r_ri 222{ 223 RETT 10 00000 111001 ..... . ............. @n_r_ri 224 RETURN 10 00000 111001 ..... . ............. @n_r_ri 225} 226 227NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 228NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 229 230NCP 11 ----- 110000 ----- --------- ----- # v8 LDC 231NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR 232NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC 233NCP 11 ----- 110100 ----- --------- ----- # v8 STC 234NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR 235NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ 236NCP 11 ----- 110111 ----- --------- ----- # v8 STDC 237