1 /* 2 * FPU op helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "fpu/softfloat.h" 25 26 static inline float128 f128_in(Int128 i) 27 { 28 union { 29 Int128 i; 30 float128 f; 31 } u; 32 33 u.i = i; 34 return u.f; 35 } 36 37 static inline Int128 f128_ret(float128 f) 38 { 39 union { 40 Int128 i; 41 float128 f; 42 } u; 43 44 u.f = f; 45 return u.i; 46 } 47 48 static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) 49 { 50 target_ulong status = get_float_exception_flags(&env->fp_status); 51 target_ulong fsr = env->fsr; 52 53 if (unlikely(status)) { 54 /* Keep exception flags clear for next time. */ 55 set_float_exception_flags(0, &env->fp_status); 56 57 /* Copy IEEE 754 flags into FSR */ 58 if (status & float_flag_invalid) { 59 fsr |= FSR_NVC; 60 } 61 if (status & float_flag_overflow) { 62 fsr |= FSR_OFC; 63 } 64 if (status & float_flag_underflow) { 65 fsr |= FSR_UFC; 66 } 67 if (status & float_flag_divbyzero) { 68 fsr |= FSR_DZC; 69 } 70 if (status & float_flag_inexact) { 71 fsr |= FSR_NXC; 72 } 73 74 if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { 75 CPUState *cs = env_cpu(env); 76 77 /* Unmasked exception, generate a trap. Note that while 78 the helper is marked as NO_WG, we can get away with 79 writing to cpu state along the exception path, since 80 TCG generated code will never see the write. */ 81 env->fsr = fsr | FSR_FTT_IEEE_EXCP; 82 cs->exception_index = TT_FP_EXCP; 83 cpu_loop_exit_restore(cs, ra); 84 } else { 85 /* Accumulate exceptions */ 86 fsr |= (fsr & FSR_CEXC_MASK) << 5; 87 } 88 } 89 90 return fsr; 91 } 92 93 target_ulong helper_check_ieee_exceptions(CPUSPARCState *env) 94 { 95 return do_check_ieee_exceptions(env, GETPC()); 96 } 97 98 #define F_BINOP(name) \ 99 float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ 100 float32 src2) \ 101 { \ 102 return float32_ ## name (src1, src2, &env->fp_status); \ 103 } \ 104 float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ 105 float64 src2) \ 106 { \ 107 return float64_ ## name (src1, src2, &env->fp_status); \ 108 } \ 109 Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ 110 Int128 src2) \ 111 { \ 112 return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ 113 &env->fp_status)); \ 114 } 115 116 F_BINOP(add); 117 F_BINOP(sub); 118 F_BINOP(mul); 119 F_BINOP(div); 120 #undef F_BINOP 121 122 float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2) 123 { 124 return float64_mul(float32_to_float64(src1, &env->fp_status), 125 float32_to_float64(src2, &env->fp_status), 126 &env->fp_status); 127 } 128 129 Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) 130 { 131 return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status), 132 float64_to_float128(src2, &env->fp_status), 133 &env->fp_status)); 134 } 135 136 /* Integer to float conversion. */ 137 float32 helper_fitos(CPUSPARCState *env, int32_t src) 138 { 139 return int32_to_float32(src, &env->fp_status); 140 } 141 142 float64 helper_fitod(CPUSPARCState *env, int32_t src) 143 { 144 return int32_to_float64(src, &env->fp_status); 145 } 146 147 Int128 helper_fitoq(CPUSPARCState *env, int32_t src) 148 { 149 return f128_ret(int32_to_float128(src, &env->fp_status)); 150 } 151 152 #ifdef TARGET_SPARC64 153 float32 helper_fxtos(CPUSPARCState *env, int64_t src) 154 { 155 return int64_to_float32(src, &env->fp_status); 156 } 157 158 float64 helper_fxtod(CPUSPARCState *env, int64_t src) 159 { 160 return int64_to_float64(src, &env->fp_status); 161 } 162 163 Int128 helper_fxtoq(CPUSPARCState *env, int64_t src) 164 { 165 return f128_ret(int64_to_float128(src, &env->fp_status)); 166 } 167 #endif 168 169 /* floating point conversion */ 170 float32 helper_fdtos(CPUSPARCState *env, float64 src) 171 { 172 return float64_to_float32(src, &env->fp_status); 173 } 174 175 float64 helper_fstod(CPUSPARCState *env, float32 src) 176 { 177 return float32_to_float64(src, &env->fp_status); 178 } 179 180 float32 helper_fqtos(CPUSPARCState *env, Int128 src) 181 { 182 return float128_to_float32(f128_in(src), &env->fp_status); 183 } 184 185 Int128 helper_fstoq(CPUSPARCState *env, float32 src) 186 { 187 return f128_ret(float32_to_float128(src, &env->fp_status)); 188 } 189 190 float64 helper_fqtod(CPUSPARCState *env, Int128 src) 191 { 192 return float128_to_float64(f128_in(src), &env->fp_status); 193 } 194 195 Int128 helper_fdtoq(CPUSPARCState *env, float64 src) 196 { 197 return f128_ret(float64_to_float128(src, &env->fp_status)); 198 } 199 200 /* Float to integer conversion. */ 201 int32_t helper_fstoi(CPUSPARCState *env, float32 src) 202 { 203 return float32_to_int32_round_to_zero(src, &env->fp_status); 204 } 205 206 int32_t helper_fdtoi(CPUSPARCState *env, float64 src) 207 { 208 return float64_to_int32_round_to_zero(src, &env->fp_status); 209 } 210 211 int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) 212 { 213 return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); 214 } 215 216 #ifdef TARGET_SPARC64 217 int64_t helper_fstox(CPUSPARCState *env, float32 src) 218 { 219 return float32_to_int64_round_to_zero(src, &env->fp_status); 220 } 221 222 int64_t helper_fdtox(CPUSPARCState *env, float64 src) 223 { 224 return float64_to_int64_round_to_zero(src, &env->fp_status); 225 } 226 227 int64_t helper_fqtox(CPUSPARCState *env, Int128 src) 228 { 229 return float128_to_int64_round_to_zero(f128_in(src), &env->fp_status); 230 } 231 #endif 232 233 float32 helper_fsqrts(CPUSPARCState *env, float32 src) 234 { 235 return float32_sqrt(src, &env->fp_status); 236 } 237 238 float64 helper_fsqrtd(CPUSPARCState *env, float64 src) 239 { 240 return float64_sqrt(src, &env->fp_status); 241 } 242 243 Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) 244 { 245 return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); 246 } 247 248 #define GEN_FCMP(name, size, FS, E) \ 249 target_ulong glue(helper_, name) (CPUSPARCState *env, \ 250 Int128 src1, Int128 src2) \ 251 { \ 252 float128 reg1 = f128_in(src1); \ 253 float128 reg2 = f128_in(src2); \ 254 FloatRelation ret; \ 255 target_ulong fsr; \ 256 if (E) { \ 257 ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \ 258 } else { \ 259 ret = glue(size, _compare_quiet)(reg1, reg2, \ 260 &env->fp_status); \ 261 } \ 262 fsr = do_check_ieee_exceptions(env, GETPC()); \ 263 switch (ret) { \ 264 case float_relation_unordered: \ 265 fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ 266 fsr |= FSR_NVA; \ 267 break; \ 268 case float_relation_less: \ 269 fsr &= ~(FSR_FCC1) << FS; \ 270 fsr |= FSR_FCC0 << FS; \ 271 break; \ 272 case float_relation_greater: \ 273 fsr &= ~(FSR_FCC0) << FS; \ 274 fsr |= FSR_FCC1 << FS; \ 275 break; \ 276 default: \ 277 fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ 278 break; \ 279 } \ 280 return fsr; \ 281 } 282 #define GEN_FCMP_T(name, size, FS, E) \ 283 target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\ 284 { \ 285 FloatRelation ret; \ 286 target_ulong fsr; \ 287 if (E) { \ 288 ret = glue(size, _compare)(src1, src2, &env->fp_status); \ 289 } else { \ 290 ret = glue(size, _compare_quiet)(src1, src2, \ 291 &env->fp_status); \ 292 } \ 293 fsr = do_check_ieee_exceptions(env, GETPC()); \ 294 switch (ret) { \ 295 case float_relation_unordered: \ 296 fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ 297 break; \ 298 case float_relation_less: \ 299 fsr &= ~(FSR_FCC1 << FS); \ 300 fsr |= FSR_FCC0 << FS; \ 301 break; \ 302 case float_relation_greater: \ 303 fsr &= ~(FSR_FCC0 << FS); \ 304 fsr |= FSR_FCC1 << FS; \ 305 break; \ 306 default: \ 307 fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ 308 break; \ 309 } \ 310 return fsr; \ 311 } 312 313 GEN_FCMP_T(fcmps, float32, 0, 0); 314 GEN_FCMP_T(fcmpd, float64, 0, 0); 315 316 GEN_FCMP_T(fcmpes, float32, 0, 1); 317 GEN_FCMP_T(fcmped, float64, 0, 1); 318 319 GEN_FCMP(fcmpq, float128, 0, 0); 320 GEN_FCMP(fcmpeq, float128, 0, 1); 321 322 #ifdef TARGET_SPARC64 323 GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); 324 GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); 325 GEN_FCMP(fcmpq_fcc1, float128, 22, 0); 326 327 GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); 328 GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); 329 GEN_FCMP(fcmpq_fcc2, float128, 24, 0); 330 331 GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); 332 GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); 333 GEN_FCMP(fcmpq_fcc3, float128, 26, 0); 334 335 GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); 336 GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); 337 GEN_FCMP(fcmpeq_fcc1, float128, 22, 1); 338 339 GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); 340 GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); 341 GEN_FCMP(fcmpeq_fcc2, float128, 24, 1); 342 343 GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); 344 GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); 345 GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); 346 #endif 347 #undef GEN_FCMP_T 348 #undef GEN_FCMP 349 350 static void set_fsr(CPUSPARCState *env, target_ulong fsr) 351 { 352 int rnd_mode; 353 354 switch (fsr & FSR_RD_MASK) { 355 case FSR_RD_NEAREST: 356 rnd_mode = float_round_nearest_even; 357 break; 358 default: 359 case FSR_RD_ZERO: 360 rnd_mode = float_round_to_zero; 361 break; 362 case FSR_RD_POS: 363 rnd_mode = float_round_up; 364 break; 365 case FSR_RD_NEG: 366 rnd_mode = float_round_down; 367 break; 368 } 369 set_float_rounding_mode(rnd_mode, &env->fp_status); 370 } 371 372 void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) 373 { 374 set_fsr(env, fsr); 375 } 376