1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 /* 10 * From Oracle SPARC Architecture 2015: 11 * 12 * Compatibility notes: The PSO memory model described in SPARC V8 and 13 * SPARC V9 compatibility architecture specifications was never implemented 14 * in a SPARC V9 implementation and is not included in the Oracle SPARC 15 * Architecture specification. 16 * 17 * The RMO memory model described in the SPARC V9 specification was 18 * implemented in some non-Sun SPARC V9 implementations, but is not 19 * directly supported in Oracle SPARC Architecture 2015 implementations. 20 * 21 * Therefore always use TSO in QEMU. 22 * 23 * D.5 Specification of Partial Store Order (PSO) 24 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 25 * 26 * D.6 Specification of Total Store Order (TSO) 27 * ... PSO with the additional requirement that all [stores] are followed 28 * by an implied MEMBAR #StoreStore. 29 */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 31 32 #if !defined(TARGET_SPARC64) 33 #define TARGET_DPREGS 16 34 #else 35 #define TARGET_DPREGS 32 36 #endif 37 38 /*#define EXCP_INTERRUPT 0x100*/ 39 40 /* Windowed register indexes. */ 41 enum { 42 WREG_O0, 43 WREG_O1, 44 WREG_O2, 45 WREG_O3, 46 WREG_O4, 47 WREG_O5, 48 WREG_O6, 49 WREG_O7, 50 51 WREG_L0, 52 WREG_L1, 53 WREG_L2, 54 WREG_L3, 55 WREG_L4, 56 WREG_L5, 57 WREG_L6, 58 WREG_L7, 59 60 WREG_I0, 61 WREG_I1, 62 WREG_I2, 63 WREG_I3, 64 WREG_I4, 65 WREG_I5, 66 WREG_I6, 67 WREG_I7, 68 69 WREG_SP = WREG_O6, 70 WREG_FP = WREG_I6, 71 }; 72 73 /* trap definitions */ 74 #ifndef TARGET_SPARC64 75 #define TT_TFAULT 0x01 76 #define TT_ILL_INSN 0x02 77 #define TT_PRIV_INSN 0x03 78 #define TT_NFPU_INSN 0x04 79 #define TT_WIN_OVF 0x05 80 #define TT_WIN_UNF 0x06 81 #define TT_UNALIGNED 0x07 82 #define TT_FP_EXCP 0x08 83 #define TT_DFAULT 0x09 84 #define TT_TOVF 0x0a 85 #define TT_EXTINT 0x10 86 #define TT_CODE_ACCESS 0x21 87 #define TT_UNIMP_FLUSH 0x25 88 #define TT_DATA_ACCESS 0x29 89 #define TT_DIV_ZERO 0x2a 90 #define TT_NCP_INSN 0x24 91 #define TT_TRAP 0x80 92 #else 93 #define TT_POWER_ON_RESET 0x01 94 #define TT_TFAULT 0x08 95 #define TT_CODE_ACCESS 0x0a 96 #define TT_ILL_INSN 0x10 97 #define TT_UNIMP_FLUSH TT_ILL_INSN 98 #define TT_PRIV_INSN 0x11 99 #define TT_NFPU_INSN 0x20 100 #define TT_FP_EXCP 0x21 101 #define TT_TOVF 0x23 102 #define TT_CLRWIN 0x24 103 #define TT_DIV_ZERO 0x28 104 #define TT_DFAULT 0x30 105 #define TT_DATA_ACCESS 0x32 106 #define TT_UNALIGNED 0x34 107 #define TT_PRIV_ACT 0x37 108 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 109 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 110 #define TT_EXTINT 0x40 111 #define TT_IVEC 0x60 112 #define TT_TMISS 0x64 113 #define TT_DMISS 0x68 114 #define TT_DPROT 0x6c 115 #define TT_SPILL 0x80 116 #define TT_FILL 0xc0 117 #define TT_WOTHER (1 << 5) 118 #define TT_TRAP 0x100 119 #define TT_HTRAP 0x180 120 #endif 121 122 #define PSR_NEG_SHIFT 23 123 #define PSR_NEG (1 << PSR_NEG_SHIFT) 124 #define PSR_ZERO_SHIFT 22 125 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 126 #define PSR_OVF_SHIFT 21 127 #define PSR_OVF (1 << PSR_OVF_SHIFT) 128 #define PSR_CARRY_SHIFT 20 129 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 130 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 131 #if !defined(TARGET_SPARC64) 132 #define PSR_EF (1<<12) 133 #define PSR_PIL 0xf00 134 #define PSR_S (1<<7) 135 #define PSR_PS (1<<6) 136 #define PSR_ET (1<<5) 137 #define PSR_CWP 0x1f 138 #endif 139 140 /* Trap base register */ 141 #define TBR_BASE_MASK 0xfffff000 142 143 #if defined(TARGET_SPARC64) 144 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 145 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 146 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 147 #define PS_CLE (1<<9) /* UA2007 */ 148 #define PS_TLE (1<<8) /* UA2007 */ 149 #define PS_RMO (1<<7) 150 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 151 #define PS_PEF (1<<4) /* enable fpu */ 152 #define PS_AM (1<<3) /* address mask */ 153 #define PS_PRIV (1<<2) 154 #define PS_IE (1<<1) 155 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 156 157 #define FPRS_DL (1 << 0) 158 #define FPRS_DU (1 << 1) 159 #define FPRS_FEF (1 << 2) 160 161 #define HS_PRIV (1<<2) 162 #endif 163 164 /* Fcc */ 165 #define FSR_RD1 (1ULL << 31) 166 #define FSR_RD0 (1ULL << 30) 167 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 168 #define FSR_RD_NEAREST 0 169 #define FSR_RD_ZERO FSR_RD0 170 #define FSR_RD_POS FSR_RD1 171 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 172 173 #define FSR_NVM (1ULL << 27) 174 #define FSR_OFM (1ULL << 26) 175 #define FSR_UFM (1ULL << 25) 176 #define FSR_DZM (1ULL << 24) 177 #define FSR_NXM (1ULL << 23) 178 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 179 180 #define FSR_NVA (1ULL << 9) 181 #define FSR_OFA (1ULL << 8) 182 #define FSR_UFA (1ULL << 7) 183 #define FSR_DZA (1ULL << 6) 184 #define FSR_NXA (1ULL << 5) 185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 186 187 #define FSR_NVC (1ULL << 4) 188 #define FSR_OFC (1ULL << 3) 189 #define FSR_UFC (1ULL << 2) 190 #define FSR_DZC (1ULL << 1) 191 #define FSR_NXC (1ULL << 0) 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 193 194 #define FSR_VER_SHIFT 17 195 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 196 197 #define FSR_FTT2 (1ULL << 16) 198 #define FSR_FTT1 (1ULL << 15) 199 #define FSR_FTT0 (1ULL << 14) 200 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 201 #ifdef TARGET_SPARC64 202 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 203 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 204 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 205 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 206 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 207 #else 208 #define FSR_FTT_NMASK 0xfffe3fffULL 209 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 210 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 211 #endif 212 #define FSR_LDFSR_MASK 0xcfc00fffULL 213 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 214 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 215 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 216 #define FSR_FTT_INVAL_FPR (6ULL << 14) 217 218 #define FSR_FCC1_SHIFT 11 219 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 220 #define FSR_FCC0_SHIFT 10 221 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 222 223 /* MMU */ 224 #define MMU_E (1<<0) 225 #define MMU_NF (1<<1) 226 227 #define PTE_ENTRYTYPE_MASK 3 228 #define PTE_ACCESS_MASK 0x1c 229 #define PTE_ACCESS_SHIFT 2 230 #define PTE_PPN_SHIFT 7 231 #define PTE_ADDR_MASK 0xffffff00 232 233 #define PG_ACCESSED_BIT 5 234 #define PG_MODIFIED_BIT 6 235 #define PG_CACHE_BIT 7 236 237 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 238 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 239 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 240 241 /* 3 <= NWINDOWS <= 32. */ 242 #define MIN_NWINDOWS 3 243 #define MAX_NWINDOWS 32 244 245 #ifdef TARGET_SPARC64 246 typedef struct trap_state { 247 uint64_t tpc; 248 uint64_t tnpc; 249 uint64_t tstate; 250 uint32_t tt; 251 } trap_state; 252 #endif 253 #define TARGET_INSN_START_EXTRA_WORDS 1 254 255 typedef struct sparc_def_t { 256 const char *name; 257 target_ulong iu_version; 258 uint32_t fpu_version; 259 uint32_t mmu_version; 260 uint32_t mmu_bm; 261 uint32_t mmu_ctpr_mask; 262 uint32_t mmu_cxr_mask; 263 uint32_t mmu_sfsr_mask; 264 uint32_t mmu_trcr_mask; 265 uint32_t mxcc_version; 266 uint32_t features; 267 uint32_t nwindows; 268 uint32_t maxtl; 269 } sparc_def_t; 270 271 #define FEATURE(X) CPU_FEATURE_BIT_##X, 272 enum { 273 #include "cpu-feature.h.inc" 274 }; 275 276 #undef FEATURE 277 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 278 279 enum { 280 #include "cpu-feature.h.inc" 281 }; 282 283 #undef FEATURE 284 285 #ifndef TARGET_SPARC64 286 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 287 CPU_FEATURE_FSMULD) 288 #else 289 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 290 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 291 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 292 enum { 293 mmu_us_12, // Ultrasparc < III (64 entry TLB) 294 mmu_us_3, // Ultrasparc III (512 entry TLB) 295 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 296 mmu_sun4v, // T1, T2 297 }; 298 #endif 299 300 #define TTE_VALID_BIT (1ULL << 63) 301 #define TTE_NFO_BIT (1ULL << 60) 302 #define TTE_IE_BIT (1ULL << 59) 303 #define TTE_USED_BIT (1ULL << 41) 304 #define TTE_LOCKED_BIT (1ULL << 6) 305 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 306 #define TTE_PRIV_BIT (1ULL << 2) 307 #define TTE_W_OK_BIT (1ULL << 1) 308 #define TTE_GLOBAL_BIT (1ULL << 0) 309 310 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 311 #define TTE_USED_BIT_UA2005 (1ULL << 47) 312 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 313 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 314 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 315 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 316 317 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 318 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 319 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 320 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 321 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 322 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 323 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 324 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 325 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 326 327 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 328 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 329 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 330 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 331 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 332 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 333 334 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 335 336 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 337 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 338 339 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 340 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 341 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 342 343 /* UltraSPARC T1 specific */ 344 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 345 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 346 347 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 348 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 349 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 350 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 351 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 352 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 353 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 354 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 355 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 356 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 357 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 358 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 359 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 360 361 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 362 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 363 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 364 #define SFSR_CT_SECONDARY (1ULL << 4) 365 #define SFSR_CT_NUCLEUS (2ULL << 4) 366 #define SFSR_CT_NOTRANS (3ULL << 4) 367 #define SFSR_CT_MASK (3ULL << 4) 368 369 /* Leon3 cache control */ 370 371 /* Cache control: emulate the behavior of cache control registers but without 372 any effect on the emulated */ 373 374 #define CACHE_STATE_MASK 0x3 375 #define CACHE_DISABLED 0x0 376 #define CACHE_FROZEN 0x1 377 #define CACHE_ENABLED 0x3 378 379 /* Cache Control register fields */ 380 381 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 382 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 383 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 384 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 385 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 386 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 387 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 388 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 389 390 #define CONVERT_BIT(X, SRC, DST) \ 391 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 392 393 typedef struct SparcTLBEntry { 394 uint64_t tag; 395 uint64_t tte; 396 } SparcTLBEntry; 397 398 struct CPUTimer 399 { 400 const char *name; 401 uint32_t frequency; 402 uint32_t disabled; 403 uint64_t disabled_mask; 404 uint32_t npt; 405 uint64_t npt_mask; 406 int64_t clock_offset; 407 QEMUTimer *qtimer; 408 }; 409 410 typedef struct CPUTimer CPUTimer; 411 412 typedef struct CPUArchState CPUSPARCState; 413 #if defined(TARGET_SPARC64) 414 typedef union { 415 uint64_t mmuregs[16]; 416 struct { 417 uint64_t tsb_tag_target; 418 uint64_t mmu_primary_context; 419 uint64_t mmu_secondary_context; 420 uint64_t sfsr; 421 uint64_t sfar; 422 uint64_t tsb; 423 uint64_t tag_access; 424 uint64_t virtual_watchpoint; 425 uint64_t physical_watchpoint; 426 uint64_t sun4v_ctx_config[2]; 427 uint64_t sun4v_tsb_pointers[4]; 428 }; 429 } SparcV9MMU; 430 #endif 431 struct CPUArchState { 432 target_ulong gregs[8]; /* general registers */ 433 target_ulong *regwptr; /* pointer to current register window */ 434 target_ulong pc; /* program counter */ 435 target_ulong npc; /* next program counter */ 436 target_ulong y; /* multiply/divide register */ 437 438 /* 439 * Bit 31 is for icc, bit 63 for xcc. 440 * Other bits are garbage. 441 */ 442 target_long cc_N; 443 target_long cc_V; 444 445 /* 446 * Z is represented as == 0; any non-zero value is !Z. 447 * For sparc64, the high 32-bits of icc.Z are garbage. 448 */ 449 target_ulong icc_Z; 450 #ifdef TARGET_SPARC64 451 target_ulong xcc_Z; 452 #endif 453 454 /* 455 * For sparc32, icc.C is boolean. 456 * For sparc64, xcc.C is boolean; 457 * icc.C is bit 32 with other bits garbage. 458 */ 459 target_ulong icc_C; 460 #ifdef TARGET_SPARC64 461 target_ulong xcc_C; 462 #endif 463 464 target_ulong cond; /* conditional branch result (XXX: save it in a 465 temporary register when possible) */ 466 467 target_ulong fsr; /* FPU state register */ 468 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 469 uint32_t cwp; /* index of current register window (extracted 470 from PSR) */ 471 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 472 uint32_t wim; /* window invalid mask */ 473 #endif 474 target_ulong tbr; /* trap base register */ 475 #if !defined(TARGET_SPARC64) 476 int psrs; /* supervisor mode (extracted from PSR) */ 477 int psrps; /* previous supervisor mode */ 478 int psret; /* enable traps */ 479 #endif 480 uint32_t psrpil; /* interrupt blocking level */ 481 uint32_t pil_in; /* incoming interrupt level bitmap */ 482 #if !defined(TARGET_SPARC64) 483 int psref; /* enable fpu */ 484 #endif 485 int interrupt_index; 486 /* NOTE: we allow 8 more registers to handle wrapping */ 487 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 488 489 /* Fields up to this point are cleared by a CPU reset */ 490 struct {} end_reset_fields; 491 492 /* Fields from here on are preserved across CPU reset. */ 493 target_ulong version; 494 uint32_t nwindows; 495 496 /* MMU regs */ 497 #if defined(TARGET_SPARC64) 498 uint64_t lsu; 499 #define DMMU_E 0x8 500 #define IMMU_E 0x4 501 SparcV9MMU immu; 502 SparcV9MMU dmmu; 503 SparcTLBEntry itlb[64]; 504 SparcTLBEntry dtlb[64]; 505 uint32_t mmu_version; 506 #else 507 uint32_t mmuregs[32]; 508 uint64_t mxccdata[4]; 509 uint64_t mxccregs[8]; 510 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 511 uint64_t mmubpaction; 512 uint64_t mmubpregs[4]; 513 uint64_t prom_addr; 514 #endif 515 float_status fp_status; 516 #if defined(TARGET_SPARC64) 517 #define MAXTL_MAX 8 518 #define MAXTL_MASK (MAXTL_MAX - 1) 519 trap_state ts[MAXTL_MAX]; 520 uint32_t asi; 521 uint32_t pstate; 522 uint32_t tl; 523 uint32_t maxtl; 524 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 525 uint64_t agregs[8]; /* alternate general registers */ 526 uint64_t bgregs[8]; /* backup for normal global registers */ 527 uint64_t igregs[8]; /* interrupt general registers */ 528 uint64_t mgregs[8]; /* mmu general registers */ 529 uint64_t glregs[8 * MAXTL_MAX]; 530 uint32_t fprs; 531 uint64_t tick_cmpr, stick_cmpr; 532 CPUTimer *tick, *stick; 533 #define TICK_NPT_MASK 0x8000000000000000ULL 534 #define TICK_INT_DIS 0x8000000000000000ULL 535 uint64_t gsr; 536 uint32_t gl; // UA2005 537 /* UA 2005 hyperprivileged registers */ 538 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 539 uint64_t scratch[8]; 540 CPUTimer *hstick; // UA 2005 541 /* Interrupt vector registers */ 542 uint64_t ivec_status; 543 uint64_t ivec_data[3]; 544 uint32_t softint; 545 #define SOFTINT_TIMER 1 546 #define SOFTINT_STIMER (1 << 16) 547 #define SOFTINT_INTRMASK (0xFFFE) 548 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 549 #endif 550 sparc_def_t def; 551 552 void *irq_manager; 553 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 554 555 /* Leon3 cache control */ 556 uint32_t cache_control; 557 }; 558 559 /** 560 * SPARCCPU: 561 * @env: #CPUSPARCState 562 * 563 * A SPARC CPU. 564 */ 565 struct ArchCPU { 566 CPUState parent_obj; 567 568 CPUSPARCState env; 569 }; 570 571 /** 572 * SPARCCPUClass: 573 * @parent_realize: The parent class' realize handler. 574 * @parent_phases: The parent class' reset phase handlers. 575 * 576 * A SPARC CPU model. 577 */ 578 struct SPARCCPUClass { 579 CPUClass parent_class; 580 581 DeviceRealize parent_realize; 582 ResettablePhases parent_phases; 583 sparc_def_t *cpu_def; 584 }; 585 586 #ifndef CONFIG_USER_ONLY 587 extern const VMStateDescription vmstate_sparc_cpu; 588 589 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 590 #endif 591 592 void sparc_cpu_do_interrupt(CPUState *cpu); 593 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 594 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 595 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 596 MMUAccessType access_type, 597 int mmu_idx, 598 uintptr_t retaddr); 599 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 600 601 /* cpu_init.c */ 602 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 603 void sparc_cpu_list(void); 604 /* mmu_helper.c */ 605 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 606 MMUAccessType access_type, int mmu_idx, 607 bool probe, uintptr_t retaddr); 608 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 609 void dump_mmu(CPUSPARCState *env); 610 611 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 612 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 613 uint8_t *buf, int len, bool is_write); 614 #endif 615 616 617 /* translate.c */ 618 void sparc_tcg_init(void); 619 void sparc_restore_state_to_opc(CPUState *cs, 620 const TranslationBlock *tb, 621 const uint64_t *data); 622 623 /* fop_helper.c */ 624 target_ulong cpu_get_fsr(CPUSPARCState *); 625 void cpu_put_fsr(CPUSPARCState *, target_ulong); 626 627 /* win_helper.c */ 628 target_ulong cpu_get_psr(CPUSPARCState *env1); 629 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 630 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 631 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 632 #ifdef TARGET_SPARC64 633 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 634 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 635 #endif 636 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 637 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 638 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 639 640 /* sun4m.c, sun4u.c */ 641 void cpu_check_irqs(CPUSPARCState *env); 642 643 #if defined (TARGET_SPARC64) 644 645 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 646 { 647 return (x & mask) == (y & mask); 648 } 649 650 #define MMU_CONTEXT_BITS 13 651 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 652 653 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 654 uint64_t context) 655 { 656 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 657 } 658 659 #endif 660 661 /* cpu-exec.c */ 662 #if !defined(CONFIG_USER_ONLY) 663 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 664 vaddr addr, unsigned size, 665 MMUAccessType access_type, 666 int mmu_idx, MemTxAttrs attrs, 667 MemTxResult response, uintptr_t retaddr); 668 #if defined(TARGET_SPARC64) 669 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 670 int mmu_idx); 671 #endif 672 #endif 673 674 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 675 676 #define cpu_list sparc_cpu_list 677 678 /* MMU modes definitions */ 679 #if defined (TARGET_SPARC64) 680 #define MMU_USER_IDX 0 681 #define MMU_USER_SECONDARY_IDX 1 682 #define MMU_KERNEL_IDX 2 683 #define MMU_KERNEL_SECONDARY_IDX 3 684 #define MMU_NUCLEUS_IDX 4 685 #define MMU_PHYS_IDX 5 686 #else 687 #define MMU_USER_IDX 0 688 #define MMU_KERNEL_IDX 1 689 #define MMU_PHYS_IDX 2 690 #endif 691 692 #if defined (TARGET_SPARC64) 693 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 694 { 695 return env1->def.features & CPU_FEATURE_HYPV; 696 } 697 698 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 699 { 700 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 701 } 702 703 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 704 { 705 return env1->pstate & PS_PRIV; 706 } 707 #else 708 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 709 { 710 return env1->psrs; 711 } 712 #endif 713 714 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 715 { 716 #if !defined (TARGET_SPARC64) 717 if (env1->psret != 0) 718 return 1; 719 #else 720 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 721 return 1; 722 } 723 #endif 724 725 return 0; 726 } 727 728 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 729 { 730 #if !defined(TARGET_SPARC64) 731 /* level 15 is non-maskable on sparc v8 */ 732 return pil == 15 || pil > env1->psrpil; 733 #else 734 return pil > env1->psrpil; 735 #endif 736 } 737 738 #include "exec/cpu-all.h" 739 740 #ifdef TARGET_SPARC64 741 /* sun4u.c */ 742 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 743 uint64_t cpu_tick_get_count(CPUTimer *timer); 744 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 745 trap_state* cpu_tsptr(CPUSPARCState* env); 746 #endif 747 748 #define TB_FLAG_MMU_MASK 7 749 #define TB_FLAG_FPU_ENABLED (1 << 4) 750 #define TB_FLAG_AM_ENABLED (1 << 5) 751 #define TB_FLAG_SUPER (1 << 6) 752 #define TB_FLAG_HYPER (1 << 7) 753 #define TB_FLAG_ASI_SHIFT 24 754 755 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 756 uint64_t *cs_base, uint32_t *pflags) 757 { 758 uint32_t flags; 759 *pc = env->pc; 760 *cs_base = env->npc; 761 flags = cpu_mmu_index(env_cpu(env), false); 762 #ifndef CONFIG_USER_ONLY 763 if (cpu_supervisor_mode(env)) { 764 flags |= TB_FLAG_SUPER; 765 } 766 #endif 767 #ifdef TARGET_SPARC64 768 #ifndef CONFIG_USER_ONLY 769 if (cpu_hypervisor_mode(env)) { 770 flags |= TB_FLAG_HYPER; 771 } 772 #endif 773 if (env->pstate & PS_AM) { 774 flags |= TB_FLAG_AM_ENABLED; 775 } 776 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 777 flags |= TB_FLAG_FPU_ENABLED; 778 } 779 flags |= env->asi << TB_FLAG_ASI_SHIFT; 780 #else 781 if (env->psref) { 782 flags |= TB_FLAG_FPU_ENABLED; 783 } 784 #endif 785 *pflags = flags; 786 } 787 788 static inline bool tb_fpu_enabled(int tb_flags) 789 { 790 #if defined(CONFIG_USER_ONLY) 791 return true; 792 #else 793 return tb_flags & TB_FLAG_FPU_ENABLED; 794 #endif 795 } 796 797 static inline bool tb_am_enabled(int tb_flags) 798 { 799 #ifndef TARGET_SPARC64 800 return false; 801 #else 802 return tb_flags & TB_FLAG_AM_ENABLED; 803 #endif 804 } 805 806 #ifdef TARGET_SPARC64 807 /* win_helper.c */ 808 target_ulong cpu_get_ccr(CPUSPARCState *env1); 809 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 810 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 811 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 812 813 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 814 { 815 uint64_t tstate = (cpu_get_ccr(env) << 32) | 816 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 817 cpu_get_cwp64(env); 818 819 if (env->def.features & CPU_FEATURE_GL) { 820 tstate |= (env->gl & 7ULL) << 40; 821 } 822 return tstate; 823 } 824 #endif 825 826 #endif 827